hw/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "pc.h"
  27 #include "nvram.h"
  28 #include "fdc.h"
  29 #include "net.h"
  30 #include "qemu-timer.h"
  31 #include "sysemu.h"
  32 #include "boards.h"
  33 #include "firmware_abi.h"
  34 #include "fw_cfg.h"
  35 #include "sysbus.h"
  36
  37 //#define DEBUG_IRQ
  38
  39 #ifdef DEBUG_IRQ
  40 #define DPRINTF(fmt, ...)                                       \
  41     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  42 #else
  43 #define DPRINTF(fmt, ...)
  44 #endif
  45
  46 #define KERNEL_LOAD_ADDR     0x00404000
  47 #define CMDLINE_ADDR         0x003ff000
  48 #define INITRD_LOAD_ADDR     0x00300000
  49 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  50 #define PROM_VADDR           0x000ffd00000ULL
  51 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  52 #define APB_MEM_BASE         0x1ff00000000ULL
  53 #define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
  54 #define PROM_FILENAME        "openbios-sparc64"
  55 #define NVRAM_SIZE           0x2000
  56 #define MAX_IDE_BUS          2
  57 #define BIOS_CFG_IOPORT      0x510
  58 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
  59 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
  60 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
  61
  62 #define MAX_PILS 16
  63
  64 #define TICK_INT_DIS         0x8000000000000000ULL
  65 #define TICK_MAX             0x7fffffffffffffffULL
  66
  67 struct hwdef {
  68     const char * const default_cpu_model;
  69     uint16_t machine_id;
  70     uint64_t prom_addr;
  71     uint64_t console_serial_base;
  72 };
  73
  74 int DMA_get_channel_mode (int nchan)
  75 {
  76     return 0;
  77 }
  78 int DMA_read_memory (int nchan, void *buf, int pos, int size)
  79 {
  80     return 0;
  81 }
  82 int DMA_write_memory (int nchan, void *buf, int pos, int size)
  83 {
  84     return 0;
  85 }
  86 void DMA_hold_DREQ (int nchan) {}
  87 void DMA_release_DREQ (int nchan) {}
  88 void DMA_schedule(int nchan) {}
  89 void DMA_init (int high_page_enable) {}
  90 void DMA_register_channel (int nchan,
  91                            DMA_transfer_handler transfer_handler,
  92                            void *opaque)
  93 {
  94 }
  95
  96 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
  97 {
  98     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
  99     return 0;
 100 }
 101
 102 static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
 103                                    const char *arch,
 104                                    ram_addr_t RAM_size,
 105                                    const char *boot_devices,
 106                                    uint32_t kernel_image, uint32_t kernel_size,
 107                                    const char *cmdline,
 108                                    uint32_t initrd_image, uint32_t initrd_size,
 109                                    uint32_t NVRAM_image,
 110                                    int width, int height, int depth,
 111                                    const uint8_t *macaddr)
 112 {
 113     unsigned int i;
 114     uint32_t start, end;
 115     uint8_t image[0x1ff0];
 116     struct OpenBIOS_nvpart_v1 *part_header;
 117
 118     memset(image, '\0', sizeof(image));
 119
 120     start = 0;
 121
 122     // OpenBIOS nvram variables
 123     // Variable partition
 124     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 125     part_header->signature = OPENBIOS_PART_SYSTEM;
 126     pstrcpy(part_header->name, sizeof(part_header->name), "system");
 127
 128     end = start + sizeof(struct OpenBIOS_nvpart_v1);
 129     for (i = 0; i < nb_prom_envs; i++)
 130         end = OpenBIOS_set_var(image, end, prom_envs[i]);
 131
 132     // End marker
 133     image[end++] = '\0';
 134
 135     end = start + ((end - start + 15) & ~15);
 136     OpenBIOS_finish_partition(part_header, end - start);
 137
 138     // free partition
 139     start = end;
 140     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 141     part_header->signature = OPENBIOS_PART_FREE;
 142     pstrcpy(part_header->name, sizeof(part_header->name), "free");
 143
 144     end = 0x1fd0;
 145     OpenBIOS_finish_partition(part_header, end - start);
 146
 147     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 148
 149     for (i = 0; i < sizeof(image); i++)
 150         m48t59_write(nvram, i, image[i]);
 151
 152     return 0;
 153 }
 154 static unsigned long sun4u_load_kernel(const char *kernel_filename,
 155                                        const char *initrd_filename,
 156                                        ram_addr_t RAM_size, long *initrd_size)
 157 {
 158     int linux_boot;
 159     unsigned int i;
 160     long kernel_size;
 161
 162     linux_boot = (kernel_filename != NULL);
 163
 164     kernel_size = 0;
 165     if (linux_boot) {
 166         kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
 167         if (kernel_size < 0)
 168             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 169                                     RAM_size - KERNEL_LOAD_ADDR);
 170         if (kernel_size < 0)
 171             kernel_size = load_image_targphys(kernel_filename,
 172                                               KERNEL_LOAD_ADDR,
 173                                               RAM_size - KERNEL_LOAD_ADDR);
 174         if (kernel_size < 0) {
 175             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 176                     kernel_filename);
 177             exit(1);
 178         }
 179
 180         /* load initrd */
 181         *initrd_size = 0;
 182         if (initrd_filename) {
 183             *initrd_size = load_image_targphys(initrd_filename,
 184                                                INITRD_LOAD_ADDR,
 185                                                RAM_size - INITRD_LOAD_ADDR);
 186             if (*initrd_size < 0) {
 187                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 188                         initrd_filename);
 189                 exit(1);
 190             }
 191         }
 192         if (*initrd_size > 0) {
 193             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 194                 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
 195                     stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
 196                     stl_phys(KERNEL_LOAD_ADDR + i + 20, *initrd_size);
 197                     break;
 198                 }
 199             }
 200         }
 201     }
 202     return kernel_size;
 203 }
 204
 205 void pic_info(Monitor *mon)
 206 {
 207 }
 208
 209 void irq_info(Monitor *mon)
 210 {
 211 }
 212
 213 void cpu_check_irqs(CPUState *env)
 214 {
 215     uint32_t pil = env->pil_in | (env->softint & ~SOFTINT_TIMER) |
 216         ((env->softint & SOFTINT_TIMER) << 14);
 217
 218     if (pil && (env->interrupt_index == 0 ||
 219                 (env->interrupt_index & ~15) == TT_EXTINT)) {
 220         unsigned int i;
 221
 222         for (i = 15; i > 0; i--) {
 223             if (pil & (1 << i)) {
 224                 int old_interrupt = env->interrupt_index;
 225
 226                 env->interrupt_index = TT_EXTINT | i;
 227                 if (old_interrupt != env->interrupt_index) {
 228                     DPRINTF("Set CPU IRQ %d\n", i);
 229                     cpu_interrupt(env, CPU_INTERRUPT_HARD);
 230                 }
 231                 break;
 232             }
 233         }
 234     } else if (!pil && (env->interrupt_index & ~15) == TT_EXTINT) {
 235         DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
 236         env->interrupt_index = 0;
 237         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 238     }
 239 }
 240
 241 static void cpu_set_irq(void *opaque, int irq, int level)
 242 {
 243     CPUState *env = opaque;
 244
 245     if (level) {
 246         DPRINTF("Raise CPU IRQ %d\n", irq);
 247         env->halted = 0;
 248         env->pil_in |= 1 << irq;
 249         cpu_check_irqs(env);
 250     } else {
 251         DPRINTF("Lower CPU IRQ %d\n", irq);
 252         env->pil_in &= ~(1 << irq);
 253         cpu_check_irqs(env);
 254     }
 255 }
 256
 257 typedef struct ResetData {
 258     CPUState *env;
 259     uint64_t reset_addr;
 260 } ResetData;
 261
 262 static void main_cpu_reset(void *opaque)
 263 {
 264     ResetData *s = (ResetData *)opaque;
 265     CPUState *env = s->env;
 266
 267     cpu_reset(env);
 268     env->tick_cmpr = TICK_INT_DIS | 0;
 269     ptimer_set_limit(env->tick, TICK_MAX, 1);
 270     ptimer_run(env->tick, 1);
 271     env->stick_cmpr = TICK_INT_DIS | 0;
 272     ptimer_set_limit(env->stick, TICK_MAX, 1);
 273     ptimer_run(env->stick, 1);
 274     env->hstick_cmpr = TICK_INT_DIS | 0;
 275     ptimer_set_limit(env->hstick, TICK_MAX, 1);
 276     ptimer_run(env->hstick, 1);
 277     env->gregs[1] = 0; // Memory start
 278     env->gregs[2] = ram_size; // Memory size
 279     env->gregs[3] = 0; // Machine description XXX
 280     env->pc = s->reset_addr;
 281     env->npc = env->pc + 4;
 282 }
 283
 284 static void tick_irq(void *opaque)
 285 {
 286     CPUState *env = opaque;
 287
 288     if (!(env->tick_cmpr & TICK_INT_DIS)) {
 289         env->softint |= SOFTINT_TIMER;
 290         cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 291     }
 292 }
 293
 294 static void stick_irq(void *opaque)
 295 {
 296     CPUState *env = opaque;
 297
 298     if (!(env->stick_cmpr & TICK_INT_DIS)) {
 299         env->softint |= SOFTINT_STIMER;
 300         cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 301     }
 302 }
 303
 304 static void hstick_irq(void *opaque)
 305 {
 306     CPUState *env = opaque;
 307
 308     if (!(env->hstick_cmpr & TICK_INT_DIS)) {
 309         cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 310     }
 311 }
 312
 313 void cpu_tick_set_count(void *opaque, uint64_t count)
 314 {
 315     ptimer_set_count(opaque, -count);
 316 }
 317
 318 uint64_t cpu_tick_get_count(void *opaque)
 319 {
 320     return -ptimer_get_count(opaque);
 321 }
 322
 323 void cpu_tick_set_limit(void *opaque, uint64_t limit)
 324 {
 325     ptimer_set_limit(opaque, -limit, 0);
 326 }
 327
 328 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 329 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 330 static const int ide_irq[2] = { 14, 15 };
 331
 332 static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 333 static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 334
 335 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 336 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 337
 338 static fdctrl_t *floppy_controller;
 339
 340 static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
 341                               uint32_t addr, uint32_t size, int type)
 342 {
 343     DPRINTF("Mapping region %d registers at %08x\n", region_num, addr);
 344     switch (region_num) {
 345     case 0:
 346         isa_mmio_init(addr, 0x1000000);
 347         break;
 348     case 1:
 349         isa_mmio_init(addr, 0x800000);
 350         break;
 351     }
 352 }
 353
 354 /* EBUS (Eight bit bus) bridge */
 355 static void
 356 pci_ebus_init(PCIBus *bus, int devfn)
 357 {
 358     pci_create_simple(bus, devfn, "ebus");
 359 }
 360
 361 static int
 362 pci_ebus_init1(PCIDevice *s)
 363 {
 364     isa_bus_new(&s->qdev);
 365
 366     pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN);
 367     pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS);
 368     s->config[0x04] = 0x06; // command = bus master, pci mem
 369     s->config[0x05] = 0x00;
 370     s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 371     s->config[0x07] = 0x03; // status = medium devsel
 372     s->config[0x08] = 0x01; // revision
 373     s->config[0x09] = 0x00; // programming i/f
 374     pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER);
 375     s->config[0x0D] = 0x0a; // latency_timer
 376     s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 377
 378     pci_register_bar(s, 0, 0x1000000, PCI_ADDRESS_SPACE_MEM,
 379                            ebus_mmio_mapfunc);
 380     pci_register_bar(s, 1, 0x800000,  PCI_ADDRESS_SPACE_MEM,
 381                            ebus_mmio_mapfunc);
 382     return 0;
 383 }
 384
 385 static PCIDeviceInfo ebus_info = {
 386     .qdev.name = "ebus",
 387     .qdev.size = sizeof(PCIDevice),
 388     .init = pci_ebus_init1,
 389 };
 390
 391 static void pci_ebus_register(void)
 392 {
 393     pci_qdev_register(&ebus_info);
 394 }
 395
 396 device_init(pci_ebus_register);
 397
 398 /* Boot PROM (OpenBIOS) */
 399 static void prom_init(target_phys_addr_t addr, const char *bios_name)
 400 {
 401     DeviceState *dev;
 402     SysBusDevice *s;
 403     char *filename;
 404     int ret;
 405
 406     dev = qdev_create(NULL, "openprom");
 407     qdev_init(dev);
 408     s = sysbus_from_qdev(dev);
 409
 410     sysbus_mmio_map(s, 0, addr);
 411
 412     /* load boot prom */
 413     if (bios_name == NULL) {
 414         bios_name = PROM_FILENAME;
 415     }
 416     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 417     if (filename) {
 418         ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL);
 419         if (ret < 0 || ret > PROM_SIZE_MAX) {
 420             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
 421         }
 422         qemu_free(filename);
 423     } else {
 424         ret = -1;
 425     }
 426     if (ret < 0 || ret > PROM_SIZE_MAX) {
 427         fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
 428         exit(1);
 429     }
 430 }
 431
 432 static int prom_init1(SysBusDevice *dev)
 433 {
 434     ram_addr_t prom_offset;
 435
 436     prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
 437     sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
 438     return 0;
 439 }
 440
 441 static SysBusDeviceInfo prom_info = {
 442     .init = prom_init1,
 443     .qdev.name  = "openprom",
 444     .qdev.size  = sizeof(SysBusDevice),
 445     .qdev.props = (Property[]) {
 446         {/* end of property list */}
 447     }
 448 };
 449
 450 static void prom_register_devices(void)
 451 {
 452     sysbus_register_withprop(&prom_info);
 453 }
 454
 455 device_init(prom_register_devices);
 456
 457
 458 typedef struct RamDevice
 459 {
 460     SysBusDevice busdev;
 461     uint64_t size;
 462 } RamDevice;
 463
 464 /* System RAM */
 465 static int ram_init1(SysBusDevice *dev)
 466 {
 467     ram_addr_t RAM_size, ram_offset;
 468     RamDevice *d = FROM_SYSBUS(RamDevice, dev);
 469
 470     RAM_size = d->size;
 471
 472     ram_offset = qemu_ram_alloc(RAM_size);
 473     sysbus_init_mmio(dev, RAM_size, ram_offset);
 474     return 0;
 475 }
 476
 477 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size)
 478 {
 479     DeviceState *dev;
 480     SysBusDevice *s;
 481     RamDevice *d;
 482
 483     /* allocate RAM */
 484     dev = qdev_create(NULL, "memory");
 485     s = sysbus_from_qdev(dev);
 486
 487     d = FROM_SYSBUS(RamDevice, s);
 488     d->size = RAM_size;
 489     qdev_init(dev);
 490
 491     sysbus_mmio_map(s, 0, addr);
 492 }
 493
 494 static SysBusDeviceInfo ram_info = {
 495     .init = ram_init1,
 496     .qdev.name  = "memory",
 497     .qdev.size  = sizeof(RamDevice),
 498     .qdev.props = (Property[]) {
 499         DEFINE_PROP_UINT64("size", RamDevice, size, 0),
 500         DEFINE_PROP_END_OF_LIST(),
 501     }
 502 };
 503
 504 static void ram_register_devices(void)
 505 {
 506     sysbus_register_withprop(&ram_info);
 507 }
 508
 509 device_init(ram_register_devices);
 510
 511 static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
 512 {
 513     CPUState *env;
 514     QEMUBH *bh;
 515     ResetData *reset_info;
 516
 517     if (!cpu_model)
 518         cpu_model = hwdef->default_cpu_model;
 519     env = cpu_init(cpu_model);
 520     if (!env) {
 521         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 522         exit(1);
 523     }
 524     bh = qemu_bh_new(tick_irq, env);
 525     env->tick = ptimer_init(bh);
 526     ptimer_set_period(env->tick, 1ULL);
 527
 528     bh = qemu_bh_new(stick_irq, env);
 529     env->stick = ptimer_init(bh);
 530     ptimer_set_period(env->stick, 1ULL);
 531
 532     bh = qemu_bh_new(hstick_irq, env);
 533     env->hstick = ptimer_init(bh);
 534     ptimer_set_period(env->hstick, 1ULL);
 535
 536     reset_info = qemu_mallocz(sizeof(ResetData));
 537     reset_info->env = env;
 538     reset_info->reset_addr = hwdef->prom_addr + 0x40ULL;
 539     qemu_register_reset(main_cpu_reset, reset_info);
 540     main_cpu_reset(reset_info);
 541     // Override warm reset address with cold start address
 542     env->pc = hwdef->prom_addr + 0x20ULL;
 543     env->npc = env->pc + 4;
 544
 545     return env;
 546 }
 547
 548 static void sun4uv_init(ram_addr_t RAM_size,
 549                         const char *boot_devices,
 550                         const char *kernel_filename, const char *kernel_cmdline,
 551                         const char *initrd_filename, const char *cpu_model,
 552                         const struct hwdef *hwdef)
 553 {
 554     CPUState *env;
 555     m48t59_t *nvram;
 556     unsigned int i;
 557     long initrd_size, kernel_size;
 558     PCIBus *pci_bus, *pci_bus2, *pci_bus3;
 559     qemu_irq *irq;
 560     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 561     BlockDriverState *fd[MAX_FD];
 562     void *fw_cfg;
 563     DriveInfo *dinfo;
 564
 565     /* init CPUs */
 566     env = cpu_devinit(cpu_model, hwdef);
 567
 568     /* set up devices */
 569     ram_init(0, RAM_size);
 570
 571     prom_init(hwdef->prom_addr, bios_name);
 572
 573
 574     irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
 575     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2,
 576                            &pci_bus3);
 577     isa_mem_base = VGA_BASE;
 578     pci_vga_init(pci_bus, 0, 0);
 579
 580     // XXX Should be pci_bus3
 581     pci_ebus_init(pci_bus, -1);
 582
 583     i = 0;
 584     if (hwdef->console_serial_base) {
 585         serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
 586                        serial_hds[i], 1);
 587         i++;
 588     }
 589     for(; i < MAX_SERIAL_PORTS; i++) {
 590         if (serial_hds[i]) {
 591             serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200,
 592                         serial_hds[i]);
 593         }
 594     }
 595
 596     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 597         if (parallel_hds[i]) {
 598             parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/,
 599                           parallel_hds[i]);
 600         }
 601     }
 602
 603     for(i = 0; i < nb_nics; i++)
 604         pci_nic_init(&nd_table[i], "ne2k_pci", NULL);
 605
 606     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 607         fprintf(stderr, "qemu: too many IDE bus\n");
 608         exit(1);
 609     }
 610     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 611         dinfo = drive_get(IF_IDE, i / MAX_IDE_DEVS,
 612                           i % MAX_IDE_DEVS);
 613         hd[i] = dinfo ? dinfo->bdrv : NULL;
 614     }
 615
 616     pci_cmd646_ide_init(pci_bus, hd, 1);
 617
 618     /* FIXME: wire up interrupts.  */
 619     i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
 620     for(i = 0; i < MAX_FD; i++) {
 621         dinfo = drive_get(IF_FLOPPY, 0, i);
 622         fd[i] = dinfo ? dinfo->bdrv : NULL;
 623     }
 624     floppy_controller = fdctrl_init_isa(6, 2, 0x3f0, fd);
 625     nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
 626
 627     initrd_size = 0;
 628     kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename,
 629                                     ram_size, &initrd_size);
 630
 631     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
 632                            KERNEL_LOAD_ADDR, kernel_size,
 633                            kernel_cmdline,
 634                            INITRD_LOAD_ADDR, initrd_size,
 635                            /* XXX: need an option to load a NVRAM image */
 636                            0,
 637                            graphic_width, graphic_height, graphic_depth,
 638                            (uint8_t *)&nd_table[0].macaddr);
 639
 640     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 641     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 642     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 643     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 644     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
 645     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 646     if (kernel_cmdline) {
 647         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
 648         pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
 649     } else {
 650         fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
 651     }
 652     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
 653     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 654     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
 655
 656     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
 657     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
 658     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
 659
 660     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 661 }
 662
 663 enum {
 664     sun4u_id = 0,
 665     sun4v_id = 64,
 666     niagara_id,
 667 };
 668
 669 static const struct hwdef hwdefs[] = {
 670     /* Sun4u generic PC-like machine */
 671     {
 672         .default_cpu_model = "TI UltraSparc II",
 673         .machine_id = sun4u_id,
 674         .prom_addr = 0x1fff0000000ULL,
 675         .console_serial_base = 0,
 676     },
 677     /* Sun4v generic PC-like machine */
 678     {
 679         .default_cpu_model = "Sun UltraSparc T1",
 680         .machine_id = sun4v_id,
 681         .prom_addr = 0x1fff0000000ULL,
 682         .console_serial_base = 0,
 683     },
 684     /* Sun4v generic Niagara machine */
 685     {
 686         .default_cpu_model = "Sun UltraSparc T1",
 687         .machine_id = niagara_id,
 688         .prom_addr = 0xfff0000000ULL,
 689         .console_serial_base = 0xfff0c2c000ULL,
 690     },
 691 };
 692
 693 /* Sun4u hardware initialisation */
 694 static void sun4u_init(ram_addr_t RAM_size,
 695                        const char *boot_devices,
 696                        const char *kernel_filename, const char *kernel_cmdline,
 697                        const char *initrd_filename, const char *cpu_model)
 698 {
 699     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 700                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
 701 }
 702
 703 /* Sun4v hardware initialisation */
 704 static void sun4v_init(ram_addr_t RAM_size,
 705                        const char *boot_devices,
 706                        const char *kernel_filename, const char *kernel_cmdline,
 707                        const char *initrd_filename, const char *cpu_model)
 708 {
 709     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 710                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
 711 }
 712
 713 /* Niagara hardware initialisation */
 714 static void niagara_init(ram_addr_t RAM_size,
 715                          const char *boot_devices,
 716                          const char *kernel_filename, const char *kernel_cmdline,
 717                          const char *initrd_filename, const char *cpu_model)
 718 {
 719     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 720                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
 721 }
 722
 723 static QEMUMachine sun4u_machine = {
 724     .name = "sun4u",
 725     .desc = "Sun4u platform",
 726     .init = sun4u_init,
 727     .max_cpus = 1, // XXX for now
 728     .is_default = 1,
 729 };
 730
 731 static QEMUMachine sun4v_machine = {
 732     .name = "sun4v",
 733     .desc = "Sun4v platform",
 734     .init = sun4v_init,
 735     .max_cpus = 1, // XXX for now
 736 };
 737
 738 static QEMUMachine niagara_machine = {
 739     .name = "Niagara",
 740     .desc = "Sun4v platform, Niagara",
 741     .init = niagara_init,
 742     .max_cpus = 1, // XXX for now
 743 };
 744
 745 static void sun4u_machine_init(void)
 746 {
 747     qemu_register_machine(&sun4u_machine);
 748     qemu_register_machine(&sun4v_machine);
 749     qemu_register_machine(&niagara_machine);
 750 }
 751
 752 machine_init(sun4u_machine_init);