hw/timer/a9gtimer.c

   1 /*
   2  * Global peripheral timer block for ARM A9MP
   3  *
   4  * (C) 2013 Xilinx Inc.
   5  *
   6  * Written by François LEGAL
   7  * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License
  11  * as published by the Free Software Foundation; either version
  12  * 2 of the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License along
  20  * with this program; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "qemu/osdep.h"
  24 #include "hw/hw.h"
  25 #include "hw/irq.h"
  26 #include "hw/timer/a9gtimer.h"
  27 #include "migration/vmstate.h"
  28 #include "qapi/error.h"
  29 #include "qemu/timer.h"
  30 #include "qemu/bitops.h"
  31 #include "qemu/log.h"
  32 #include "qemu/module.h"
  33 #include "qom/cpu.h"
  34
  35 #ifndef A9_GTIMER_ERR_DEBUG
  36 #define A9_GTIMER_ERR_DEBUG 0
  37 #endif
  38
  39 #define DB_PRINT_L(level, ...) do { \
  40     if (A9_GTIMER_ERR_DEBUG > (level)) { \
  41         fprintf(stderr,  ": %s: ", __func__); \
  42         fprintf(stderr, ## __VA_ARGS__); \
  43     } \
  44 } while (0)
  45
  46 #define DB_PRINT(...) DB_PRINT_L(0, ## __VA_ARGS__)
  47
  48 static inline int a9_gtimer_get_current_cpu(A9GTimerState *s)
  49 {
  50     if (current_cpu->cpu_index >= s->num_cpu) {
  51         hw_error("a9gtimer: num-cpu %d but this cpu is %d!\n",
  52                  s->num_cpu, current_cpu->cpu_index);
  53     }
  54     return current_cpu->cpu_index;
  55 }
  56
  57 static inline uint64_t a9_gtimer_get_conv(A9GTimerState *s)
  58 {
  59     uint64_t prescale = extract32(s->control, R_CONTROL_PRESCALER_SHIFT,
  60                                   R_CONTROL_PRESCALER_LEN);
  61
  62     return (prescale + 1) * 10;
  63 }
  64
  65 static A9GTimerUpdate a9_gtimer_get_update(A9GTimerState *s)
  66 {
  67     A9GTimerUpdate ret;
  68
  69     ret.now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
  70     ret.new = s->ref_counter +
  71               (ret.now - s->cpu_ref_time) / a9_gtimer_get_conv(s);
  72     return ret;
  73 }
  74
  75 static void a9_gtimer_update(A9GTimerState *s, bool sync)
  76 {
  77
  78     A9GTimerUpdate update = a9_gtimer_get_update(s);
  79     int i;
  80     int64_t next_cdiff = 0;
  81
  82     for (i = 0; i < s->num_cpu; ++i) {
  83         A9GTimerPerCPU *gtb = &s->per_cpu[i];
  84         int64_t cdiff = 0;
  85
  86         if ((s->control & R_CONTROL_TIMER_ENABLE) &&
  87                 (gtb->control & R_CONTROL_COMP_ENABLE)) {
  88             /* R2p0+, where the compare function is >= */
  89             if (gtb->compare < update.new) {
  90                 DB_PRINT("Compare event happened for CPU %d\n", i);
  91                 gtb->status = 1;
  92                 if (gtb->control & R_CONTROL_AUTO_INCREMENT && gtb->inc) {
  93                     uint64_t inc =
  94                         QEMU_ALIGN_UP(update.new - gtb->compare, gtb->inc);
  95                     DB_PRINT("Auto incrementing timer compare by %"
  96                                                         PRId64 "\n", inc);
  97                     gtb->compare += inc;
  98                 }
  99             }
 100             cdiff = (int64_t)gtb->compare - (int64_t)update.new + 1;
 101             if (cdiff > 0 && (cdiff < next_cdiff || !next_cdiff)) {
 102                 next_cdiff = cdiff;
 103             }
 104         }
 105
 106         qemu_set_irq(gtb->irq,
 107                      gtb->status && (gtb->control & R_CONTROL_IRQ_ENABLE));
 108     }
 109
 110     timer_del(s->timer);
 111     if (next_cdiff) {
 112         DB_PRINT("scheduling qemu_timer to fire again in %"
 113                  PRIx64 " cycles\n", next_cdiff);
 114         timer_mod(s->timer, update.now + next_cdiff * a9_gtimer_get_conv(s));
 115     }
 116
 117     if (s->control & R_CONTROL_TIMER_ENABLE) {
 118         s->counter = update.new;
 119     }
 120
 121     if (sync) {
 122         s->cpu_ref_time = update.now;
 123         s->ref_counter = s->counter;
 124     }
 125 }
 126
 127 static void a9_gtimer_update_no_sync(void *opaque)
 128 {
 129     A9GTimerState *s = A9_GTIMER(opaque);
 130
 131     a9_gtimer_update(s, false);
 132 }
 133
 134 static uint64_t a9_gtimer_read(void *opaque, hwaddr addr, unsigned size)
 135 {
 136     A9GTimerPerCPU *gtb = (A9GTimerPerCPU *)opaque;
 137     A9GTimerState *s = gtb->parent;
 138     A9GTimerUpdate update;
 139     uint64_t ret = 0;
 140     int shift = 0;
 141
 142     switch (addr) {
 143     case R_COUNTER_HI:
 144         shift = 32;
 145         /* fallthrough */
 146     case R_COUNTER_LO:
 147         update = a9_gtimer_get_update(s);
 148         ret = extract64(update.new, shift, 32);
 149         break;
 150     case R_CONTROL:
 151         ret = s->control | gtb->control;
 152         break;
 153     case R_INTERRUPT_STATUS:
 154         ret = gtb->status;
 155         break;
 156     case R_COMPARATOR_HI:
 157         shift = 32;
 158         /* fallthrough */
 159     case R_COMPARATOR_LO:
 160         ret = extract64(gtb->compare, shift, 32);
 161         break;
 162     case R_AUTO_INCREMENT:
 163         ret =  gtb->inc;
 164         break;
 165     default:
 166         qemu_log_mask(LOG_GUEST_ERROR, "bad a9gtimer register: %x\n",
 167                       (unsigned)addr);
 168         return 0;
 169     }
 170
 171     DB_PRINT("addr:%#x data:%#08" PRIx64 "\n", (unsigned)addr, ret);
 172     return ret;
 173 }
 174
 175 static void a9_gtimer_write(void *opaque, hwaddr addr, uint64_t value,
 176                             unsigned size)
 177 {
 178     A9GTimerPerCPU *gtb = (A9GTimerPerCPU *)opaque;
 179     A9GTimerState *s = gtb->parent;
 180     int shift = 0;
 181
 182     DB_PRINT("addr:%#x data:%#08" PRIx64 "\n", (unsigned)addr, value);
 183
 184     switch (addr) {
 185     case R_COUNTER_HI:
 186         shift = 32;
 187         /* fallthrough */
 188     case R_COUNTER_LO:
 189         /*
 190          * Keep it simple - ARM docco explicitly says to disable timer before
 191          * modding it, so don't bother trying to do all the difficult on the fly
 192          * timer modifications - (if they even work in real hardware??).
 193          */
 194         if (s->control & R_CONTROL_TIMER_ENABLE) {
 195             qemu_log_mask(LOG_GUEST_ERROR, "Cannot mod running ARM gtimer\n");
 196             return;
 197         }
 198         s->counter = deposit64(s->counter, shift, 32, value);
 199         return;
 200     case R_CONTROL:
 201         a9_gtimer_update(s, (value ^ s->control) & R_CONTROL_NEEDS_SYNC);
 202         gtb->control = value & R_CONTROL_BANKED;
 203         s->control = value & ~R_CONTROL_BANKED;
 204         break;
 205     case R_INTERRUPT_STATUS:
 206         a9_gtimer_update(s, false);
 207         gtb->status &= ~value;
 208         break;
 209     case R_COMPARATOR_HI:
 210         shift = 32;
 211         /* fallthrough */
 212     case R_COMPARATOR_LO:
 213         a9_gtimer_update(s, false);
 214         gtb->compare = deposit64(gtb->compare, shift, 32, value);
 215         break;
 216     case R_AUTO_INCREMENT:
 217         gtb->inc = value;
 218         return;
 219     default:
 220         return;
 221     }
 222
 223     a9_gtimer_update(s, false);
 224 }
 225
 226 /* Wrapper functions to implement the "read global timer for
 227  * the current CPU" memory regions.
 228  */
 229 static uint64_t a9_gtimer_this_read(void *opaque, hwaddr addr,
 230                                     unsigned size)
 231 {
 232     A9GTimerState *s = A9_GTIMER(opaque);
 233     int id = a9_gtimer_get_current_cpu(s);
 234
 235     /* no \n so concatenates with message from read fn */
 236     DB_PRINT("CPU:%d:", id);
 237
 238     return a9_gtimer_read(&s->per_cpu[id], addr, size);
 239 }
 240
 241 static void a9_gtimer_this_write(void *opaque, hwaddr addr,
 242                                  uint64_t value, unsigned size)
 243 {
 244     A9GTimerState *s = A9_GTIMER(opaque);
 245     int id = a9_gtimer_get_current_cpu(s);
 246
 247     /* no \n so concatenates with message from write fn */
 248     DB_PRINT("CPU:%d:", id);
 249
 250     a9_gtimer_write(&s->per_cpu[id], addr, value, size);
 251 }
 252
 253 static const MemoryRegionOps a9_gtimer_this_ops = {
 254     .read = a9_gtimer_this_read,
 255     .write = a9_gtimer_this_write,
 256     .valid = {
 257         .min_access_size = 4,
 258         .max_access_size = 4,
 259     },
 260     .endianness = DEVICE_NATIVE_ENDIAN,
 261 };
 262
 263 static const MemoryRegionOps a9_gtimer_ops = {
 264     .read = a9_gtimer_read,
 265     .write = a9_gtimer_write,
 266     .valid = {
 267         .min_access_size = 4,
 268         .max_access_size = 4,
 269     },
 270     .endianness = DEVICE_NATIVE_ENDIAN,
 271 };
 272
 273 static void a9_gtimer_reset(DeviceState *dev)
 274 {
 275     A9GTimerState *s = A9_GTIMER(dev);
 276     int i;
 277
 278     s->counter = 0;
 279     s->control = 0;
 280
 281     for (i = 0; i < s->num_cpu; i++) {
 282         A9GTimerPerCPU *gtb = &s->per_cpu[i];
 283
 284         gtb->control = 0;
 285         gtb->status = 0;
 286         gtb->compare = 0;
 287         gtb->inc = 0;
 288     }
 289     a9_gtimer_update(s, false);
 290 }
 291
 292 static void a9_gtimer_realize(DeviceState *dev, Error **errp)
 293 {
 294     A9GTimerState *s = A9_GTIMER(dev);
 295     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 296     int i;
 297
 298     if (s->num_cpu < 1 || s->num_cpu > A9_GTIMER_MAX_CPUS) {
 299         error_setg(errp, "%s: num-cpu must be between 1 and %d",
 300                    __func__, A9_GTIMER_MAX_CPUS);
 301         return;
 302     }
 303
 304     memory_region_init_io(&s->iomem, OBJECT(dev), &a9_gtimer_this_ops, s,
 305                           "a9gtimer shared", 0x20);
 306     sysbus_init_mmio(sbd, &s->iomem);
 307     s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, a9_gtimer_update_no_sync, s);
 308
 309     for (i = 0; i < s->num_cpu; i++) {
 310         A9GTimerPerCPU *gtb = &s->per_cpu[i];
 311
 312         gtb->parent = s;
 313         sysbus_init_irq(sbd, &gtb->irq);
 314         memory_region_init_io(&gtb->iomem, OBJECT(dev), &a9_gtimer_ops, gtb,
 315                               "a9gtimer per cpu", 0x20);
 316         sysbus_init_mmio(sbd, &gtb->iomem);
 317     }
 318 }
 319
 320 static const VMStateDescription vmstate_a9_gtimer_per_cpu = {
 321     .name = "arm.cortex-a9-global-timer.percpu",
 322     .version_id = 1,
 323     .minimum_version_id = 1,
 324     .fields = (VMStateField[]) {
 325         VMSTATE_UINT32(control, A9GTimerPerCPU),
 326         VMSTATE_UINT64(compare, A9GTimerPerCPU),
 327         VMSTATE_UINT32(status, A9GTimerPerCPU),
 328         VMSTATE_UINT32(inc, A9GTimerPerCPU),
 329         VMSTATE_END_OF_LIST()
 330     }
 331 };
 332
 333 static const VMStateDescription vmstate_a9_gtimer = {
 334     .name = "arm.cortex-a9-global-timer",
 335     .version_id = 1,
 336     .minimum_version_id = 1,
 337     .fields = (VMStateField[]) {
 338         VMSTATE_TIMER_PTR(timer, A9GTimerState),
 339         VMSTATE_UINT64(counter, A9GTimerState),
 340         VMSTATE_UINT64(ref_counter, A9GTimerState),
 341         VMSTATE_UINT64(cpu_ref_time, A9GTimerState),
 342         VMSTATE_STRUCT_VARRAY_UINT32(per_cpu, A9GTimerState, num_cpu,
 343                                      1, vmstate_a9_gtimer_per_cpu,
 344                                      A9GTimerPerCPU),
 345         VMSTATE_END_OF_LIST()
 346     }
 347 };
 348
 349 static Property a9_gtimer_properties[] = {
 350     DEFINE_PROP_UINT32("num-cpu", A9GTimerState, num_cpu, 0),
 351     DEFINE_PROP_END_OF_LIST()
 352 };
 353
 354 static void a9_gtimer_class_init(ObjectClass *klass, void *data)
 355 {
 356     DeviceClass *dc = DEVICE_CLASS(klass);
 357
 358     dc->realize = a9_gtimer_realize;
 359     dc->vmsd = &vmstate_a9_gtimer;
 360     dc->reset = a9_gtimer_reset;
 361     dc->props = a9_gtimer_properties;
 362 }
 363
 364 static const TypeInfo a9_gtimer_info = {
 365     .name          = TYPE_A9_GTIMER,
 366     .parent        = TYPE_SYS_BUS_DEVICE,
 367     .instance_size = sizeof(A9GTimerState),
 368     .class_init    = a9_gtimer_class_init,
 369 };
 370
 371 static void a9_gtimer_register_types(void)
 372 {
 373     type_register_static(&a9_gtimer_info);
 374 }
 375
 376 type_init(a9_gtimer_register_types)