2 * Global peripheral timer block for ARM A9MP
6 * Written by François LEGAL
7 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 #include "qemu/osdep.h"
24 #include "hw/timer/a9gtimer.h"
25 #include "qemu/timer.h"
26 #include "qemu/bitops.h"
30 #ifndef A9_GTIMER_ERR_DEBUG
31 #define A9_GTIMER_ERR_DEBUG 0
34 #define DB_PRINT_L(level, ...) do { \
35 if (A9_GTIMER_ERR_DEBUG > (level)) { \
36 fprintf(stderr, ": %s: ", __func__); \
37 fprintf(stderr, ## __VA_ARGS__); \
41 #define DB_PRINT(...) DB_PRINT_L(0, ## __VA_ARGS__)
43 static inline int a9_gtimer_get_current_cpu(A9GTimerState
*s
)
45 if (current_cpu
->cpu_index
>= s
->num_cpu
) {
46 hw_error("a9gtimer: num-cpu %d but this cpu is %d!\n",
47 s
->num_cpu
, current_cpu
->cpu_index
);
49 return current_cpu
->cpu_index
;
52 static inline uint64_t a9_gtimer_get_conv(A9GTimerState
*s
)
54 uint64_t prescale
= extract32(s
->control
, R_CONTROL_PRESCALER_SHIFT
,
55 R_CONTROL_PRESCALER_LEN
);
57 return (prescale
+ 1) * 10;
60 static A9GTimerUpdate
a9_gtimer_get_update(A9GTimerState
*s
)
64 ret
.now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
65 ret
.new = s
->ref_counter
+
66 (ret
.now
- s
->cpu_ref_time
) / a9_gtimer_get_conv(s
);
70 static void a9_gtimer_update(A9GTimerState
*s
, bool sync
)
73 A9GTimerUpdate update
= a9_gtimer_get_update(s
);
75 int64_t next_cdiff
= 0;
77 for (i
= 0; i
< s
->num_cpu
; ++i
) {
78 A9GTimerPerCPU
*gtb
= &s
->per_cpu
[i
];
81 if ((s
->control
& R_CONTROL_TIMER_ENABLE
) &&
82 (gtb
->control
& R_CONTROL_COMP_ENABLE
)) {
83 /* R2p0+, where the compare function is >= */
84 while (gtb
->compare
< update
.new) {
85 DB_PRINT("Compare event happened for CPU %d\n", i
);
87 if (gtb
->control
& R_CONTROL_AUTO_INCREMENT
) {
88 DB_PRINT("Auto incrementing timer compare by %" PRId32
"\n",
90 gtb
->compare
+= gtb
->inc
;
95 cdiff
= (int64_t)gtb
->compare
- (int64_t)update
.new + 1;
96 if (cdiff
> 0 && (cdiff
< next_cdiff
|| !next_cdiff
)) {
101 qemu_set_irq(gtb
->irq
,
102 gtb
->status
&& (gtb
->control
& R_CONTROL_IRQ_ENABLE
));
107 DB_PRINT("scheduling qemu_timer to fire again in %"
108 PRIx64
" cycles\n", next_cdiff
);
109 timer_mod(s
->timer
, update
.now
+ next_cdiff
* a9_gtimer_get_conv(s
));
112 if (s
->control
& R_CONTROL_TIMER_ENABLE
) {
113 s
->counter
= update
.new;
117 s
->cpu_ref_time
= update
.now
;
118 s
->ref_counter
= s
->counter
;
122 static void a9_gtimer_update_no_sync(void *opaque
)
124 A9GTimerState
*s
= A9_GTIMER(opaque
);
126 a9_gtimer_update(s
, false);
129 static uint64_t a9_gtimer_read(void *opaque
, hwaddr addr
, unsigned size
)
131 A9GTimerPerCPU
*gtb
= (A9GTimerPerCPU
*)opaque
;
132 A9GTimerState
*s
= gtb
->parent
;
133 A9GTimerUpdate update
;
142 update
= a9_gtimer_get_update(s
);
143 ret
= extract64(update
.new, shift
, 32);
146 ret
= s
->control
| gtb
->control
;
148 case R_INTERRUPT_STATUS
:
151 case R_COMPARATOR_HI
:
154 case R_COMPARATOR_LO
:
155 ret
= extract64(gtb
->compare
, shift
, 32);
157 case R_AUTO_INCREMENT
:
161 qemu_log_mask(LOG_GUEST_ERROR
, "bad a9gtimer register: %x\n",
166 DB_PRINT("addr:%#x data:%#08" PRIx64
"\n", (unsigned)addr
, ret
);
170 static void a9_gtimer_write(void *opaque
, hwaddr addr
, uint64_t value
,
173 A9GTimerPerCPU
*gtb
= (A9GTimerPerCPU
*)opaque
;
174 A9GTimerState
*s
= gtb
->parent
;
177 DB_PRINT("addr:%#x data:%#08" PRIx64
"\n", (unsigned)addr
, value
);
185 * Keep it simple - ARM docco explicitly says to disable timer before
186 * modding it, so dont bother trying to do all the difficult on the fly
187 * timer modifications - (if they even work in real hardware??).
189 if (s
->control
& R_CONTROL_TIMER_ENABLE
) {
190 qemu_log_mask(LOG_GUEST_ERROR
, "Cannot mod running ARM gtimer\n");
193 s
->counter
= deposit64(s
->counter
, shift
, 32, value
);
196 a9_gtimer_update(s
, (value
^ s
->control
) & R_CONTROL_NEEDS_SYNC
);
197 gtb
->control
= value
& R_CONTROL_BANKED
;
198 s
->control
= value
& ~R_CONTROL_BANKED
;
200 case R_INTERRUPT_STATUS
:
201 a9_gtimer_update(s
, false);
202 gtb
->status
&= ~value
;
204 case R_COMPARATOR_HI
:
207 case R_COMPARATOR_LO
:
208 a9_gtimer_update(s
, false);
209 gtb
->compare
= deposit64(gtb
->compare
, shift
, 32, value
);
211 case R_AUTO_INCREMENT
:
218 a9_gtimer_update(s
, false);
221 /* Wrapper functions to implement the "read global timer for
222 * the current CPU" memory regions.
224 static uint64_t a9_gtimer_this_read(void *opaque
, hwaddr addr
,
227 A9GTimerState
*s
= A9_GTIMER(opaque
);
228 int id
= a9_gtimer_get_current_cpu(s
);
230 /* no \n so concatenates with message from read fn */
231 DB_PRINT("CPU:%d:", id
);
233 return a9_gtimer_read(&s
->per_cpu
[id
], addr
, size
);
236 static void a9_gtimer_this_write(void *opaque
, hwaddr addr
,
237 uint64_t value
, unsigned size
)
239 A9GTimerState
*s
= A9_GTIMER(opaque
);
240 int id
= a9_gtimer_get_current_cpu(s
);
242 /* no \n so concatenates with message from write fn */
243 DB_PRINT("CPU:%d:", id
);
245 a9_gtimer_write(&s
->per_cpu
[id
], addr
, value
, size
);
248 static const MemoryRegionOps a9_gtimer_this_ops
= {
249 .read
= a9_gtimer_this_read
,
250 .write
= a9_gtimer_this_write
,
252 .min_access_size
= 4,
253 .max_access_size
= 4,
255 .endianness
= DEVICE_NATIVE_ENDIAN
,
258 static const MemoryRegionOps a9_gtimer_ops
= {
259 .read
= a9_gtimer_read
,
260 .write
= a9_gtimer_write
,
262 .min_access_size
= 4,
263 .max_access_size
= 4,
265 .endianness
= DEVICE_NATIVE_ENDIAN
,
268 static void a9_gtimer_reset(DeviceState
*dev
)
270 A9GTimerState
*s
= A9_GTIMER(dev
);
276 for (i
= 0; i
< s
->num_cpu
; i
++) {
277 A9GTimerPerCPU
*gtb
= &s
->per_cpu
[i
];
284 a9_gtimer_update(s
, false);
287 static void a9_gtimer_realize(DeviceState
*dev
, Error
**errp
)
289 A9GTimerState
*s
= A9_GTIMER(dev
);
290 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
293 if (s
->num_cpu
< 1 || s
->num_cpu
> A9_GTIMER_MAX_CPUS
) {
294 error_setg(errp
, "%s: num-cpu must be between 1 and %d",
295 __func__
, A9_GTIMER_MAX_CPUS
);
299 memory_region_init_io(&s
->iomem
, OBJECT(dev
), &a9_gtimer_this_ops
, s
,
300 "a9gtimer shared", 0x20);
301 sysbus_init_mmio(sbd
, &s
->iomem
);
302 s
->timer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
, a9_gtimer_update_no_sync
, s
);
304 for (i
= 0; i
< s
->num_cpu
; i
++) {
305 A9GTimerPerCPU
*gtb
= &s
->per_cpu
[i
];
308 sysbus_init_irq(sbd
, >b
->irq
);
309 memory_region_init_io(>b
->iomem
, OBJECT(dev
), &a9_gtimer_ops
, gtb
,
310 "a9gtimer per cpu", 0x20);
311 sysbus_init_mmio(sbd
, >b
->iomem
);
315 static const VMStateDescription vmstate_a9_gtimer_per_cpu
= {
316 .name
= "arm.cortex-a9-global-timer.percpu",
318 .minimum_version_id
= 1,
319 .fields
= (VMStateField
[]) {
320 VMSTATE_UINT32(control
, A9GTimerPerCPU
),
321 VMSTATE_UINT64(compare
, A9GTimerPerCPU
),
322 VMSTATE_UINT32(status
, A9GTimerPerCPU
),
323 VMSTATE_UINT32(inc
, A9GTimerPerCPU
),
324 VMSTATE_END_OF_LIST()
328 static const VMStateDescription vmstate_a9_gtimer
= {
329 .name
= "arm.cortex-a9-global-timer",
331 .minimum_version_id
= 1,
332 .fields
= (VMStateField
[]) {
333 VMSTATE_TIMER_PTR(timer
, A9GTimerState
),
334 VMSTATE_UINT64(counter
, A9GTimerState
),
335 VMSTATE_UINT64(ref_counter
, A9GTimerState
),
336 VMSTATE_UINT64(cpu_ref_time
, A9GTimerState
),
337 VMSTATE_STRUCT_VARRAY_UINT32(per_cpu
, A9GTimerState
, num_cpu
,
338 1, vmstate_a9_gtimer_per_cpu
,
340 VMSTATE_END_OF_LIST()
344 static Property a9_gtimer_properties
[] = {
345 DEFINE_PROP_UINT32("num-cpu", A9GTimerState
, num_cpu
, 0),
346 DEFINE_PROP_END_OF_LIST()
349 static void a9_gtimer_class_init(ObjectClass
*klass
, void *data
)
351 DeviceClass
*dc
= DEVICE_CLASS(klass
);
353 dc
->realize
= a9_gtimer_realize
;
354 dc
->vmsd
= &vmstate_a9_gtimer
;
355 dc
->reset
= a9_gtimer_reset
;
356 dc
->props
= a9_gtimer_properties
;
359 static const TypeInfo a9_gtimer_info
= {
360 .name
= TYPE_A9_GTIMER
,
361 .parent
= TYPE_SYS_BUS_DEVICE
,
362 .instance_size
= sizeof(A9GTimerState
),
363 .class_init
= a9_gtimer_class_init
,
366 static void a9_gtimer_register_types(void)
368 type_register_static(&a9_gtimer_info
);
371 type_init(a9_gtimer_register_types
)