hw/timer/arm_mptimer.c

   1 /*
   2  * Private peripheral timer/watchdog blocks for ARM 11MPCore and A9MP
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Copyright (c) 2011 Linaro Limited
   6  * Written by Paul Brook, Peter Maydell
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version
  11  * 2 of the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "qemu/osdep.h"
  23 #include "hw/irq.h"
  24 #include "hw/ptimer.h"
  25 #include "hw/timer/arm_mptimer.h"
  26 #include "migration/vmstate.h"
  27 #include "qapi/error.h"
  28 #include "qemu/main-loop.h"
  29 #include "qemu/module.h"
  30 #include "qom/cpu.h"
  31
  32 #define PTIMER_POLICY                       \
  33     (PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD |  \
  34      PTIMER_POLICY_CONTINUOUS_TRIGGER    |  \
  35      PTIMER_POLICY_NO_IMMEDIATE_TRIGGER  |  \
  36      PTIMER_POLICY_NO_IMMEDIATE_RELOAD   |  \
  37      PTIMER_POLICY_NO_COUNTER_ROUND_DOWN)
  38
  39 /* This device implements the per-cpu private timer and watchdog block
  40  * which is used in both the ARM11MPCore and Cortex-A9MP.
  41  */
  42
  43 static inline int get_current_cpu(ARMMPTimerState *s)
  44 {
  45     int cpu_id = current_cpu ? current_cpu->cpu_index : 0;
  46
  47     if (cpu_id >= s->num_cpu) {
  48         hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n",
  49                  s->num_cpu, cpu_id);
  50     }
  51
  52     return cpu_id;
  53 }
  54
  55 static inline void timerblock_update_irq(TimerBlock *tb)
  56 {
  57     qemu_set_irq(tb->irq, tb->status && (tb->control & 4));
  58 }
  59
  60 /* Return conversion factor from mpcore timer ticks to qemu timer ticks.  */
  61 static inline uint32_t timerblock_scale(uint32_t control)
  62 {
  63     return (((control >> 8) & 0xff) + 1) * 10;
  64 }
  65
  66 static inline void timerblock_set_count(struct ptimer_state *timer,
  67                                         uint32_t control, uint64_t *count)
  68 {
  69     /* PTimer would trigger interrupt for periodic timer when counter set
  70      * to 0, MPtimer under certain condition only.
  71      */
  72     if ((control & 3) == 3 && (control & 0xff00) == 0 && *count == 0) {
  73         *count = ptimer_get_limit(timer);
  74     }
  75     ptimer_set_count(timer, *count);
  76 }
  77
  78 static inline void timerblock_run(struct ptimer_state *timer,
  79                                   uint32_t control, uint32_t load)
  80 {
  81     if ((control & 1) && ((control & 0xff00) || load != 0)) {
  82         ptimer_run(timer, !(control & 2));
  83     }
  84 }
  85
  86 static void timerblock_tick(void *opaque)
  87 {
  88     TimerBlock *tb = (TimerBlock *)opaque;
  89     /* Periodic timer with load = 0 and prescaler != 0 would re-trigger
  90      * IRQ after one period, otherwise it either stops or wraps around.
  91      */
  92     if ((tb->control & 2) && (tb->control & 0xff00) == 0 &&
  93             ptimer_get_limit(tb->timer) == 0) {
  94         ptimer_stop(tb->timer);
  95     }
  96     tb->status = 1;
  97     timerblock_update_irq(tb);
  98 }
  99
 100 static uint64_t timerblock_read(void *opaque, hwaddr addr,
 101                                 unsigned size)
 102 {
 103     TimerBlock *tb = (TimerBlock *)opaque;
 104     switch (addr) {
 105     case 0: /* Load */
 106         return ptimer_get_limit(tb->timer);
 107     case 4: /* Counter.  */
 108         return ptimer_get_count(tb->timer);
 109     case 8: /* Control.  */
 110         return tb->control;
 111     case 12: /* Interrupt status.  */
 112         return tb->status;
 113     default:
 114         return 0;
 115     }
 116 }
 117
 118 static void timerblock_write(void *opaque, hwaddr addr,
 119                              uint64_t value, unsigned size)
 120 {
 121     TimerBlock *tb = (TimerBlock *)opaque;
 122     uint32_t control = tb->control;
 123     switch (addr) {
 124     case 0: /* Load */
 125         /* Setting load to 0 stops the timer without doing the tick if
 126          * prescaler = 0.
 127          */
 128         if ((control & 1) && (control & 0xff00) == 0 && value == 0) {
 129             ptimer_stop(tb->timer);
 130         }
 131         ptimer_set_limit(tb->timer, value, 1);
 132         timerblock_run(tb->timer, control, value);
 133         break;
 134     case 4: /* Counter.  */
 135         /* Setting counter to 0 stops the one-shot timer, or periodic with
 136          * load = 0, without doing the tick if prescaler = 0.
 137          */
 138         if ((control & 1) && (control & 0xff00) == 0 && value == 0 &&
 139                 (!(control & 2) || ptimer_get_limit(tb->timer) == 0)) {
 140             ptimer_stop(tb->timer);
 141         }
 142         timerblock_set_count(tb->timer, control, &value);
 143         timerblock_run(tb->timer, control, value);
 144         break;
 145     case 8: /* Control.  */
 146         if ((control & 3) != (value & 3)) {
 147             ptimer_stop(tb->timer);
 148         }
 149         if ((control & 0xff00) != (value & 0xff00)) {
 150             ptimer_set_period(tb->timer, timerblock_scale(value));
 151         }
 152         if (value & 1) {
 153             uint64_t count = ptimer_get_count(tb->timer);
 154             /* Re-load periodic timer counter if needed.  */
 155             if ((value & 2) && count == 0) {
 156                 timerblock_set_count(tb->timer, value, &count);
 157             }
 158             timerblock_run(tb->timer, value, count);
 159         }
 160         tb->control = value;
 161         break;
 162     case 12: /* Interrupt status.  */
 163         tb->status &= ~value;
 164         timerblock_update_irq(tb);
 165         break;
 166     }
 167 }
 168
 169 /* Wrapper functions to implement the "read timer/watchdog for
 170  * the current CPU" memory regions.
 171  */
 172 static uint64_t arm_thistimer_read(void *opaque, hwaddr addr,
 173                                    unsigned size)
 174 {
 175     ARMMPTimerState *s = (ARMMPTimerState *)opaque;
 176     int id = get_current_cpu(s);
 177     return timerblock_read(&s->timerblock[id], addr, size);
 178 }
 179
 180 static void arm_thistimer_write(void *opaque, hwaddr addr,
 181                                 uint64_t value, unsigned size)
 182 {
 183     ARMMPTimerState *s = (ARMMPTimerState *)opaque;
 184     int id = get_current_cpu(s);
 185     timerblock_write(&s->timerblock[id], addr, value, size);
 186 }
 187
 188 static const MemoryRegionOps arm_thistimer_ops = {
 189     .read = arm_thistimer_read,
 190     .write = arm_thistimer_write,
 191     .valid = {
 192         .min_access_size = 4,
 193         .max_access_size = 4,
 194     },
 195     .endianness = DEVICE_NATIVE_ENDIAN,
 196 };
 197
 198 static const MemoryRegionOps timerblock_ops = {
 199     .read = timerblock_read,
 200     .write = timerblock_write,
 201     .valid = {
 202         .min_access_size = 4,
 203         .max_access_size = 4,
 204     },
 205     .endianness = DEVICE_NATIVE_ENDIAN,
 206 };
 207
 208 static void timerblock_reset(TimerBlock *tb)
 209 {
 210     tb->control = 0;
 211     tb->status = 0;
 212     if (tb->timer) {
 213         ptimer_stop(tb->timer);
 214         ptimer_set_limit(tb->timer, 0, 1);
 215         ptimer_set_period(tb->timer, timerblock_scale(0));
 216     }
 217 }
 218
 219 static void arm_mptimer_reset(DeviceState *dev)
 220 {
 221     ARMMPTimerState *s = ARM_MPTIMER(dev);
 222     int i;
 223
 224     for (i = 0; i < ARRAY_SIZE(s->timerblock); i++) {
 225         timerblock_reset(&s->timerblock[i]);
 226     }
 227 }
 228
 229 static void arm_mptimer_init(Object *obj)
 230 {
 231     ARMMPTimerState *s = ARM_MPTIMER(obj);
 232
 233     memory_region_init_io(&s->iomem, obj, &arm_thistimer_ops, s,
 234                           "arm_mptimer_timer", 0x20);
 235     sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem);
 236 }
 237
 238 static void arm_mptimer_realize(DeviceState *dev, Error **errp)
 239 {
 240     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 241     ARMMPTimerState *s = ARM_MPTIMER(dev);
 242     int i;
 243
 244     if (s->num_cpu < 1 || s->num_cpu > ARM_MPTIMER_MAX_CPUS) {
 245         error_setg(errp, "num-cpu must be between 1 and %d",
 246                    ARM_MPTIMER_MAX_CPUS);
 247         return;
 248     }
 249     /* We implement one timer block per CPU, and expose multiple MMIO regions:
 250      *  * region 0 is "timer for this core"
 251      *  * region 1 is "timer for core 0"
 252      *  * region 2 is "timer for core 1"
 253      * and so on.
 254      * The outgoing interrupt lines are
 255      *  * timer for core 0
 256      *  * timer for core 1
 257      * and so on.
 258      */
 259     for (i = 0; i < s->num_cpu; i++) {
 260         TimerBlock *tb = &s->timerblock[i];
 261         QEMUBH *bh = qemu_bh_new(timerblock_tick, tb);
 262         tb->timer = ptimer_init(bh, PTIMER_POLICY);
 263         sysbus_init_irq(sbd, &tb->irq);
 264         memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb,
 265                               "arm_mptimer_timerblock", 0x20);
 266         sysbus_init_mmio(sbd, &tb->iomem);
 267     }
 268 }
 269
 270 static const VMStateDescription vmstate_timerblock = {
 271     .name = "arm_mptimer_timerblock",
 272     .version_id = 3,
 273     .minimum_version_id = 3,
 274     .fields = (VMStateField[]) {
 275         VMSTATE_UINT32(control, TimerBlock),
 276         VMSTATE_UINT32(status, TimerBlock),
 277         VMSTATE_PTIMER(timer, TimerBlock),
 278         VMSTATE_END_OF_LIST()
 279     }
 280 };
 281
 282 static const VMStateDescription vmstate_arm_mptimer = {
 283     .name = "arm_mptimer",
 284     .version_id = 3,
 285     .minimum_version_id = 3,
 286     .fields = (VMStateField[]) {
 287         VMSTATE_STRUCT_VARRAY_UINT32(timerblock, ARMMPTimerState, num_cpu,
 288                                      3, vmstate_timerblock, TimerBlock),
 289         VMSTATE_END_OF_LIST()
 290     }
 291 };
 292
 293 static Property arm_mptimer_properties[] = {
 294     DEFINE_PROP_UINT32("num-cpu", ARMMPTimerState, num_cpu, 0),
 295     DEFINE_PROP_END_OF_LIST()
 296 };
 297
 298 static void arm_mptimer_class_init(ObjectClass *klass, void *data)
 299 {
 300     DeviceClass *dc = DEVICE_CLASS(klass);
 301
 302     dc->realize = arm_mptimer_realize;
 303     dc->vmsd = &vmstate_arm_mptimer;
 304     dc->reset = arm_mptimer_reset;
 305     dc->props = arm_mptimer_properties;
 306 }
 307
 308 static const TypeInfo arm_mptimer_info = {
 309     .name          = TYPE_ARM_MPTIMER,
 310     .parent        = TYPE_SYS_BUS_DEVICE,
 311     .instance_size = sizeof(ARMMPTimerState),
 312     .instance_init = arm_mptimer_init,
 313     .class_init    = arm_mptimer_class_init,
 314 };
 315
 316 static void arm_mptimer_register_types(void)
 317 {
 318     type_register_static(&arm_mptimer_info);
 319 }
 320
 321 type_init(arm_mptimer_register_types)