hw/timer/arm_mptimer.c

   1 /*
   2  * Private peripheral timer/watchdog blocks for ARM 11MPCore and A9MP
   3  *
   4  * Copyright (c) 2006-2007 CodeSourcery.
   5  * Copyright (c) 2011 Linaro Limited
   6  * Written by Paul Brook, Peter Maydell
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version
  11  * 2 of the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "hw/sysbus.h"
  23 #include "qemu/timer.h"
  24 #include "qom/cpu.h"
  25
  26 /* This device implements the per-cpu private timer and watchdog block
  27  * which is used in both the ARM11MPCore and Cortex-A9MP.
  28  */
  29
  30 #define MAX_CPUS 4
  31
  32 /* State of a single timer or watchdog block */
  33 typedef struct {
  34     uint32_t count;
  35     uint32_t load;
  36     uint32_t control;
  37     uint32_t status;
  38     int64_t tick;
  39     QEMUTimer *timer;
  40     qemu_irq irq;
  41     MemoryRegion iomem;
  42 } TimerBlock;
  43
  44 typedef struct {
  45     SysBusDevice busdev;
  46     uint32_t num_cpu;
  47     TimerBlock timerblock[MAX_CPUS];
  48     MemoryRegion iomem;
  49 } ARMMPTimerState;
  50
  51 static inline int get_current_cpu(ARMMPTimerState *s)
  52 {
  53     if (current_cpu->cpu_index >= s->num_cpu) {
  54         hw_error("arm_mptimer: num-cpu %d but this cpu is %d!\n",
  55                  s->num_cpu, current_cpu->cpu_index);
  56     }
  57     return current_cpu->cpu_index;
  58 }
  59
  60 static inline void timerblock_update_irq(TimerBlock *tb)
  61 {
  62     qemu_set_irq(tb->irq, tb->status);
  63 }
  64
  65 /* Return conversion factor from mpcore timer ticks to qemu timer ticks.  */
  66 static inline uint32_t timerblock_scale(TimerBlock *tb)
  67 {
  68     return (((tb->control >> 8) & 0xff) + 1) * 10;
  69 }
  70
  71 static void timerblock_reload(TimerBlock *tb, int restart)
  72 {
  73     if (tb->count == 0) {
  74         return;
  75     }
  76     if (restart) {
  77         tb->tick = qemu_get_clock_ns(vm_clock);
  78     }
  79     tb->tick += (int64_t)tb->count * timerblock_scale(tb);
  80     qemu_mod_timer(tb->timer, tb->tick);
  81 }
  82
  83 static void timerblock_tick(void *opaque)
  84 {
  85     TimerBlock *tb = (TimerBlock *)opaque;
  86     tb->status = 1;
  87     if (tb->control & 2) {
  88         tb->count = tb->load;
  89         timerblock_reload(tb, 0);
  90     } else {
  91         tb->count = 0;
  92     }
  93     timerblock_update_irq(tb);
  94 }
  95
  96 static uint64_t timerblock_read(void *opaque, hwaddr addr,
  97                                 unsigned size)
  98 {
  99     TimerBlock *tb = (TimerBlock *)opaque;
 100     int64_t val;
 101     switch (addr) {
 102     case 0: /* Load */
 103         return tb->load;
 104     case 4: /* Counter.  */
 105         if (((tb->control & 1) == 0) || (tb->count == 0)) {
 106             return 0;
 107         }
 108         /* Slow and ugly, but hopefully won't happen too often.  */
 109         val = tb->tick - qemu_get_clock_ns(vm_clock);
 110         val /= timerblock_scale(tb);
 111         if (val < 0) {
 112             val = 0;
 113         }
 114         return val;
 115     case 8: /* Control.  */
 116         return tb->control;
 117     case 12: /* Interrupt status.  */
 118         return tb->status;
 119     default:
 120         return 0;
 121     }
 122 }
 123
 124 static void timerblock_write(void *opaque, hwaddr addr,
 125                              uint64_t value, unsigned size)
 126 {
 127     TimerBlock *tb = (TimerBlock *)opaque;
 128     int64_t old;
 129     switch (addr) {
 130     case 0: /* Load */
 131         tb->load = value;
 132         /* Fall through.  */
 133     case 4: /* Counter.  */
 134         if ((tb->control & 1) && tb->count) {
 135             /* Cancel the previous timer.  */
 136             qemu_del_timer(tb->timer);
 137         }
 138         tb->count = value;
 139         if (tb->control & 1) {
 140             timerblock_reload(tb, 1);
 141         }
 142         break;
 143     case 8: /* Control.  */
 144         old = tb->control;
 145         tb->control = value;
 146         if (((old & 1) == 0) && (value & 1)) {
 147             if (tb->count == 0 && (tb->control & 2)) {
 148                 tb->count = tb->load;
 149             }
 150             timerblock_reload(tb, 1);
 151         }
 152         break;
 153     case 12: /* Interrupt status.  */
 154         tb->status &= ~value;
 155         timerblock_update_irq(tb);
 156         break;
 157     }
 158 }
 159
 160 /* Wrapper functions to implement the "read timer/watchdog for
 161  * the current CPU" memory regions.
 162  */
 163 static uint64_t arm_thistimer_read(void *opaque, hwaddr addr,
 164                                    unsigned size)
 165 {
 166     ARMMPTimerState *s = (ARMMPTimerState *)opaque;
 167     int id = get_current_cpu(s);
 168     return timerblock_read(&s->timerblock[id], addr, size);
 169 }
 170
 171 static void arm_thistimer_write(void *opaque, hwaddr addr,
 172                                 uint64_t value, unsigned size)
 173 {
 174     ARMMPTimerState *s = (ARMMPTimerState *)opaque;
 175     int id = get_current_cpu(s);
 176     timerblock_write(&s->timerblock[id], addr, value, size);
 177 }
 178
 179 static const MemoryRegionOps arm_thistimer_ops = {
 180     .read = arm_thistimer_read,
 181     .write = arm_thistimer_write,
 182     .valid = {
 183         .min_access_size = 4,
 184         .max_access_size = 4,
 185     },
 186     .endianness = DEVICE_NATIVE_ENDIAN,
 187 };
 188
 189 static const MemoryRegionOps timerblock_ops = {
 190     .read = timerblock_read,
 191     .write = timerblock_write,
 192     .valid = {
 193         .min_access_size = 4,
 194         .max_access_size = 4,
 195     },
 196     .endianness = DEVICE_NATIVE_ENDIAN,
 197 };
 198
 199 static void timerblock_reset(TimerBlock *tb)
 200 {
 201     tb->count = 0;
 202     tb->load = 0;
 203     tb->control = 0;
 204     tb->status = 0;
 205     tb->tick = 0;
 206     if (tb->timer) {
 207         qemu_del_timer(tb->timer);
 208     }
 209 }
 210
 211 static void arm_mptimer_reset(DeviceState *dev)
 212 {
 213     ARMMPTimerState *s =
 214         FROM_SYSBUS(ARMMPTimerState, SYS_BUS_DEVICE(dev));
 215     int i;
 216     for (i = 0; i < ARRAY_SIZE(s->timerblock); i++) {
 217         timerblock_reset(&s->timerblock[i]);
 218     }
 219 }
 220
 221 static int arm_mptimer_init(SysBusDevice *dev)
 222 {
 223     ARMMPTimerState *s = FROM_SYSBUS(ARMMPTimerState, dev);
 224     int i;
 225     if (s->num_cpu < 1 || s->num_cpu > MAX_CPUS) {
 226         hw_error("%s: num-cpu must be between 1 and %d\n", __func__, MAX_CPUS);
 227     }
 228     /* We implement one timer block per CPU, and expose multiple MMIO regions:
 229      *  * region 0 is "timer for this core"
 230      *  * region 1 is "timer for core 0"
 231      *  * region 2 is "timer for core 1"
 232      * and so on.
 233      * The outgoing interrupt lines are
 234      *  * timer for core 0
 235      *  * timer for core 1
 236      * and so on.
 237      */
 238     memory_region_init_io(&s->iomem, OBJECT(s), &arm_thistimer_ops, s,
 239                           "arm_mptimer_timer", 0x20);
 240     sysbus_init_mmio(dev, &s->iomem);
 241     for (i = 0; i < s->num_cpu; i++) {
 242         TimerBlock *tb = &s->timerblock[i];
 243         tb->timer = qemu_new_timer_ns(vm_clock, timerblock_tick, tb);
 244         sysbus_init_irq(dev, &tb->irq);
 245         memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb,
 246                               "arm_mptimer_timerblock", 0x20);
 247         sysbus_init_mmio(dev, &tb->iomem);
 248     }
 249
 250     return 0;
 251 }
 252
 253 static const VMStateDescription vmstate_timerblock = {
 254     .name = "arm_mptimer_timerblock",
 255     .version_id = 2,
 256     .minimum_version_id = 2,
 257     .fields = (VMStateField[]) {
 258         VMSTATE_UINT32(count, TimerBlock),
 259         VMSTATE_UINT32(load, TimerBlock),
 260         VMSTATE_UINT32(control, TimerBlock),
 261         VMSTATE_UINT32(status, TimerBlock),
 262         VMSTATE_INT64(tick, TimerBlock),
 263         VMSTATE_TIMER(timer, TimerBlock),
 264         VMSTATE_END_OF_LIST()
 265     }
 266 };
 267
 268 static const VMStateDescription vmstate_arm_mptimer = {
 269     .name = "arm_mptimer",
 270     .version_id = 2,
 271     .minimum_version_id = 2,
 272     .fields = (VMStateField[]) {
 273         VMSTATE_STRUCT_VARRAY_UINT32(timerblock, ARMMPTimerState, num_cpu,
 274                                      2, vmstate_timerblock, TimerBlock),
 275         VMSTATE_END_OF_LIST()
 276     }
 277 };
 278
 279 static Property arm_mptimer_properties[] = {
 280     DEFINE_PROP_UINT32("num-cpu", ARMMPTimerState, num_cpu, 0),
 281     DEFINE_PROP_END_OF_LIST()
 282 };
 283
 284 static void arm_mptimer_class_init(ObjectClass *klass, void *data)
 285 {
 286     DeviceClass *dc = DEVICE_CLASS(klass);
 287     SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
 288
 289     sbc->init = arm_mptimer_init;
 290     dc->vmsd = &vmstate_arm_mptimer;
 291     dc->reset = arm_mptimer_reset;
 292     dc->no_user = 1;
 293     dc->props = arm_mptimer_properties;
 294 }
 295
 296 static const TypeInfo arm_mptimer_info = {
 297     .name          = "arm_mptimer",
 298     .parent        = TYPE_SYS_BUS_DEVICE,
 299     .instance_size = sizeof(ARMMPTimerState),
 300     .class_init    = arm_mptimer_class_init,
 301 };
 302
 303 static void arm_mptimer_register_types(void)
 304 {
 305     type_register_static(&arm_mptimer_info);
 306 }
 307
 308 type_init(arm_mptimer_register_types)