hw/timer/etraxfs_timer.c

   1 /*
   2  * QEMU ETRAX Timers
   3  *
   4  * Copyright (c) 2007 Edgar E. Iglesias, Axis Communications AB.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "qemu/osdep.h"
  26 #include "hw/sysbus.h"
  27 #include "sysemu/reset.h"
  28 #include "sysemu/sysemu.h"
  29 #include "qemu/module.h"
  30 #include "qemu/timer.h"
  31 #include "hw/ptimer.h"
  32
  33 #define D(x)
  34
  35 #define RW_TMR0_DIV   0x00
  36 #define R_TMR0_DATA   0x04
  37 #define RW_TMR0_CTRL  0x08
  38 #define RW_TMR1_DIV   0x10
  39 #define R_TMR1_DATA   0x14
  40 #define RW_TMR1_CTRL  0x18
  41 #define R_TIME        0x38
  42 #define RW_WD_CTRL    0x40
  43 #define R_WD_STAT     0x44
  44 #define RW_INTR_MASK  0x48
  45 #define RW_ACK_INTR   0x4c
  46 #define R_INTR        0x50
  47 #define R_MASKED_INTR 0x54
  48
  49 #define TYPE_ETRAX_FS_TIMER "etraxfs,timer"
  50 #define ETRAX_TIMER(obj) \
  51     OBJECT_CHECK(ETRAXTimerState, (obj), TYPE_ETRAX_FS_TIMER)
  52
  53 typedef struct ETRAXTimerState {
  54     SysBusDevice parent_obj;
  55
  56     MemoryRegion mmio;
  57     qemu_irq irq;
  58     qemu_irq nmi;
  59
  60     QEMUBH *bh_t0;
  61     QEMUBH *bh_t1;
  62     QEMUBH *bh_wd;
  63     ptimer_state *ptimer_t0;
  64     ptimer_state *ptimer_t1;
  65     ptimer_state *ptimer_wd;
  66
  67     int wd_hits;
  68
  69     /* Control registers.  */
  70     uint32_t rw_tmr0_div;
  71     uint32_t r_tmr0_data;
  72     uint32_t rw_tmr0_ctrl;
  73
  74     uint32_t rw_tmr1_div;
  75     uint32_t r_tmr1_data;
  76     uint32_t rw_tmr1_ctrl;
  77
  78     uint32_t rw_wd_ctrl;
  79
  80     uint32_t rw_intr_mask;
  81     uint32_t rw_ack_intr;
  82     uint32_t r_intr;
  83     uint32_t r_masked_intr;
  84 } ETRAXTimerState;
  85
  86 static uint64_t
  87 timer_read(void *opaque, hwaddr addr, unsigned int size)
  88 {
  89     ETRAXTimerState *t = opaque;
  90     uint32_t r = 0;
  91
  92     switch (addr) {
  93     case R_TMR0_DATA:
  94         r = ptimer_get_count(t->ptimer_t0);
  95         break;
  96     case R_TMR1_DATA:
  97         r = ptimer_get_count(t->ptimer_t1);
  98         break;
  99     case R_TIME:
 100         r = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / 10;
 101         break;
 102     case RW_INTR_MASK:
 103         r = t->rw_intr_mask;
 104         break;
 105     case R_MASKED_INTR:
 106         r = t->r_intr & t->rw_intr_mask;
 107         break;
 108     default:
 109         D(printf ("%s %x\n", __func__, addr));
 110         break;
 111     }
 112     return r;
 113 }
 114
 115 static void update_ctrl(ETRAXTimerState *t, int tnum)
 116 {
 117     unsigned int op;
 118     unsigned int freq;
 119     unsigned int freq_hz;
 120     unsigned int div;
 121     uint32_t ctrl;
 122
 123     ptimer_state *timer;
 124
 125     if (tnum == 0) {
 126         ctrl = t->rw_tmr0_ctrl;
 127         div = t->rw_tmr0_div;
 128         timer = t->ptimer_t0;
 129     } else {
 130         ctrl = t->rw_tmr1_ctrl;
 131         div = t->rw_tmr1_div;
 132         timer = t->ptimer_t1;
 133     }
 134
 135
 136     op = ctrl & 3;
 137     freq = ctrl >> 2;
 138     freq_hz = 32000000;
 139
 140     switch (freq)
 141     {
 142     case 0:
 143     case 1:
 144         D(printf ("extern or disabled timer clock?\n"));
 145         break;
 146     case 4: freq_hz =  29493000; break;
 147     case 5: freq_hz =  32000000; break;
 148     case 6: freq_hz =  32768000; break;
 149     case 7: freq_hz = 100000000; break;
 150     default:
 151         abort();
 152         break;
 153     }
 154
 155     D(printf ("freq_hz=%d div=%d\n", freq_hz, div));
 156     ptimer_set_freq(timer, freq_hz);
 157     ptimer_set_limit(timer, div, 0);
 158
 159     switch (op)
 160     {
 161         case 0:
 162             /* Load.  */
 163             ptimer_set_limit(timer, div, 1);
 164             break;
 165         case 1:
 166             /* Hold.  */
 167             ptimer_stop(timer);
 168             break;
 169         case 2:
 170             /* Run.  */
 171             ptimer_run(timer, 0);
 172             break;
 173         default:
 174             abort();
 175             break;
 176     }
 177 }
 178
 179 static void timer_update_irq(ETRAXTimerState *t)
 180 {
 181     t->r_intr &= ~(t->rw_ack_intr);
 182     t->r_masked_intr = t->r_intr & t->rw_intr_mask;
 183
 184     D(printf("%s: masked_intr=%x\n", __func__, t->r_masked_intr));
 185     qemu_set_irq(t->irq, !!t->r_masked_intr);
 186 }
 187
 188 static void timer0_hit(void *opaque)
 189 {
 190     ETRAXTimerState *t = opaque;
 191     t->r_intr |= 1;
 192     timer_update_irq(t);
 193 }
 194
 195 static void timer1_hit(void *opaque)
 196 {
 197     ETRAXTimerState *t = opaque;
 198     t->r_intr |= 2;
 199     timer_update_irq(t);
 200 }
 201
 202 static void watchdog_hit(void *opaque)
 203 {
 204     ETRAXTimerState *t = opaque;
 205     if (t->wd_hits == 0) {
 206         /* real hw gives a single tick before reseting but we are
 207            a bit friendlier to compensate for our slower execution.  */
 208         ptimer_set_count(t->ptimer_wd, 10);
 209         ptimer_run(t->ptimer_wd, 1);
 210         qemu_irq_raise(t->nmi);
 211     }
 212     else
 213         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 214
 215     t->wd_hits++;
 216 }
 217
 218 static inline void timer_watchdog_update(ETRAXTimerState *t, uint32_t value)
 219 {
 220     unsigned int wd_en = t->rw_wd_ctrl & (1 << 8);
 221     unsigned int wd_key = t->rw_wd_ctrl >> 9;
 222     unsigned int wd_cnt = t->rw_wd_ctrl & 511;
 223     unsigned int new_key = value >> 9 & ((1 << 7) - 1);
 224     unsigned int new_cmd = (value >> 8) & 1;
 225
 226     /* If the watchdog is enabled, they written key must match the
 227        complement of the previous.  */
 228     wd_key = ~wd_key & ((1 << 7) - 1);
 229
 230     if (wd_en && wd_key != new_key)
 231         return;
 232
 233     D(printf("en=%d new_key=%x oldkey=%x cmd=%d cnt=%d\n",
 234          wd_en, new_key, wd_key, new_cmd, wd_cnt));
 235
 236     if (t->wd_hits)
 237         qemu_irq_lower(t->nmi);
 238
 239     t->wd_hits = 0;
 240
 241     ptimer_set_freq(t->ptimer_wd, 760);
 242     if (wd_cnt == 0)
 243         wd_cnt = 256;
 244     ptimer_set_count(t->ptimer_wd, wd_cnt);
 245     if (new_cmd)
 246         ptimer_run(t->ptimer_wd, 1);
 247     else
 248         ptimer_stop(t->ptimer_wd);
 249
 250     t->rw_wd_ctrl = value;
 251 }
 252
 253 static void
 254 timer_write(void *opaque, hwaddr addr,
 255             uint64_t val64, unsigned int size)
 256 {
 257     ETRAXTimerState *t = opaque;
 258     uint32_t value = val64;
 259
 260     switch (addr)
 261     {
 262         case RW_TMR0_DIV:
 263             t->rw_tmr0_div = value;
 264             break;
 265         case RW_TMR0_CTRL:
 266             D(printf ("RW_TMR0_CTRL=%x\n", value));
 267             t->rw_tmr0_ctrl = value;
 268             update_ctrl(t, 0);
 269             break;
 270         case RW_TMR1_DIV:
 271             t->rw_tmr1_div = value;
 272             break;
 273         case RW_TMR1_CTRL:
 274             D(printf ("RW_TMR1_CTRL=%x\n", value));
 275             t->rw_tmr1_ctrl = value;
 276             update_ctrl(t, 1);
 277             break;
 278         case RW_INTR_MASK:
 279             D(printf ("RW_INTR_MASK=%x\n", value));
 280             t->rw_intr_mask = value;
 281             timer_update_irq(t);
 282             break;
 283         case RW_WD_CTRL:
 284             timer_watchdog_update(t, value);
 285             break;
 286         case RW_ACK_INTR:
 287             t->rw_ack_intr = value;
 288             timer_update_irq(t);
 289             t->rw_ack_intr = 0;
 290             break;
 291         default:
 292             printf ("%s " TARGET_FMT_plx " %x\n",
 293                 __func__, addr, value);
 294             break;
 295     }
 296 }
 297
 298 static const MemoryRegionOps timer_ops = {
 299     .read = timer_read,
 300     .write = timer_write,
 301     .endianness = DEVICE_LITTLE_ENDIAN,
 302     .valid = {
 303         .min_access_size = 4,
 304         .max_access_size = 4
 305     }
 306 };
 307
 308 static void etraxfs_timer_reset(void *opaque)
 309 {
 310     ETRAXTimerState *t = opaque;
 311
 312     ptimer_stop(t->ptimer_t0);
 313     ptimer_stop(t->ptimer_t1);
 314     ptimer_stop(t->ptimer_wd);
 315     t->rw_wd_ctrl = 0;
 316     t->r_intr = 0;
 317     t->rw_intr_mask = 0;
 318     qemu_irq_lower(t->irq);
 319 }
 320
 321 static void etraxfs_timer_realize(DeviceState *dev, Error **errp)
 322 {
 323     ETRAXTimerState *t = ETRAX_TIMER(dev);
 324     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 325
 326     t->bh_t0 = qemu_bh_new(timer0_hit, t);
 327     t->bh_t1 = qemu_bh_new(timer1_hit, t);
 328     t->bh_wd = qemu_bh_new(watchdog_hit, t);
 329     t->ptimer_t0 = ptimer_init(t->bh_t0, PTIMER_POLICY_DEFAULT);
 330     t->ptimer_t1 = ptimer_init(t->bh_t1, PTIMER_POLICY_DEFAULT);
 331     t->ptimer_wd = ptimer_init(t->bh_wd, PTIMER_POLICY_DEFAULT);
 332
 333     sysbus_init_irq(sbd, &t->irq);
 334     sysbus_init_irq(sbd, &t->nmi);
 335
 336     memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
 337                           "etraxfs-timer", 0x5c);
 338     sysbus_init_mmio(sbd, &t->mmio);
 339     qemu_register_reset(etraxfs_timer_reset, t);
 340 }
 341
 342 static void etraxfs_timer_class_init(ObjectClass *klass, void *data)
 343 {
 344     DeviceClass *dc = DEVICE_CLASS(klass);
 345
 346     dc->realize = etraxfs_timer_realize;
 347 }
 348
 349 static const TypeInfo etraxfs_timer_info = {
 350     .name          = TYPE_ETRAX_FS_TIMER,
 351     .parent        = TYPE_SYS_BUS_DEVICE,
 352     .instance_size = sizeof(ETRAXTimerState),
 353     .class_init    = etraxfs_timer_class_init,
 354 };
 355
 356 static void etraxfs_timer_register_types(void)
 357 {
 358     type_register_static(&etraxfs_timer_info);
 359 }
 360
 361 type_init(etraxfs_timer_register_types)