2 * Samsung exynos4210 Multi Core timer
4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
7 * Evgeny Voevodin <e.voevodin@samsung.com>
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License as published by the
11 * Free Software Foundation; either version 2 of the License, or (at your
12 * option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
17 * See the GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License along
20 * with this program; if not, see <http://www.gnu.org/licenses/>.
26 * Consists of two timers. First represents Free Running Counter and second
27 * is used to measure interval from FRC to nearest comparator.
31 * | <-------------------------------------------------------------- |
32 * | --------------------------------------------frc---------------> |
33 * |______________________________________________|__________________|
34 * CMP0 CMP1 CMP2 | CMP3
40 * Problem: when implementing global timer as is, overflow arises.
41 * next_time = cur_time + period * count;
42 * period and count are 64 bits width.
43 * Lets arm timer for MCT_GT_COUNTER_STEP count and update internal G_CNT
44 * register during each event.
46 * Problem: both timers need to be implemented using MCT_XT_COUNTER_STEP because
47 * local timer contains two counters: TCNT and ICNT. TCNT == 0 -> ICNT--.
48 * IRQ is generated when ICNT riches zero. Implementation where TCNT == 0
49 * generates IRQs suffers from too frequently events. Better to have one
50 * uint64_t counter equal to TCNT*ICNT and arm ptimer.c for a minimum(TCNT*ICNT,
51 * MCT_GT_COUNTER_STEP); (yes, if target tunes ICNT * TCNT to be too low values,
52 * there is no way to avoid frequently events).
55 #include "qemu/osdep.h"
58 #include "hw/sysbus.h"
59 #include "migration/vmstate.h"
60 #include "qemu/timer.h"
61 #include "qemu/main-loop.h"
62 #include "qemu/module.h"
63 #include "hw/ptimer.h"
65 #include "hw/arm/exynos4210.h"
72 #define DPRINTF(fmt, ...) \
73 do { fprintf(stdout, "MCT: [%24s:%5d] " fmt, __func__, __LINE__, \
74 ## __VA_ARGS__); } while (0)
76 #define DPRINTF(fmt, ...) do {} while (0)
82 #define G_CNT_WSTAT 0x110
83 #define G_COMP0_L 0x200
84 #define G_COMP0_U 0x204
85 #define G_COMP0_ADD_INCR 0x208
86 #define G_COMP1_L 0x210
87 #define G_COMP1_U 0x214
88 #define G_COMP1_ADD_INCR 0x218
89 #define G_COMP2_L 0x220
90 #define G_COMP2_U 0x224
91 #define G_COMP2_ADD_INCR 0x228
92 #define G_COMP3_L 0x230
93 #define G_COMP3_U 0x234
94 #define G_COMP3_ADD_INCR 0x238
96 #define G_INT_CSTAT 0x244
97 #define G_INT_ENB 0x248
99 #define L0_TCNTB 0x300
100 #define L0_TCNTO 0x304
101 #define L0_ICNTB 0x308
102 #define L0_ICNTO 0x30C
103 #define L0_FRCNTB 0x310
104 #define L0_FRCNTO 0x314
105 #define L0_TCON 0x320
106 #define L0_INT_CSTAT 0x330
107 #define L0_INT_ENB 0x334
108 #define L0_WSTAT 0x340
109 #define L1_TCNTB 0x400
110 #define L1_TCNTO 0x404
111 #define L1_ICNTB 0x408
112 #define L1_ICNTO 0x40C
113 #define L1_FRCNTB 0x410
114 #define L1_FRCNTO 0x414
115 #define L1_TCON 0x420
116 #define L1_INT_CSTAT 0x430
117 #define L1_INT_ENB 0x434
118 #define L1_WSTAT 0x440
120 #define MCT_CFG_GET_PRESCALER(x) ((x) & 0xFF)
121 #define MCT_CFG_GET_DIVIDER(x) (1 << ((x) >> 8 & 7))
123 #define GET_G_COMP_IDX(offset) (((offset) - G_COMP0_L) / 0x10)
124 #define GET_G_COMP_ADD_INCR_IDX(offset) (((offset) - G_COMP0_ADD_INCR) / 0x10)
126 #define G_COMP_L(x) (G_COMP0_L + (x) * 0x10)
127 #define G_COMP_U(x) (G_COMP0_U + (x) * 0x10)
129 #define G_COMP_ADD_INCR(x) (G_COMP0_ADD_INCR + (x) * 0x10)
132 #define G_TCON_COMP_ENABLE(x) (1 << 2 * (x))
133 #define G_TCON_AUTO_ICREMENT(x) (1 << (2 * (x) + 1))
134 #define G_TCON_TIMER_ENABLE (1 << 8)
136 #define G_INT_ENABLE(x) (1 << (x))
137 #define G_INT_CSTAT_COMP(x) (1 << (x))
139 #define G_CNT_WSTAT_L 1
140 #define G_CNT_WSTAT_U 2
142 #define G_WSTAT_COMP_L(x) (1 << 4 * (x))
143 #define G_WSTAT_COMP_U(x) (1 << ((4 * (x)) + 1))
144 #define G_WSTAT_COMP_ADDINCR(x) (1 << ((4 * (x)) + 2))
145 #define G_WSTAT_TCON_WRITE (1 << 16)
147 #define GET_L_TIMER_IDX(offset) ((((offset) & 0xF00) - L0_TCNTB) / 0x100)
148 #define GET_L_TIMER_CNT_REG_IDX(offset, lt_i) \
149 (((offset) - (L0_TCNTB + 0x100 * (lt_i))) >> 2)
151 #define L_ICNTB_MANUAL_UPDATE (1 << 31)
153 #define L_TCON_TICK_START (1)
154 #define L_TCON_INT_START (1 << 1)
155 #define L_TCON_INTERVAL_MODE (1 << 2)
156 #define L_TCON_FRC_START (1 << 3)
158 #define L_INT_CSTAT_INTCNT (1 << 0)
159 #define L_INT_CSTAT_FRCCNT (1 << 1)
161 #define L_INT_INTENB_ICNTEIE (1 << 0)
162 #define L_INT_INTENB_FRCEIE (1 << 1)
164 #define L_WSTAT_TCNTB_WRITE (1 << 0)
165 #define L_WSTAT_ICNTB_WRITE (1 << 1)
166 #define L_WSTAT_FRCCNTB_WRITE (1 << 2)
167 #define L_WSTAT_TCON_WRITE (1 << 3)
169 enum LocalTimerRegCntIndexes
{
180 #define MCT_SFR_SIZE 0x444
182 #define MCT_GT_CMP_NUM 4
184 #define MCT_GT_COUNTER_STEP 0x100000000ULL
185 #define MCT_LT_COUNTER_STEP 0x100000000ULL
186 #define MCT_LT_CNT_LOW_LIMIT 0x100
190 qemu_irq irq
[MCT_GT_CMP_NUM
];
199 uint64_t comp
[MCT_GT_CMP_NUM
];
200 uint32_t comp_add_incr
[MCT_GT_CMP_NUM
];
203 uint64_t count
; /* Value FRC was armed with */
204 int32_t curr_comp
; /* Current comparator FRC is running to */
206 ptimer_state
*ptimer_frc
; /* FRC timer */
212 int id
; /* timer id */
213 qemu_irq irq
; /* local timer irq */
216 uint32_t cnt_run
; /* cnt timer is running */
217 uint32_t int_run
; /* int timer is running */
221 uint32_t tcntb
; /* initial value for TCNTB */
222 uint32_t icntb
; /* initial value for ICNTB */
225 uint64_t distance
; /* distance to count to the next event */
226 uint64_t progress
; /* progress when counting by steps */
227 uint64_t count
; /* count to arm timer with */
229 ptimer_state
*ptimer_tick
; /* timer for tick counter */
232 /* use ptimer.c to represent count down timer */
234 ptimer_state
*ptimer_frc
; /* timer for free running counter */
238 uint32_t cnt
[L_REG_CNT_AMOUNT
];
247 #define TYPE_EXYNOS4210_MCT "exynos4210.mct"
248 #define EXYNOS4210_MCT(obj) \
249 OBJECT_CHECK(Exynos4210MCTState, (obj), TYPE_EXYNOS4210_MCT)
251 typedef struct Exynos4210MCTState
{
252 SysBusDevice parent_obj
;
257 uint32_t reg_mct_cfg
;
259 Exynos4210MCTLT l_timer
[2];
260 Exynos4210MCTGT g_timer
;
262 uint32_t freq
; /* all timers tick frequency, TCLK */
263 } Exynos4210MCTState
;
266 static const VMStateDescription vmstate_tick_timer
= {
267 .name
= "exynos4210.mct.tick_timer",
269 .minimum_version_id
= 1,
270 .fields
= (VMStateField
[]) {
271 VMSTATE_UINT32(cnt_run
, struct tick_timer
),
272 VMSTATE_UINT32(int_run
, struct tick_timer
),
273 VMSTATE_UINT32(last_icnto
, struct tick_timer
),
274 VMSTATE_UINT32(last_tcnto
, struct tick_timer
),
275 VMSTATE_UINT32(tcntb
, struct tick_timer
),
276 VMSTATE_UINT32(icntb
, struct tick_timer
),
277 VMSTATE_UINT64(distance
, struct tick_timer
),
278 VMSTATE_UINT64(progress
, struct tick_timer
),
279 VMSTATE_UINT64(count
, struct tick_timer
),
280 VMSTATE_PTIMER(ptimer_tick
, struct tick_timer
),
281 VMSTATE_END_OF_LIST()
285 static const VMStateDescription vmstate_lregs
= {
286 .name
= "exynos4210.mct.lregs",
288 .minimum_version_id
= 1,
289 .fields
= (VMStateField
[]) {
290 VMSTATE_UINT32_ARRAY(cnt
, struct lregs
, L_REG_CNT_AMOUNT
),
291 VMSTATE_UINT32(tcon
, struct lregs
),
292 VMSTATE_UINT32(int_cstat
, struct lregs
),
293 VMSTATE_UINT32(int_enb
, struct lregs
),
294 VMSTATE_UINT32(wstat
, struct lregs
),
295 VMSTATE_END_OF_LIST()
299 static const VMStateDescription vmstate_exynos4210_mct_lt
= {
300 .name
= "exynos4210.mct.lt",
302 .minimum_version_id
= 1,
303 .fields
= (VMStateField
[]) {
304 VMSTATE_INT32(id
, Exynos4210MCTLT
),
305 VMSTATE_STRUCT(tick_timer
, Exynos4210MCTLT
, 0,
308 VMSTATE_PTIMER(ptimer_frc
, Exynos4210MCTLT
),
309 VMSTATE_STRUCT(reg
, Exynos4210MCTLT
, 0,
312 VMSTATE_END_OF_LIST()
316 static const VMStateDescription vmstate_gregs
= {
317 .name
= "exynos4210.mct.lregs",
319 .minimum_version_id
= 1,
320 .fields
= (VMStateField
[]) {
321 VMSTATE_UINT64(cnt
, struct gregs
),
322 VMSTATE_UINT32(cnt_wstat
, struct gregs
),
323 VMSTATE_UINT32(tcon
, struct gregs
),
324 VMSTATE_UINT32(int_cstat
, struct gregs
),
325 VMSTATE_UINT32(int_enb
, struct gregs
),
326 VMSTATE_UINT32(wstat
, struct gregs
),
327 VMSTATE_UINT64_ARRAY(comp
, struct gregs
, MCT_GT_CMP_NUM
),
328 VMSTATE_UINT32_ARRAY(comp_add_incr
, struct gregs
,
330 VMSTATE_END_OF_LIST()
334 static const VMStateDescription vmstate_exynos4210_mct_gt
= {
335 .name
= "exynos4210.mct.lt",
337 .minimum_version_id
= 1,
338 .fields
= (VMStateField
[]) {
339 VMSTATE_STRUCT(reg
, Exynos4210MCTGT
, 0, vmstate_gregs
,
341 VMSTATE_UINT64(count
, Exynos4210MCTGT
),
342 VMSTATE_INT32(curr_comp
, Exynos4210MCTGT
),
343 VMSTATE_PTIMER(ptimer_frc
, Exynos4210MCTGT
),
344 VMSTATE_END_OF_LIST()
348 static const VMStateDescription vmstate_exynos4210_mct_state
= {
349 .name
= "exynos4210.mct",
351 .minimum_version_id
= 1,
352 .fields
= (VMStateField
[]) {
353 VMSTATE_UINT32(reg_mct_cfg
, Exynos4210MCTState
),
354 VMSTATE_STRUCT_ARRAY(l_timer
, Exynos4210MCTState
, 2, 0,
355 vmstate_exynos4210_mct_lt
, Exynos4210MCTLT
),
356 VMSTATE_STRUCT(g_timer
, Exynos4210MCTState
, 0,
357 vmstate_exynos4210_mct_gt
, Exynos4210MCTGT
),
358 VMSTATE_UINT32(freq
, Exynos4210MCTState
),
359 VMSTATE_END_OF_LIST()
363 static void exynos4210_mct_update_freq(Exynos4210MCTState
*s
);
366 * Set counter of FRC global timer.
367 * Must be called within exynos4210_gfrc_tx_begin/commit block.
369 static void exynos4210_gfrc_set_count(Exynos4210MCTGT
*s
, uint64_t count
)
372 DPRINTF("global timer frc set count 0x%llx\n", count
);
373 ptimer_set_count(s
->ptimer_frc
, count
);
377 * Get counter of FRC global timer.
379 static uint64_t exynos4210_gfrc_get_count(Exynos4210MCTGT
*s
)
382 count
= ptimer_get_count(s
->ptimer_frc
);
383 count
= s
->count
- count
;
384 return s
->reg
.cnt
+ count
;
388 * Stop global FRC timer
389 * Must be called within exynos4210_gfrc_tx_begin/commit block.
391 static void exynos4210_gfrc_stop(Exynos4210MCTGT
*s
)
393 DPRINTF("global timer frc stop\n");
395 ptimer_stop(s
->ptimer_frc
);
399 * Start global FRC timer
400 * Must be called within exynos4210_gfrc_tx_begin/commit block.
402 static void exynos4210_gfrc_start(Exynos4210MCTGT
*s
)
404 DPRINTF("global timer frc start\n");
406 ptimer_run(s
->ptimer_frc
, 1);
410 * Start ptimer transaction for global FRC timer; this is just for
411 * consistency with the way we wrap operations like stop and run.
413 static void exynos4210_gfrc_tx_begin(Exynos4210MCTGT
*s
)
415 ptimer_transaction_begin(s
->ptimer_frc
);
418 /* Commit ptimer transaction for global FRC timer. */
419 static void exynos4210_gfrc_tx_commit(Exynos4210MCTGT
*s
)
421 ptimer_transaction_commit(s
->ptimer_frc
);
425 * Find next nearest Comparator. If current Comparator value equals to other
426 * Comparator value, skip them both
428 static int32_t exynos4210_gcomp_find(Exynos4210MCTState
*s
)
437 uint64_t distance_min
;
441 gfrc
= exynos4210_gfrc_get_count(&s
->g_timer
);
444 distance_min
= UINT64_MAX
;
445 comp_i
= MCT_GT_CMP_NUM
;
446 min_comp_i
= MCT_GT_CMP_NUM
;
449 /* lookup for nearest comparator */
450 for (i
= 0; i
< MCT_GT_CMP_NUM
; i
++) {
452 if (s
->g_timer
.reg
.tcon
& G_TCON_COMP_ENABLE(i
)) {
456 if (s
->g_timer
.reg
.comp
[i
] > gfrc
) {
457 /* Comparator is upper then FRC */
458 distance
= s
->g_timer
.reg
.comp
[i
] - gfrc
;
460 if (distance
<= distance_min
) {
461 distance_min
= distance
;
465 /* Comparator is below FRC, find the smallest */
467 if (s
->g_timer
.reg
.comp
[i
] <= min
) {
468 min
= s
->g_timer
.reg
.comp
[i
];
476 /* All Comparators disabled */
478 } else if (comp_i
< MCT_GT_CMP_NUM
) {
479 /* Found upper Comparator */
482 /* All Comparators are below or equal to FRC */
486 DPRINTF("found comparator %d: comp 0x%llx distance 0x%llx, gfrc 0x%llx\n",
488 s
->g_timer
.reg
.comp
[res
],
496 * Get distance to nearest Comparator
498 static uint64_t exynos4210_gcomp_get_distance(Exynos4210MCTState
*s
, int32_t id
)
501 /* no enabled Comparators, choose max distance */
502 return MCT_GT_COUNTER_STEP
;
504 if (s
->g_timer
.reg
.comp
[id
] - s
->g_timer
.reg
.cnt
< MCT_GT_COUNTER_STEP
) {
505 return s
->g_timer
.reg
.comp
[id
] - s
->g_timer
.reg
.cnt
;
507 return MCT_GT_COUNTER_STEP
;
512 * Restart global FRC timer
513 * Must be called within exynos4210_gfrc_tx_begin/commit block.
515 static void exynos4210_gfrc_restart(Exynos4210MCTState
*s
)
519 exynos4210_gfrc_stop(&s
->g_timer
);
521 s
->g_timer
.curr_comp
= exynos4210_gcomp_find(s
);
523 distance
= exynos4210_gcomp_get_distance(s
, s
->g_timer
.curr_comp
);
525 if (distance
> MCT_GT_COUNTER_STEP
|| !distance
) {
526 distance
= MCT_GT_COUNTER_STEP
;
529 exynos4210_gfrc_set_count(&s
->g_timer
, distance
);
530 exynos4210_gfrc_start(&s
->g_timer
);
534 * Raise global timer CMP IRQ
536 static void exynos4210_gcomp_raise_irq(void *opaque
, uint32_t id
)
538 Exynos4210MCTGT
*s
= opaque
;
540 /* If CSTAT is pending and IRQ is enabled */
541 if ((s
->reg
.int_cstat
& G_INT_CSTAT_COMP(id
)) &&
542 (s
->reg
.int_enb
& G_INT_ENABLE(id
))) {
543 DPRINTF("gcmp timer[%d] IRQ\n", id
);
544 qemu_irq_raise(s
->irq
[id
]);
549 * Lower global timer CMP IRQ
551 static void exynos4210_gcomp_lower_irq(void *opaque
, uint32_t id
)
553 Exynos4210MCTGT
*s
= opaque
;
554 qemu_irq_lower(s
->irq
[id
]);
558 * Global timer FRC event handler.
559 * Each event occurs when internal counter reaches counter + MCT_GT_COUNTER_STEP
560 * Every time we arm global FRC timer to count for MCT_GT_COUNTER_STEP value
562 static void exynos4210_gfrc_event(void *opaque
)
564 Exynos4210MCTState
*s
= (Exynos4210MCTState
*)opaque
;
570 s
->g_timer
.reg
.cnt
+= s
->g_timer
.count
;
572 /* Process all comparators */
573 for (i
= 0; i
< MCT_GT_CMP_NUM
; i
++) {
575 if (s
->g_timer
.reg
.cnt
== s
->g_timer
.reg
.comp
[i
]) {
576 /* reached nearest comparator */
578 s
->g_timer
.reg
.int_cstat
|= G_INT_CSTAT_COMP(i
);
581 if (s
->g_timer
.reg
.tcon
& G_TCON_AUTO_ICREMENT(i
)) {
582 s
->g_timer
.reg
.comp
[i
] += s
->g_timer
.reg
.comp_add_incr
[i
];
586 exynos4210_gcomp_raise_irq(&s
->g_timer
, i
);
590 /* Reload FRC to reach nearest comparator */
591 s
->g_timer
.curr_comp
= exynos4210_gcomp_find(s
);
592 distance
= exynos4210_gcomp_get_distance(s
, s
->g_timer
.curr_comp
);
593 if (distance
> MCT_GT_COUNTER_STEP
|| !distance
) {
594 distance
= MCT_GT_COUNTER_STEP
;
596 exynos4210_gfrc_set_count(&s
->g_timer
, distance
);
598 exynos4210_gfrc_start(&s
->g_timer
);
602 * Get counter of FRC local timer.
604 static uint64_t exynos4210_lfrc_get_count(Exynos4210MCTLT
*s
)
606 return ptimer_get_count(s
->ptimer_frc
);
610 * Set counter of FRC local timer.
611 * Must be called from within exynos4210_lfrc_tx_begin/commit block.
613 static void exynos4210_lfrc_update_count(Exynos4210MCTLT
*s
)
615 if (!s
->reg
.cnt
[L_REG_CNT_FRCCNTB
]) {
616 ptimer_set_count(s
->ptimer_frc
, MCT_LT_COUNTER_STEP
);
618 ptimer_set_count(s
->ptimer_frc
, s
->reg
.cnt
[L_REG_CNT_FRCCNTB
]);
623 * Start local FRC timer
624 * Must be called from within exynos4210_lfrc_tx_begin/commit block.
626 static void exynos4210_lfrc_start(Exynos4210MCTLT
*s
)
628 ptimer_run(s
->ptimer_frc
, 1);
632 * Stop local FRC timer
633 * Must be called from within exynos4210_lfrc_tx_begin/commit block.
635 static void exynos4210_lfrc_stop(Exynos4210MCTLT
*s
)
637 ptimer_stop(s
->ptimer_frc
);
640 /* Start ptimer transaction for local FRC timer */
641 static void exynos4210_lfrc_tx_begin(Exynos4210MCTLT
*s
)
643 ptimer_transaction_begin(s
->ptimer_frc
);
646 /* Commit ptimer transaction for local FRC timer */
647 static void exynos4210_lfrc_tx_commit(Exynos4210MCTLT
*s
)
649 ptimer_transaction_commit(s
->ptimer_frc
);
653 * Local timer free running counter tick handler
655 static void exynos4210_lfrc_event(void *opaque
)
657 Exynos4210MCTLT
* s
= (Exynos4210MCTLT
*)opaque
;
659 /* local frc expired */
663 s
->reg
.int_cstat
|= L_INT_CSTAT_FRCCNT
;
665 /* update frc counter */
666 exynos4210_lfrc_update_count(s
);
669 if (s
->reg
.int_enb
& L_INT_INTENB_FRCEIE
) {
670 qemu_irq_raise(s
->irq
);
673 /* we reached here, this means that timer is enabled */
674 exynos4210_lfrc_start(s
);
677 static uint32_t exynos4210_ltick_int_get_cnto(struct tick_timer
*s
);
678 static uint32_t exynos4210_ltick_cnt_get_cnto(struct tick_timer
*s
);
679 static void exynos4210_ltick_recalc_count(struct tick_timer
*s
);
682 * Action on enabling local tick int timer
684 static void exynos4210_ltick_int_start(struct tick_timer
*s
)
692 * Action on disabling local tick int timer
694 static void exynos4210_ltick_int_stop(struct tick_timer
*s
)
697 s
->last_icnto
= exynos4210_ltick_int_get_cnto(s
);
703 * Get count for INT timer
705 static uint32_t exynos4210_ltick_int_get_cnto(struct tick_timer
*s
)
711 uint64_t cur_progress
;
713 count
= ptimer_get_count(s
->ptimer_tick
);
715 /* timer is still counting, called not from event */
716 counted
= s
->count
- ptimer_get_count(s
->ptimer_tick
);
717 cur_progress
= s
->progress
+ counted
;
719 /* timer expired earlier */
720 cur_progress
= s
->progress
;
723 remain
= s
->distance
- cur_progress
;
726 /* INT is stopped. */
727 icnto
= s
->last_icnto
;
729 /* Both are counting */
730 icnto
= remain
/ s
->tcntb
;
737 * Start local tick cnt timer.
739 static void exynos4210_ltick_cnt_start(struct tick_timer
*s
)
743 exynos4210_ltick_recalc_count(s
);
744 ptimer_set_count(s
->ptimer_tick
, s
->count
);
745 ptimer_run(s
->ptimer_tick
, 1);
752 * Stop local tick cnt timer.
754 static void exynos4210_ltick_cnt_stop(struct tick_timer
*s
)
758 s
->last_tcnto
= exynos4210_ltick_cnt_get_cnto(s
);
761 exynos4210_ltick_int_stop(s
);
764 ptimer_stop(s
->ptimer_tick
);
771 * Get counter for CNT timer
773 static uint32_t exynos4210_ltick_cnt_get_cnto(struct tick_timer
*s
)
780 uint64_t cur_progress
;
782 count
= ptimer_get_count(s
->ptimer_tick
);
784 /* timer is still counting, called not from event */
785 counted
= s
->count
- ptimer_get_count(s
->ptimer_tick
);
786 cur_progress
= s
->progress
+ counted
;
788 /* timer expired earlier */
789 cur_progress
= s
->progress
;
792 remain
= s
->distance
- cur_progress
;
795 /* Both are stopped. */
796 tcnto
= s
->last_tcnto
;
797 } else if (!s
->int_run
) {
798 /* INT counter is stopped, progress is by CNT timer */
799 tcnto
= remain
% s
->tcntb
;
801 /* Both are counting */
802 icnto
= remain
/ s
->tcntb
;
804 tcnto
= remain
% (icnto
* s
->tcntb
);
806 tcnto
= remain
% s
->tcntb
;
814 * Set new values of counters for CNT and INT timers
816 static void exynos4210_ltick_set_cntb(struct tick_timer
*s
, uint32_t new_cnt
,
819 uint32_t cnt_stopped
= 0;
820 uint32_t int_stopped
= 0;
823 exynos4210_ltick_cnt_stop(s
);
828 exynos4210_ltick_int_stop(s
);
832 s
->tcntb
= new_cnt
+ 1;
833 s
->icntb
= new_int
+ 1;
836 exynos4210_ltick_cnt_start(s
);
839 exynos4210_ltick_int_start(s
);
845 * Calculate new counter value for tick timer
847 static void exynos4210_ltick_recalc_count(struct tick_timer
*s
)
851 if ((s
->cnt_run
&& s
->last_tcnto
) || (s
->int_run
&& s
->last_icnto
)) {
853 * one or both timers run and not counted to the end;
854 * distance is not passed, recalculate with last_tcnto * last_icnto
858 to_count
= (uint64_t)s
->last_tcnto
* s
->last_icnto
;
860 to_count
= s
->last_icnto
;
863 /* distance is passed, recalculate with tcnto * icnto */
865 s
->distance
= (uint64_t)s
->tcntb
* s
->icntb
;
867 s
->distance
= s
->tcntb
;
870 to_count
= s
->distance
;
874 if (to_count
> MCT_LT_COUNTER_STEP
) {
876 s
->count
= MCT_LT_COUNTER_STEP
;
883 * Initialize tick_timer
885 static void exynos4210_ltick_timer_init(struct tick_timer
*s
)
887 exynos4210_ltick_int_stop(s
);
888 exynos4210_ltick_cnt_stop(s
);
899 * Raises when abstract tick_timer expires.
901 static void exynos4210_ltick_timer_event(struct tick_timer
*s
)
903 s
->progress
+= s
->count
;
907 * Local timer tick counter handler.
908 * Don't use reloaded timers. If timer counter = zero
909 * then handler called but after handler finished no
910 * timer reload occurs.
912 static void exynos4210_ltick_event(void *opaque
)
914 Exynos4210MCTLT
* s
= (Exynos4210MCTLT
*)opaque
;
918 static uint64_t time1
[2] = {0};
919 static uint64_t time2
[2] = {0};
922 /* Call tick_timer event handler, it will update its tcntb and icntb. */
923 exynos4210_ltick_timer_event(&s
->tick_timer
);
925 /* get tick_timer cnt */
926 tcnto
= exynos4210_ltick_cnt_get_cnto(&s
->tick_timer
);
928 /* get tick_timer int */
929 icnto
= exynos4210_ltick_int_get_cnto(&s
->tick_timer
);
931 /* raise IRQ if needed */
932 if (!icnto
&& s
->reg
.tcon
& L_TCON_INT_START
) {
933 /* INT counter enabled and expired */
935 s
->reg
.int_cstat
|= L_INT_CSTAT_INTCNT
;
937 /* raise interrupt if enabled */
938 if (s
->reg
.int_enb
& L_INT_INTENB_ICNTEIE
) {
940 time2
[s
->id
] = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
941 DPRINTF("local timer[%d] IRQ: %llx\n", s
->id
,
942 time2
[s
->id
] - time1
[s
->id
]);
943 time1
[s
->id
] = time2
[s
->id
];
945 qemu_irq_raise(s
->irq
);
949 if (s
->reg
.tcon
& L_TCON_INTERVAL_MODE
) {
950 exynos4210_ltick_set_cntb(&s
->tick_timer
,
951 s
->reg
.cnt
[L_REG_CNT_TCNTB
],
952 s
->reg
.cnt
[L_REG_CNT_ICNTB
]);
957 exynos4210_ltick_set_cntb(&s
->tick_timer
,
958 s
->reg
.cnt
[L_REG_CNT_TCNTB
],
963 /* start tick_timer cnt */
964 exynos4210_ltick_cnt_start(&s
->tick_timer
);
966 /* start tick_timer int */
967 exynos4210_ltick_int_start(&s
->tick_timer
);
970 static void tx_ptimer_set_freq(ptimer_state
*s
, uint32_t freq
)
973 * callers of exynos4210_mct_update_freq() never do anything
974 * else that needs to be in the same ptimer transaction, so
975 * to avoid a lot of repetition we have a convenience function
976 * for begin/set_freq/commit.
978 ptimer_transaction_begin(s
);
979 ptimer_set_freq(s
, freq
);
980 ptimer_transaction_commit(s
);
983 /* update timer frequency */
984 static void exynos4210_mct_update_freq(Exynos4210MCTState
*s
)
986 uint32_t freq
= s
->freq
;
988 ((MCT_CFG_GET_PRESCALER(s
->reg_mct_cfg
) + 1) *
989 MCT_CFG_GET_DIVIDER(s
->reg_mct_cfg
));
991 if (freq
!= s
->freq
) {
992 DPRINTF("freq=%dHz\n", s
->freq
);
995 tx_ptimer_set_freq(s
->g_timer
.ptimer_frc
, s
->freq
);
998 ptimer_set_freq(s
->l_timer
[0].tick_timer
.ptimer_tick
, s
->freq
);
999 tx_ptimer_set_freq(s
->l_timer
[0].ptimer_frc
, s
->freq
);
1000 ptimer_set_freq(s
->l_timer
[1].tick_timer
.ptimer_tick
, s
->freq
);
1001 tx_ptimer_set_freq(s
->l_timer
[1].ptimer_frc
, s
->freq
);
1005 /* set defaul_timer values for all fields */
1006 static void exynos4210_mct_reset(DeviceState
*d
)
1008 Exynos4210MCTState
*s
= EXYNOS4210_MCT(d
);
1014 memset(&s
->g_timer
.reg
, 0, sizeof(s
->g_timer
.reg
));
1015 exynos4210_gfrc_tx_begin(&s
->g_timer
);
1016 exynos4210_gfrc_stop(&s
->g_timer
);
1017 exynos4210_gfrc_tx_commit(&s
->g_timer
);
1020 memset(s
->l_timer
[0].reg
.cnt
, 0, sizeof(s
->l_timer
[0].reg
.cnt
));
1021 memset(s
->l_timer
[1].reg
.cnt
, 0, sizeof(s
->l_timer
[1].reg
.cnt
));
1022 for (i
= 0; i
< 2; i
++) {
1023 s
->l_timer
[i
].reg
.int_cstat
= 0;
1024 s
->l_timer
[i
].reg
.int_enb
= 0;
1025 s
->l_timer
[i
].reg
.tcon
= 0;
1026 s
->l_timer
[i
].reg
.wstat
= 0;
1027 s
->l_timer
[i
].tick_timer
.count
= 0;
1028 s
->l_timer
[i
].tick_timer
.distance
= 0;
1029 s
->l_timer
[i
].tick_timer
.progress
= 0;
1030 exynos4210_lfrc_tx_begin(&s
->l_timer
[i
]);
1031 ptimer_stop(s
->l_timer
[i
].ptimer_frc
);
1032 exynos4210_lfrc_tx_commit(&s
->l_timer
[i
]);
1034 exynos4210_ltick_timer_init(&s
->l_timer
[i
].tick_timer
);
1037 exynos4210_mct_update_freq(s
);
1041 /* Multi Core Timer read */
1042 static uint64_t exynos4210_mct_read(void *opaque
, hwaddr offset
,
1045 Exynos4210MCTState
*s
= (Exynos4210MCTState
*)opaque
;
1055 value
= s
->reg_mct_cfg
;
1058 case G_CNT_L
: case G_CNT_U
:
1059 shift
= 8 * (offset
& 0x4);
1060 count
= exynos4210_gfrc_get_count(&s
->g_timer
);
1061 value
= UINT32_MAX
& (count
>> shift
);
1062 DPRINTF("read FRC=0x%llx\n", count
);
1066 value
= s
->g_timer
.reg
.cnt_wstat
;
1069 case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3):
1070 case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3):
1071 index
= GET_G_COMP_IDX(offset
);
1072 shift
= 8 * (offset
& 0x4);
1073 value
= UINT32_MAX
& (s
->g_timer
.reg
.comp
[index
] >> shift
);
1077 value
= s
->g_timer
.reg
.tcon
;
1081 value
= s
->g_timer
.reg
.int_cstat
;
1085 value
= s
->g_timer
.reg
.int_enb
;
1088 value
= s
->g_timer
.reg
.wstat
;
1091 case G_COMP0_ADD_INCR
: case G_COMP1_ADD_INCR
:
1092 case G_COMP2_ADD_INCR
: case G_COMP3_ADD_INCR
:
1093 value
= s
->g_timer
.reg
.comp_add_incr
[GET_G_COMP_ADD_INCR_IDX(offset
)];
1097 case L0_TCNTB
: case L0_ICNTB
: case L0_FRCNTB
:
1098 case L1_TCNTB
: case L1_ICNTB
: case L1_FRCNTB
:
1099 lt_i
= GET_L_TIMER_IDX(offset
);
1100 index
= GET_L_TIMER_CNT_REG_IDX(offset
, lt_i
);
1101 value
= s
->l_timer
[lt_i
].reg
.cnt
[index
];
1104 case L0_TCNTO
: case L1_TCNTO
:
1105 lt_i
= GET_L_TIMER_IDX(offset
);
1107 value
= exynos4210_ltick_cnt_get_cnto(&s
->l_timer
[lt_i
].tick_timer
);
1108 DPRINTF("local timer[%d] read TCNTO %x\n", lt_i
, value
);
1111 case L0_ICNTO
: case L1_ICNTO
:
1112 lt_i
= GET_L_TIMER_IDX(offset
);
1114 value
= exynos4210_ltick_int_get_cnto(&s
->l_timer
[lt_i
].tick_timer
);
1115 DPRINTF("local timer[%d] read ICNTO %x\n", lt_i
, value
);
1118 case L0_FRCNTO
: case L1_FRCNTO
:
1119 lt_i
= GET_L_TIMER_IDX(offset
);
1121 value
= exynos4210_lfrc_get_count(&s
->l_timer
[lt_i
]);
1124 case L0_TCON
: case L1_TCON
:
1125 lt_i
= ((offset
& 0xF00) - L0_TCNTB
) / 0x100;
1126 value
= s
->l_timer
[lt_i
].reg
.tcon
;
1129 case L0_INT_CSTAT
: case L1_INT_CSTAT
:
1130 lt_i
= ((offset
& 0xF00) - L0_TCNTB
) / 0x100;
1131 value
= s
->l_timer
[lt_i
].reg
.int_cstat
;
1134 case L0_INT_ENB
: case L1_INT_ENB
:
1135 lt_i
= ((offset
& 0xF00) - L0_TCNTB
) / 0x100;
1136 value
= s
->l_timer
[lt_i
].reg
.int_enb
;
1139 case L0_WSTAT
: case L1_WSTAT
:
1140 lt_i
= ((offset
& 0xF00) - L0_TCNTB
) / 0x100;
1141 value
= s
->l_timer
[lt_i
].reg
.wstat
;
1145 hw_error("exynos4210.mct: bad read offset "
1146 TARGET_FMT_plx
"\n", offset
);
1153 static void exynos4210_mct_write(void *opaque
, hwaddr offset
,
1154 uint64_t value
, unsigned size
)
1156 Exynos4210MCTState
*s
= (Exynos4210MCTState
*)opaque
;
1157 int index
; /* index in buffer which represents register set */
1164 static uint32_t icntb_max
[2] = {0};
1165 static uint32_t icntb_min
[2] = {UINT32_MAX
, UINT32_MAX
};
1166 static uint32_t tcntb_max
[2] = {0};
1167 static uint32_t tcntb_min
[2] = {UINT32_MAX
, UINT32_MAX
};
1170 new_frc
= s
->g_timer
.reg
.cnt
;
1175 s
->reg_mct_cfg
= value
;
1176 exynos4210_mct_update_freq(s
);
1181 if (offset
== G_CNT_L
) {
1183 DPRINTF("global timer write to reg.cntl %llx\n", value
);
1185 new_frc
= (s
->g_timer
.reg
.cnt
& (uint64_t)UINT32_MAX
<< 32) + value
;
1186 s
->g_timer
.reg
.cnt_wstat
|= G_CNT_WSTAT_L
;
1188 if (offset
== G_CNT_U
) {
1190 DPRINTF("global timer write to reg.cntu %llx\n", value
);
1192 new_frc
= (s
->g_timer
.reg
.cnt
& UINT32_MAX
) +
1193 ((uint64_t)value
<< 32);
1194 s
->g_timer
.reg
.cnt_wstat
|= G_CNT_WSTAT_U
;
1197 s
->g_timer
.reg
.cnt
= new_frc
;
1198 exynos4210_gfrc_tx_begin(&s
->g_timer
);
1199 exynos4210_gfrc_restart(s
);
1200 exynos4210_gfrc_tx_commit(&s
->g_timer
);
1204 s
->g_timer
.reg
.cnt_wstat
&= ~(value
);
1207 case G_COMP_L(0): case G_COMP_L(1): case G_COMP_L(2): case G_COMP_L(3):
1208 case G_COMP_U(0): case G_COMP_U(1): case G_COMP_U(2): case G_COMP_U(3):
1209 index
= GET_G_COMP_IDX(offset
);
1210 shift
= 8 * (offset
& 0x4);
1211 s
->g_timer
.reg
.comp
[index
] =
1212 (s
->g_timer
.reg
.comp
[index
] &
1213 (((uint64_t)UINT32_MAX
<< 32) >> shift
)) +
1216 DPRINTF("comparator %d write 0x%llx val << %d\n", index
, value
, shift
);
1219 s
->g_timer
.reg
.wstat
|= G_WSTAT_COMP_U(index
);
1221 s
->g_timer
.reg
.wstat
|= G_WSTAT_COMP_L(index
);
1224 exynos4210_gfrc_tx_begin(&s
->g_timer
);
1225 exynos4210_gfrc_restart(s
);
1226 exynos4210_gfrc_tx_commit(&s
->g_timer
);
1230 old_val
= s
->g_timer
.reg
.tcon
;
1231 s
->g_timer
.reg
.tcon
= value
;
1232 s
->g_timer
.reg
.wstat
|= G_WSTAT_TCON_WRITE
;
1234 DPRINTF("global timer write to reg.g_tcon %llx\n", value
);
1236 exynos4210_gfrc_tx_begin(&s
->g_timer
);
1238 /* Start FRC if transition from disabled to enabled */
1239 if ((value
& G_TCON_TIMER_ENABLE
) > (old_val
&
1240 G_TCON_TIMER_ENABLE
)) {
1241 exynos4210_gfrc_start(&s
->g_timer
);
1243 if ((value
& G_TCON_TIMER_ENABLE
) < (old_val
&
1244 G_TCON_TIMER_ENABLE
)) {
1245 exynos4210_gfrc_stop(&s
->g_timer
);
1248 /* Start CMP if transition from disabled to enabled */
1249 for (i
= 0; i
< MCT_GT_CMP_NUM
; i
++) {
1250 if ((value
& G_TCON_COMP_ENABLE(i
)) != (old_val
&
1251 G_TCON_COMP_ENABLE(i
))) {
1252 exynos4210_gfrc_restart(s
);
1256 exynos4210_gfrc_tx_commit(&s
->g_timer
);
1260 s
->g_timer
.reg
.int_cstat
&= ~(value
);
1261 for (i
= 0; i
< MCT_GT_CMP_NUM
; i
++) {
1262 if (value
& G_INT_CSTAT_COMP(i
)) {
1263 exynos4210_gcomp_lower_irq(&s
->g_timer
, i
);
1269 /* Raise IRQ if transition from disabled to enabled and CSTAT pending */
1270 for (i
= 0; i
< MCT_GT_CMP_NUM
; i
++) {
1271 if ((value
& G_INT_ENABLE(i
)) > (s
->g_timer
.reg
.tcon
&
1273 if (s
->g_timer
.reg
.int_cstat
& G_INT_CSTAT_COMP(i
)) {
1274 exynos4210_gcomp_raise_irq(&s
->g_timer
, i
);
1278 if ((value
& G_INT_ENABLE(i
)) < (s
->g_timer
.reg
.tcon
&
1280 exynos4210_gcomp_lower_irq(&s
->g_timer
, i
);
1284 DPRINTF("global timer INT enable %llx\n", value
);
1285 s
->g_timer
.reg
.int_enb
= value
;
1289 s
->g_timer
.reg
.wstat
&= ~(value
);
1292 case G_COMP0_ADD_INCR
: case G_COMP1_ADD_INCR
:
1293 case G_COMP2_ADD_INCR
: case G_COMP3_ADD_INCR
:
1294 index
= GET_G_COMP_ADD_INCR_IDX(offset
);
1295 s
->g_timer
.reg
.comp_add_incr
[index
] = value
;
1296 s
->g_timer
.reg
.wstat
|= G_WSTAT_COMP_ADDINCR(index
);
1300 case L0_TCON
: case L1_TCON
:
1301 lt_i
= GET_L_TIMER_IDX(offset
);
1302 old_val
= s
->l_timer
[lt_i
].reg
.tcon
;
1304 s
->l_timer
[lt_i
].reg
.wstat
|= L_WSTAT_TCON_WRITE
;
1305 s
->l_timer
[lt_i
].reg
.tcon
= value
;
1307 /* Stop local CNT */
1308 if ((value
& L_TCON_TICK_START
) <
1309 (old_val
& L_TCON_TICK_START
)) {
1310 DPRINTF("local timer[%d] stop cnt\n", lt_i
);
1311 exynos4210_ltick_cnt_stop(&s
->l_timer
[lt_i
].tick_timer
);
1314 /* Stop local INT */
1315 if ((value
& L_TCON_INT_START
) <
1316 (old_val
& L_TCON_INT_START
)) {
1317 DPRINTF("local timer[%d] stop int\n", lt_i
);
1318 exynos4210_ltick_int_stop(&s
->l_timer
[lt_i
].tick_timer
);
1321 /* Start local CNT */
1322 if ((value
& L_TCON_TICK_START
) >
1323 (old_val
& L_TCON_TICK_START
)) {
1324 DPRINTF("local timer[%d] start cnt\n", lt_i
);
1325 exynos4210_ltick_cnt_start(&s
->l_timer
[lt_i
].tick_timer
);
1328 /* Start local INT */
1329 if ((value
& L_TCON_INT_START
) >
1330 (old_val
& L_TCON_INT_START
)) {
1331 DPRINTF("local timer[%d] start int\n", lt_i
);
1332 exynos4210_ltick_int_start(&s
->l_timer
[lt_i
].tick_timer
);
1335 /* Start or Stop local FRC if TCON changed */
1336 exynos4210_lfrc_tx_begin(&s
->l_timer
[lt_i
]);
1337 if ((value
& L_TCON_FRC_START
) >
1338 (s
->l_timer
[lt_i
].reg
.tcon
& L_TCON_FRC_START
)) {
1339 DPRINTF("local timer[%d] start frc\n", lt_i
);
1340 exynos4210_lfrc_start(&s
->l_timer
[lt_i
]);
1342 if ((value
& L_TCON_FRC_START
) <
1343 (s
->l_timer
[lt_i
].reg
.tcon
& L_TCON_FRC_START
)) {
1344 DPRINTF("local timer[%d] stop frc\n", lt_i
);
1345 exynos4210_lfrc_stop(&s
->l_timer
[lt_i
]);
1347 exynos4210_lfrc_tx_commit(&s
->l_timer
[lt_i
]);
1350 case L0_TCNTB
: case L1_TCNTB
:
1351 lt_i
= GET_L_TIMER_IDX(offset
);
1352 index
= GET_L_TIMER_CNT_REG_IDX(offset
, lt_i
);
1355 * TCNTB is updated to internal register only after CNT expired.
1356 * Due to this we should reload timer to nearest moment when CNT is
1357 * expired and then in event handler update tcntb to new TCNTB value.
1359 exynos4210_ltick_set_cntb(&s
->l_timer
[lt_i
].tick_timer
, value
,
1360 s
->l_timer
[lt_i
].tick_timer
.icntb
);
1362 s
->l_timer
[lt_i
].reg
.wstat
|= L_WSTAT_TCNTB_WRITE
;
1363 s
->l_timer
[lt_i
].reg
.cnt
[L_REG_CNT_TCNTB
] = value
;
1366 if (tcntb_min
[lt_i
] > value
) {
1367 tcntb_min
[lt_i
] = value
;
1369 if (tcntb_max
[lt_i
] < value
) {
1370 tcntb_max
[lt_i
] = value
;
1372 DPRINTF("local timer[%d] TCNTB write %llx; max=%x, min=%x\n",
1373 lt_i
, value
, tcntb_max
[lt_i
], tcntb_min
[lt_i
]);
1377 case L0_ICNTB
: case L1_ICNTB
:
1378 lt_i
= GET_L_TIMER_IDX(offset
);
1379 index
= GET_L_TIMER_CNT_REG_IDX(offset
, lt_i
);
1381 s
->l_timer
[lt_i
].reg
.wstat
|= L_WSTAT_ICNTB_WRITE
;
1382 s
->l_timer
[lt_i
].reg
.cnt
[L_REG_CNT_ICNTB
] = value
&
1383 ~L_ICNTB_MANUAL_UPDATE
;
1386 * We need to avoid too small values for TCNTB*ICNTB. If not, IRQ event
1387 * could raise too fast disallowing QEMU to execute target code.
1389 if (s
->l_timer
[lt_i
].reg
.cnt
[L_REG_CNT_ICNTB
] *
1390 s
->l_timer
[lt_i
].reg
.cnt
[L_REG_CNT_TCNTB
] < MCT_LT_CNT_LOW_LIMIT
) {
1391 if (!s
->l_timer
[lt_i
].reg
.cnt
[L_REG_CNT_TCNTB
]) {
1392 s
->l_timer
[lt_i
].reg
.cnt
[L_REG_CNT_ICNTB
] =
1393 MCT_LT_CNT_LOW_LIMIT
;
1395 s
->l_timer
[lt_i
].reg
.cnt
[L_REG_CNT_ICNTB
] =
1396 MCT_LT_CNT_LOW_LIMIT
/
1397 s
->l_timer
[lt_i
].reg
.cnt
[L_REG_CNT_TCNTB
];
1401 if (value
& L_ICNTB_MANUAL_UPDATE
) {
1402 exynos4210_ltick_set_cntb(&s
->l_timer
[lt_i
].tick_timer
,
1403 s
->l_timer
[lt_i
].tick_timer
.tcntb
,
1404 s
->l_timer
[lt_i
].reg
.cnt
[L_REG_CNT_ICNTB
]);
1408 if (icntb_min
[lt_i
] > value
) {
1409 icntb_min
[lt_i
] = value
;
1411 if (icntb_max
[lt_i
] < value
) {
1412 icntb_max
[lt_i
] = value
;
1414 DPRINTF("local timer[%d] ICNTB write %llx; max=%x, min=%x\n\n",
1415 lt_i
, value
, icntb_max
[lt_i
], icntb_min
[lt_i
]);
1419 case L0_FRCNTB
: case L1_FRCNTB
:
1420 lt_i
= GET_L_TIMER_IDX(offset
);
1421 index
= GET_L_TIMER_CNT_REG_IDX(offset
, lt_i
);
1423 DPRINTF("local timer[%d] FRCNTB write %llx\n", lt_i
, value
);
1425 s
->l_timer
[lt_i
].reg
.wstat
|= L_WSTAT_FRCCNTB_WRITE
;
1426 s
->l_timer
[lt_i
].reg
.cnt
[L_REG_CNT_FRCCNTB
] = value
;
1430 case L0_TCNTO
: case L1_TCNTO
:
1431 case L0_ICNTO
: case L1_ICNTO
:
1432 case L0_FRCNTO
: case L1_FRCNTO
:
1433 qemu_log_mask(LOG_GUEST_ERROR
,
1434 "exynos4210.mct: write to RO register " TARGET_FMT_plx
,
1438 case L0_INT_CSTAT
: case L1_INT_CSTAT
:
1439 lt_i
= GET_L_TIMER_IDX(offset
);
1441 DPRINTF("local timer[%d] CSTAT write %llx\n", lt_i
, value
);
1443 s
->l_timer
[lt_i
].reg
.int_cstat
&= ~value
;
1444 if (!s
->l_timer
[lt_i
].reg
.int_cstat
) {
1445 qemu_irq_lower(s
->l_timer
[lt_i
].irq
);
1449 case L0_INT_ENB
: case L1_INT_ENB
:
1450 lt_i
= GET_L_TIMER_IDX(offset
);
1451 old_val
= s
->l_timer
[lt_i
].reg
.int_enb
;
1453 /* Raise Local timer IRQ if cstat is pending */
1454 if ((value
& L_INT_INTENB_ICNTEIE
) > (old_val
& L_INT_INTENB_ICNTEIE
)) {
1455 if (s
->l_timer
[lt_i
].reg
.int_cstat
& L_INT_CSTAT_INTCNT
) {
1456 qemu_irq_raise(s
->l_timer
[lt_i
].irq
);
1460 s
->l_timer
[lt_i
].reg
.int_enb
= value
;
1464 case L0_WSTAT
: case L1_WSTAT
:
1465 lt_i
= GET_L_TIMER_IDX(offset
);
1467 s
->l_timer
[lt_i
].reg
.wstat
&= ~value
;
1471 hw_error("exynos4210.mct: bad write offset "
1472 TARGET_FMT_plx
"\n", offset
);
1477 static const MemoryRegionOps exynos4210_mct_ops
= {
1478 .read
= exynos4210_mct_read
,
1479 .write
= exynos4210_mct_write
,
1480 .endianness
= DEVICE_NATIVE_ENDIAN
,
1484 static void exynos4210_mct_init(Object
*obj
)
1487 Exynos4210MCTState
*s
= EXYNOS4210_MCT(obj
);
1488 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
1492 s
->g_timer
.ptimer_frc
= ptimer_init(exynos4210_gfrc_event
, s
,
1493 PTIMER_POLICY_DEFAULT
);
1494 memset(&s
->g_timer
.reg
, 0, sizeof(struct gregs
));
1497 for (i
= 0; i
< 2; i
++) {
1498 bh
[0] = qemu_bh_new(exynos4210_ltick_event
, &s
->l_timer
[i
]);
1499 s
->l_timer
[i
].tick_timer
.ptimer_tick
=
1500 ptimer_init_with_bh(bh
[0], PTIMER_POLICY_DEFAULT
);
1501 s
->l_timer
[i
].ptimer_frc
=
1502 ptimer_init(exynos4210_lfrc_event
, &s
->l_timer
[i
],
1503 PTIMER_POLICY_DEFAULT
);
1504 s
->l_timer
[i
].id
= i
;
1508 for (i
= 0; i
< MCT_GT_CMP_NUM
; i
++) {
1509 sysbus_init_irq(dev
, &s
->g_timer
.irq
[i
]);
1511 for (i
= 0; i
< 2; i
++) {
1512 sysbus_init_irq(dev
, &s
->l_timer
[i
].irq
);
1515 memory_region_init_io(&s
->iomem
, obj
, &exynos4210_mct_ops
, s
,
1516 "exynos4210-mct", MCT_SFR_SIZE
);
1517 sysbus_init_mmio(dev
, &s
->iomem
);
1520 static void exynos4210_mct_class_init(ObjectClass
*klass
, void *data
)
1522 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1524 dc
->reset
= exynos4210_mct_reset
;
1525 dc
->vmsd
= &vmstate_exynos4210_mct_state
;
1528 static const TypeInfo exynos4210_mct_info
= {
1529 .name
= TYPE_EXYNOS4210_MCT
,
1530 .parent
= TYPE_SYS_BUS_DEVICE
,
1531 .instance_size
= sizeof(Exynos4210MCTState
),
1532 .instance_init
= exynos4210_mct_init
,
1533 .class_init
= exynos4210_mct_class_init
,
1536 static void exynos4210_mct_register_types(void)
1538 type_register_static(&exynos4210_mct_info
);
1541 type_init(exynos4210_mct_register_types
)