4 * Copyright (c) 2008 OK Labs
5 * Copyright (c) 2011 NICTA Pty Ltd
6 * Originally written by Hans Jiang
7 * Updated by Peter Chubb
9 * This code is licensed under GPL version 2 or later. See
10 * the COPYING file in the top-level directory.
15 #include "qemu/bitops.h"
16 #include "qemu/timer.h"
17 #include "hw/ptimer.h"
18 #include "hw/sysbus.h"
19 #include "hw/arm/imx.h"
21 //#define DEBUG_TIMER 1
23 # define DPRINTF(fmt, args...) \
24 do { printf("imx_timer: " fmt , ##args); } while (0)
26 # define DPRINTF(fmt, args...) do {} while (0)
30 * Define to 1 for messages about attempts to
31 * access unimplemented registers or similar.
33 #define DEBUG_IMPLEMENTATION 1
34 #if DEBUG_IMPLEMENTATION
35 # define IPRINTF(fmt, args...) \
36 do { fprintf(stderr, "imx_timer: " fmt, ##args); } while (0)
38 # define IPRINTF(fmt, args...) do {} while (0)
42 * GPT : General purpose timer
44 * This timer counts up continuously while it is enabled, resetting itself
45 * to 0 when it reaches TIMER_MAX (in freerun mode) or when it
46 * reaches the value of ocr1 (in periodic mode). WE simulate this using a
47 * QEMU ptimer counting down from ocr1 and reloading from ocr1 in
48 * periodic mode, or counting from ocr1 to zero, then TIMER_MAX - ocr1.
49 * waiting_rov is set when counting from TIMER_MAX.
51 * In the real hardware, there are three comparison registers that can
52 * trigger interrupts, and compare channel 1 can be used to
53 * force-reset the timer. However, this is a `bare-bones'
54 * implementation: only what Linux 3.x uses has been implemented
55 * (free-running timer from 0 to OCR1 or TIMER_MAX) .
58 #define TIMER_MAX 0XFFFFFFFFUL
60 /* Control register. Not all of these bits have any effect (yet) */
61 #define GPT_CR_EN (1 << 0) /* GPT Enable */
62 #define GPT_CR_ENMOD (1 << 1) /* GPT Enable Mode */
63 #define GPT_CR_DBGEN (1 << 2) /* GPT Debug mode enable */
64 #define GPT_CR_WAITEN (1 << 3) /* GPT Wait Mode Enable */
65 #define GPT_CR_DOZEN (1 << 4) /* GPT Doze mode enable */
66 #define GPT_CR_STOPEN (1 << 5) /* GPT Stop Mode Enable */
67 #define GPT_CR_CLKSRC_SHIFT (6)
68 #define GPT_CR_CLKSRC_MASK (0x7)
70 #define GPT_CR_FRR (1 << 9) /* Freerun or Restart */
71 #define GPT_CR_SWR (1 << 15) /* Software Reset */
72 #define GPT_CR_IM1 (3 << 16) /* Input capture channel 1 mode (2 bits) */
73 #define GPT_CR_IM2 (3 << 18) /* Input capture channel 2 mode (2 bits) */
74 #define GPT_CR_OM1 (7 << 20) /* Output Compare Channel 1 Mode (3 bits) */
75 #define GPT_CR_OM2 (7 << 23) /* Output Compare Channel 2 Mode (3 bits) */
76 #define GPT_CR_OM3 (7 << 26) /* Output Compare Channel 3 Mode (3 bits) */
77 #define GPT_CR_FO1 (1 << 29) /* Force Output Compare Channel 1 */
78 #define GPT_CR_FO2 (1 << 30) /* Force Output Compare Channel 2 */
79 #define GPT_CR_FO3 (1 << 31) /* Force Output Compare Channel 3 */
81 #define GPT_SR_OF1 (1 << 0)
82 #define GPT_SR_ROV (1 << 5)
84 #define GPT_IR_OF1IE (1 << 0)
85 #define GPT_IR_ROVIE (1 << 5)
104 uint32_t waiting_rov
;
108 static const VMStateDescription vmstate_imx_timerg
= {
109 .name
= "imx-timerg",
111 .minimum_version_id
= 2,
112 .minimum_version_id_old
= 2,
113 .fields
= (VMStateField
[]) {
114 VMSTATE_UINT32(cr
, IMXTimerGState
),
115 VMSTATE_UINT32(pr
, IMXTimerGState
),
116 VMSTATE_UINT32(sr
, IMXTimerGState
),
117 VMSTATE_UINT32(ir
, IMXTimerGState
),
118 VMSTATE_UINT32(ocr1
, IMXTimerGState
),
119 VMSTATE_UINT32(ocr2
, IMXTimerGState
),
120 VMSTATE_UINT32(ocr3
, IMXTimerGState
),
121 VMSTATE_UINT32(icr1
, IMXTimerGState
),
122 VMSTATE_UINT32(icr2
, IMXTimerGState
),
123 VMSTATE_UINT32(cnt
, IMXTimerGState
),
124 VMSTATE_UINT32(waiting_rov
, IMXTimerGState
),
125 VMSTATE_PTIMER(timer
, IMXTimerGState
),
126 VMSTATE_END_OF_LIST()
130 static const IMXClk imx_timerg_clocks
[] = {
131 NOCLK
, /* 000 No clock source */
132 IPG
, /* 001 ipg_clk, 532MHz*/
133 IPG
, /* 010 ipg_clk_highfreq */
134 NOCLK
, /* 011 not defined */
135 CLK_32k
, /* 100 ipg_clk_32k */
136 NOCLK
, /* 101 not defined */
137 NOCLK
, /* 110 not defined */
138 NOCLK
, /* 111 not defined */
142 static void imx_timerg_set_freq(IMXTimerGState
*s
)
147 clksrc
= (s
->cr
>> GPT_CR_CLKSRC_SHIFT
) & GPT_CR_CLKSRC_MASK
;
148 freq
= imx_clock_frequency(s
->ccm
, imx_timerg_clocks
[clksrc
]) / (1 + s
->pr
);
150 DPRINTF("Setting gtimer clksrc %d to frequency %d\n", clksrc
, freq
);
153 ptimer_set_freq(s
->timer
, freq
);
157 static void imx_timerg_update(IMXTimerGState
*s
)
159 uint32_t flags
= s
->sr
& s
->ir
& (GPT_SR_OF1
| GPT_SR_ROV
);
161 DPRINTF("g-timer SR: %s %s IR=%s %s, %s\n",
162 s
->sr
& GPT_SR_OF1
? "OF1" : "",
163 s
->sr
& GPT_SR_ROV
? "ROV" : "",
164 s
->ir
& GPT_SR_OF1
? "OF1" : "",
165 s
->ir
& GPT_SR_ROV
? "ROV" : "",
166 s
->cr
& GPT_CR_EN
? "CR_EN" : "Not Enabled");
168 qemu_set_irq(s
->irq
, (s
->cr
& GPT_CR_EN
) && flags
);
171 static uint32_t imx_timerg_update_counts(IMXTimerGState
*s
)
173 uint64_t target
= s
->waiting_rov
? TIMER_MAX
: s
->ocr1
;
174 uint64_t cnt
= ptimer_get_count(s
->timer
);
175 s
->cnt
= target
- cnt
;
179 static void imx_timerg_reload(IMXTimerGState
*s
, uint32_t timeout
)
183 if (!(s
->cr
& GPT_CR_FRR
)) {
184 IPRINTF("IMX_timerg_reload --- called in reset-mode\n");
189 * For small timeouts, qemu sometimes runs too slow.
190 * Better deliver a late interrupt than none.
192 * In Reset mode (FRR bit clear)
193 * the ptimer reloads itself from OCR1;
194 * in free-running mode we need to fake
195 * running from 0 to ocr1 to TIMER_MAX
197 if (timeout
> s
->cnt
) {
198 diff_cnt
= timeout
- s
->cnt
;
202 ptimer_set_count(s
->timer
, diff_cnt
);
205 static uint64_t imx_timerg_read(void *opaque
, hwaddr offset
,
208 IMXTimerGState
*s
= (IMXTimerGState
*)opaque
;
210 DPRINTF("g-read(offset=%x)", (unsigned int)(offset
>> 2));
211 switch (offset
>> 2) {
212 case 0: /* Control Register */
213 DPRINTF(" cr = %x\n", s
->cr
);
216 case 1: /* prescaler */
217 DPRINTF(" pr = %x\n", s
->pr
);
220 case 2: /* Status Register */
221 DPRINTF(" sr = %x\n", s
->sr
);
224 case 3: /* Interrupt Register */
225 DPRINTF(" ir = %x\n", s
->ir
);
228 case 4: /* Output Compare Register 1 */
229 DPRINTF(" ocr1 = %x\n", s
->ocr1
);
232 case 5: /* Output Compare Register 2 */
233 DPRINTF(" ocr2 = %x\n", s
->ocr2
);
236 case 6: /* Output Compare Register 3 */
237 DPRINTF(" ocr3 = %x\n", s
->ocr3
);
240 case 7: /* input Capture Register 1 */
241 DPRINTF(" icr1 = %x\n", s
->icr1
);
244 case 8: /* input Capture Register 2 */
245 DPRINTF(" icr2 = %x\n", s
->icr2
);
249 imx_timerg_update_counts(s
);
250 DPRINTF(" cnt = %x\n", s
->cnt
);
254 IPRINTF("imx_timerg_read: Bad offset %x\n",
260 static void imx_timerg_reset(DeviceState
*dev
)
262 IMXTimerGState
*s
= container_of(dev
, IMXTimerGState
, busdev
.qdev
);
265 * Soft reset doesn't touch some bits; hard reset clears them
267 s
->cr
&= ~(GPT_CR_EN
|GPT_CR_ENMOD
|GPT_CR_STOPEN
|GPT_CR_DOZEN
|
268 GPT_CR_WAITEN
|GPT_CR_DBGEN
);
278 ptimer_stop(s
->timer
);
279 ptimer_set_limit(s
->timer
, TIMER_MAX
, 1);
280 ptimer_set_count(s
->timer
, TIMER_MAX
);
281 imx_timerg_set_freq(s
);
284 static void imx_timerg_write(void *opaque
, hwaddr offset
,
285 uint64_t value
, unsigned size
)
287 IMXTimerGState
*s
= (IMXTimerGState
*)opaque
;
288 DPRINTF("g-write(offset=%x, value = 0x%x)\n", (unsigned int)offset
>> 2,
289 (unsigned int)value
);
291 switch (offset
>> 2) {
293 uint32_t oldcr
= s
->cr
;
295 if (value
& GPT_CR_SWR
) { /* force reset */
296 value
&= ~GPT_CR_SWR
;
297 imx_timerg_reset(&s
->busdev
.qdev
);
298 imx_timerg_update(s
);
301 s
->cr
= value
& ~0x7c00;
302 imx_timerg_set_freq(s
);
303 if ((oldcr
^ value
) & GPT_CR_EN
) {
304 if (value
& GPT_CR_EN
) {
305 if (value
& GPT_CR_ENMOD
) {
306 ptimer_set_count(s
->timer
, s
->ocr1
);
310 (value
& GPT_CR_FRR
) && (s
->ocr1
!= TIMER_MAX
));
312 ptimer_stop(s
->timer
);
318 case 1: /* Prescaler */
319 s
->pr
= value
& 0xfff;
320 imx_timerg_set_freq(s
);
325 * No point in implementing the status register bits to do with
326 * external interrupt sources.
328 value
&= GPT_SR_OF1
| GPT_SR_ROV
;
330 imx_timerg_update(s
);
333 case 3: /* IR -- interrupt register */
334 s
->ir
= value
& 0x3f;
335 imx_timerg_update(s
);
338 case 4: /* OCR1 -- output compare register */
339 /* In non-freerun mode, reset count when this register is written */
340 if (!(s
->cr
& GPT_CR_FRR
)) {
342 ptimer_set_limit(s
->timer
, value
, 1);
344 imx_timerg_update_counts(s
);
345 if (value
> s
->cnt
) {
347 imx_timerg_reload(s
, value
);
350 imx_timerg_reload(s
, TIMER_MAX
- s
->cnt
);
356 case 5: /* OCR2 -- output compare register */
357 case 6: /* OCR3 -- output compare register */
359 IPRINTF("imx_timerg_write: Bad offset %x\n",
364 static void imx_timerg_timeout(void *opaque
)
366 IMXTimerGState
*s
= (IMXTimerGState
*)opaque
;
368 DPRINTF("imx_timerg_timeout, waiting rov=%d\n", s
->waiting_rov
);
369 if (s
->cr
& GPT_CR_FRR
) {
371 * Free running timer from 0 -> TIMERMAX
372 * Generates interrupt at TIMER_MAX and at cnt==ocr1
373 * If ocr1 == TIMER_MAX, then no need to reload timer.
375 if (s
->ocr1
== TIMER_MAX
) {
376 DPRINTF("s->ocr1 == TIMER_MAX, FRR\n");
377 s
->sr
|= GPT_SR_OF1
| GPT_SR_ROV
;
378 imx_timerg_update(s
);
382 if (s
->waiting_rov
) {
384 * We were waiting for cnt==TIMER_MAX
389 imx_timerg_reload(s
, s
->ocr1
);
391 /* Must have got a cnt==ocr1 timeout. */
395 imx_timerg_reload(s
, TIMER_MAX
);
397 imx_timerg_update(s
);
402 imx_timerg_update(s
);
405 static const MemoryRegionOps imx_timerg_ops
= {
406 .read
= imx_timerg_read
,
407 .write
= imx_timerg_write
,
408 .endianness
= DEVICE_NATIVE_ENDIAN
,
412 static int imx_timerg_init(SysBusDevice
*dev
)
414 IMXTimerGState
*s
= FROM_SYSBUS(IMXTimerGState
, dev
);
417 sysbus_init_irq(dev
, &s
->irq
);
418 memory_region_init_io(&s
->iomem
, &imx_timerg_ops
,
421 sysbus_init_mmio(dev
, &s
->iomem
);
423 bh
= qemu_bh_new(imx_timerg_timeout
, s
);
424 s
->timer
= ptimer_init(bh
);
426 /* Hard reset resets extra bits in CR */
431 void imx_timerg_create(const hwaddr addr
,
438 dev
= sysbus_create_simple("imx_timerg", addr
, irq
);
439 pp
= container_of(dev
, IMXTimerGState
, busdev
.qdev
);
443 static void imx_timerg_class_init(ObjectClass
*klass
, void *data
)
445 DeviceClass
*dc
= DEVICE_CLASS(klass
);
446 SysBusDeviceClass
*k
= SYS_BUS_DEVICE_CLASS(klass
);
447 k
->init
= imx_timerg_init
;
448 dc
->vmsd
= &vmstate_imx_timerg
;
449 dc
->reset
= imx_timerg_reset
;
450 dc
->desc
= "i.MX general timer";
453 static const TypeInfo imx_timerg_info
= {
454 .name
= "imx_timerg",
455 .parent
= TYPE_SYS_BUS_DEVICE
,
456 .instance_size
= sizeof(IMXTimerGState
),
457 .class_init
= imx_timerg_class_init
,
460 static void imx_timer_register_types(void)
462 type_register_static(&imx_timerg_info
);
465 type_init(imx_timer_register_types
)