hw/timer/m48t59.c

   1 /*
   2  * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
   3  *
   4  * Copyright (c) 2003-2005, 2007, 2017 Jocelyn Mayer
   5  * Copyright (c) 2013 Hervé Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "hw/hw.h"
  28 #include "hw/timer/m48t59.h"
  29 #include "qemu/timer.h"
  30 #include "sysemu/sysemu.h"
  31 #include "hw/sysbus.h"
  32 #include "exec/address-spaces.h"
  33 #include "qemu/bcd.h"
  34 #include "qemu/module.h"
  35
  36 #include "m48t59-internal.h"
  37
  38 #define TYPE_M48TXX_SYS_BUS "sysbus-m48txx"
  39 #define M48TXX_SYS_BUS_GET_CLASS(obj) \
  40     OBJECT_GET_CLASS(M48txxSysBusDeviceClass, (obj), TYPE_M48TXX_SYS_BUS)
  41 #define M48TXX_SYS_BUS_CLASS(klass) \
  42     OBJECT_CLASS_CHECK(M48txxSysBusDeviceClass, (klass), TYPE_M48TXX_SYS_BUS)
  43 #define M48TXX_SYS_BUS(obj) \
  44     OBJECT_CHECK(M48txxSysBusState, (obj), TYPE_M48TXX_SYS_BUS)
  45
  46 /*
  47  * Chipset docs:
  48  * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
  49  * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
  50  * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
  51  */
  52
  53 typedef struct M48txxSysBusState {
  54     SysBusDevice parent_obj;
  55     M48t59State state;
  56     MemoryRegion io;
  57 } M48txxSysBusState;
  58
  59 typedef struct M48txxSysBusDeviceClass {
  60     SysBusDeviceClass parent_class;
  61     M48txxInfo info;
  62 } M48txxSysBusDeviceClass;
  63
  64 static M48txxInfo m48txx_sysbus_info[] = {
  65     {
  66         .bus_name = "sysbus-m48t02",
  67         .model = 2,
  68         .size = 0x800,
  69     },{
  70         .bus_name = "sysbus-m48t08",
  71         .model = 8,
  72         .size = 0x2000,
  73     },{
  74         .bus_name = "sysbus-m48t59",
  75         .model = 59,
  76         .size = 0x2000,
  77     }
  78 };
  79
  80
  81 /* Fake timer functions */
  82
  83 /* Alarm management */
  84 static void alarm_cb (void *opaque)
  85 {
  86     struct tm tm;
  87     uint64_t next_time;
  88     M48t59State *NVRAM = opaque;
  89
  90     qemu_set_irq(NVRAM->IRQ, 1);
  91     if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
  92         (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
  93         (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
  94         (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
  95         /* Repeat once a month */
  96         qemu_get_timedate(&tm, NVRAM->time_offset);
  97         tm.tm_mon++;
  98         if (tm.tm_mon == 13) {
  99             tm.tm_mon = 1;
 100             tm.tm_year++;
 101         }
 102         next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset;
 103     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 104                (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
 105                (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
 106                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 107         /* Repeat once a day */
 108         next_time = 24 * 60 * 60;
 109     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 110                (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
 111                (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
 112                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 113         /* Repeat once an hour */
 114         next_time = 60 * 60;
 115     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 116                (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
 117                (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
 118                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 119         /* Repeat once a minute */
 120         next_time = 60;
 121     } else {
 122         /* Repeat once a second */
 123         next_time = 1;
 124     }
 125     timer_mod(NVRAM->alrm_timer, qemu_clock_get_ns(rtc_clock) +
 126                     next_time * 1000);
 127     qemu_set_irq(NVRAM->IRQ, 0);
 128 }
 129
 130 static void set_alarm(M48t59State *NVRAM)
 131 {
 132     int diff;
 133     if (NVRAM->alrm_timer != NULL) {
 134         timer_del(NVRAM->alrm_timer);
 135         diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
 136         if (diff > 0)
 137             timer_mod(NVRAM->alrm_timer, diff * 1000);
 138     }
 139 }
 140
 141 /* RTC management helpers */
 142 static inline void get_time(M48t59State *NVRAM, struct tm *tm)
 143 {
 144     qemu_get_timedate(tm, NVRAM->time_offset);
 145 }
 146
 147 static void set_time(M48t59State *NVRAM, struct tm *tm)
 148 {
 149     NVRAM->time_offset = qemu_timedate_diff(tm);
 150     set_alarm(NVRAM);
 151 }
 152
 153 /* Watchdog management */
 154 static void watchdog_cb (void *opaque)
 155 {
 156     M48t59State *NVRAM = opaque;
 157
 158     NVRAM->buffer[0x1FF0] |= 0x80;
 159     if (NVRAM->buffer[0x1FF7] & 0x80) {
 160         NVRAM->buffer[0x1FF7] = 0x00;
 161         NVRAM->buffer[0x1FFC] &= ~0x40;
 162         /* May it be a hw CPU Reset instead ? */
 163         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 164     } else {
 165         qemu_set_irq(NVRAM->IRQ, 1);
 166         qemu_set_irq(NVRAM->IRQ, 0);
 167     }
 168 }
 169
 170 static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
 171 {
 172     uint64_t interval; /* in 1/16 seconds */
 173
 174     NVRAM->buffer[0x1FF0] &= ~0x80;
 175     if (NVRAM->wd_timer != NULL) {
 176         timer_del(NVRAM->wd_timer);
 177         if (value != 0) {
 178             interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
 179             timer_mod(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
 180                            ((interval * 1000) >> 4));
 181         }
 182     }
 183 }
 184
 185 /* Direct access to NVRAM */
 186 void m48t59_write(M48t59State *NVRAM, uint32_t addr, uint32_t val)
 187 {
 188     struct tm tm;
 189     int tmp;
 190
 191     if (addr > 0x1FF8 && addr < 0x2000)
 192         NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
 193
 194     /* check for NVRAM access */
 195     if ((NVRAM->model == 2 && addr < 0x7f8) ||
 196         (NVRAM->model == 8 && addr < 0x1ff8) ||
 197         (NVRAM->model == 59 && addr < 0x1ff0)) {
 198         goto do_write;
 199     }
 200
 201     /* TOD access */
 202     switch (addr) {
 203     case 0x1FF0:
 204         /* flags register : read-only */
 205         break;
 206     case 0x1FF1:
 207         /* unused */
 208         break;
 209     case 0x1FF2:
 210         /* alarm seconds */
 211         tmp = from_bcd(val & 0x7F);
 212         if (tmp >= 0 && tmp <= 59) {
 213             NVRAM->alarm.tm_sec = tmp;
 214             NVRAM->buffer[0x1FF2] = val;
 215             set_alarm(NVRAM);
 216         }
 217         break;
 218     case 0x1FF3:
 219         /* alarm minutes */
 220         tmp = from_bcd(val & 0x7F);
 221         if (tmp >= 0 && tmp <= 59) {
 222             NVRAM->alarm.tm_min = tmp;
 223             NVRAM->buffer[0x1FF3] = val;
 224             set_alarm(NVRAM);
 225         }
 226         break;
 227     case 0x1FF4:
 228         /* alarm hours */
 229         tmp = from_bcd(val & 0x3F);
 230         if (tmp >= 0 && tmp <= 23) {
 231             NVRAM->alarm.tm_hour = tmp;
 232             NVRAM->buffer[0x1FF4] = val;
 233             set_alarm(NVRAM);
 234         }
 235         break;
 236     case 0x1FF5:
 237         /* alarm date */
 238         tmp = from_bcd(val & 0x3F);
 239         if (tmp != 0) {
 240             NVRAM->alarm.tm_mday = tmp;
 241             NVRAM->buffer[0x1FF5] = val;
 242             set_alarm(NVRAM);
 243         }
 244         break;
 245     case 0x1FF6:
 246         /* interrupts */
 247         NVRAM->buffer[0x1FF6] = val;
 248         break;
 249     case 0x1FF7:
 250         /* watchdog */
 251         NVRAM->buffer[0x1FF7] = val;
 252         set_up_watchdog(NVRAM, val);
 253         break;
 254     case 0x1FF8:
 255     case 0x07F8:
 256         /* control */
 257        NVRAM->buffer[addr] = (val & ~0xA0) | 0x90;
 258         break;
 259     case 0x1FF9:
 260     case 0x07F9:
 261         /* seconds (BCD) */
 262         tmp = from_bcd(val & 0x7F);
 263         if (tmp >= 0 && tmp <= 59) {
 264             get_time(NVRAM, &tm);
 265             tm.tm_sec = tmp;
 266             set_time(NVRAM, &tm);
 267         }
 268         if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
 269             if (val & 0x80) {
 270                 NVRAM->stop_time = time(NULL);
 271             } else {
 272                 NVRAM->time_offset += NVRAM->stop_time - time(NULL);
 273                 NVRAM->stop_time = 0;
 274             }
 275         }
 276         NVRAM->buffer[addr] = val & 0x80;
 277         break;
 278     case 0x1FFA:
 279     case 0x07FA:
 280         /* minutes (BCD) */
 281         tmp = from_bcd(val & 0x7F);
 282         if (tmp >= 0 && tmp <= 59) {
 283             get_time(NVRAM, &tm);
 284             tm.tm_min = tmp;
 285             set_time(NVRAM, &tm);
 286         }
 287         break;
 288     case 0x1FFB:
 289     case 0x07FB:
 290         /* hours (BCD) */
 291         tmp = from_bcd(val & 0x3F);
 292         if (tmp >= 0 && tmp <= 23) {
 293             get_time(NVRAM, &tm);
 294             tm.tm_hour = tmp;
 295             set_time(NVRAM, &tm);
 296         }
 297         break;
 298     case 0x1FFC:
 299     case 0x07FC:
 300         /* day of the week / century */
 301         tmp = from_bcd(val & 0x07);
 302         get_time(NVRAM, &tm);
 303         tm.tm_wday = tmp;
 304         set_time(NVRAM, &tm);
 305         NVRAM->buffer[addr] = val & 0x40;
 306         break;
 307     case 0x1FFD:
 308     case 0x07FD:
 309         /* date (BCD) */
 310        tmp = from_bcd(val & 0x3F);
 311         if (tmp != 0) {
 312             get_time(NVRAM, &tm);
 313             tm.tm_mday = tmp;
 314             set_time(NVRAM, &tm);
 315         }
 316         break;
 317     case 0x1FFE:
 318     case 0x07FE:
 319         /* month */
 320         tmp = from_bcd(val & 0x1F);
 321         if (tmp >= 1 && tmp <= 12) {
 322             get_time(NVRAM, &tm);
 323             tm.tm_mon = tmp - 1;
 324             set_time(NVRAM, &tm);
 325         }
 326         break;
 327     case 0x1FFF:
 328     case 0x07FF:
 329         /* year */
 330         tmp = from_bcd(val);
 331         if (tmp >= 0 && tmp <= 99) {
 332             get_time(NVRAM, &tm);
 333             tm.tm_year = from_bcd(val) + NVRAM->base_year - 1900;
 334             set_time(NVRAM, &tm);
 335         }
 336         break;
 337     default:
 338         /* Check lock registers state */
 339         if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
 340             break;
 341         if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
 342             break;
 343     do_write:
 344         if (addr < NVRAM->size) {
 345             NVRAM->buffer[addr] = val & 0xFF;
 346         }
 347         break;
 348     }
 349 }
 350
 351 uint32_t m48t59_read(M48t59State *NVRAM, uint32_t addr)
 352 {
 353     struct tm tm;
 354     uint32_t retval = 0xFF;
 355
 356     /* check for NVRAM access */
 357     if ((NVRAM->model == 2 && addr < 0x078f) ||
 358         (NVRAM->model == 8 && addr < 0x1ff8) ||
 359         (NVRAM->model == 59 && addr < 0x1ff0)) {
 360         goto do_read;
 361     }
 362
 363     /* TOD access */
 364     switch (addr) {
 365     case 0x1FF0:
 366         /* flags register */
 367         goto do_read;
 368     case 0x1FF1:
 369         /* unused */
 370         retval = 0;
 371         break;
 372     case 0x1FF2:
 373         /* alarm seconds */
 374         goto do_read;
 375     case 0x1FF3:
 376         /* alarm minutes */
 377         goto do_read;
 378     case 0x1FF4:
 379         /* alarm hours */
 380         goto do_read;
 381     case 0x1FF5:
 382         /* alarm date */
 383         goto do_read;
 384     case 0x1FF6:
 385         /* interrupts */
 386         goto do_read;
 387     case 0x1FF7:
 388         /* A read resets the watchdog */
 389         set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
 390         goto do_read;
 391     case 0x1FF8:
 392     case 0x07F8:
 393         /* control */
 394         goto do_read;
 395     case 0x1FF9:
 396     case 0x07F9:
 397         /* seconds (BCD) */
 398         get_time(NVRAM, &tm);
 399         retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec);
 400         break;
 401     case 0x1FFA:
 402     case 0x07FA:
 403         /* minutes (BCD) */
 404         get_time(NVRAM, &tm);
 405         retval = to_bcd(tm.tm_min);
 406         break;
 407     case 0x1FFB:
 408     case 0x07FB:
 409         /* hours (BCD) */
 410         get_time(NVRAM, &tm);
 411         retval = to_bcd(tm.tm_hour);
 412         break;
 413     case 0x1FFC:
 414     case 0x07FC:
 415         /* day of the week / century */
 416         get_time(NVRAM, &tm);
 417         retval = NVRAM->buffer[addr] | tm.tm_wday;
 418         break;
 419     case 0x1FFD:
 420     case 0x07FD:
 421         /* date */
 422         get_time(NVRAM, &tm);
 423         retval = to_bcd(tm.tm_mday);
 424         break;
 425     case 0x1FFE:
 426     case 0x07FE:
 427         /* month */
 428         get_time(NVRAM, &tm);
 429         retval = to_bcd(tm.tm_mon + 1);
 430         break;
 431     case 0x1FFF:
 432     case 0x07FF:
 433         /* year */
 434         get_time(NVRAM, &tm);
 435         retval = to_bcd((tm.tm_year + 1900 - NVRAM->base_year) % 100);
 436         break;
 437     default:
 438         /* Check lock registers state */
 439         if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
 440             break;
 441         if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
 442             break;
 443     do_read:
 444         if (addr < NVRAM->size) {
 445             retval = NVRAM->buffer[addr];
 446         }
 447         break;
 448     }
 449     if (addr > 0x1FF9 && addr < 0x2000)
 450        NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
 451
 452     return retval;
 453 }
 454
 455 /* IO access to NVRAM */
 456 static void NVRAM_writeb(void *opaque, hwaddr addr, uint64_t val,
 457                          unsigned size)
 458 {
 459     M48t59State *NVRAM = opaque;
 460
 461     NVRAM_PRINTF("%s: 0x%"HWADDR_PRIx" => 0x%"PRIx64"\n", __func__, addr, val);
 462     switch (addr) {
 463     case 0:
 464         NVRAM->addr &= ~0x00FF;
 465         NVRAM->addr |= val;
 466         break;
 467     case 1:
 468         NVRAM->addr &= ~0xFF00;
 469         NVRAM->addr |= val << 8;
 470         break;
 471     case 3:
 472         m48t59_write(NVRAM, NVRAM->addr, val);
 473         NVRAM->addr = 0x0000;
 474         break;
 475     default:
 476         break;
 477     }
 478 }
 479
 480 static uint64_t NVRAM_readb(void *opaque, hwaddr addr, unsigned size)
 481 {
 482     M48t59State *NVRAM = opaque;
 483     uint32_t retval;
 484
 485     switch (addr) {
 486     case 3:
 487         retval = m48t59_read(NVRAM, NVRAM->addr);
 488         break;
 489     default:
 490         retval = -1;
 491         break;
 492     }
 493     NVRAM_PRINTF("%s: 0x%"HWADDR_PRIx" <= 0x%08x\n", __func__, addr, retval);
 494
 495     return retval;
 496 }
 497
 498 static uint64_t nvram_read(void *opaque, hwaddr addr, unsigned size)
 499 {
 500     M48t59State *NVRAM = opaque;
 501
 502     return m48t59_read(NVRAM, addr);
 503 }
 504
 505 static void nvram_write(void *opaque, hwaddr addr, uint64_t value,
 506                         unsigned size)
 507 {
 508     M48t59State *NVRAM = opaque;
 509
 510     return m48t59_write(NVRAM, addr, value);
 511 }
 512
 513 static const MemoryRegionOps nvram_ops = {
 514     .read = nvram_read,
 515     .write = nvram_write,
 516     .impl.min_access_size = 1,
 517     .impl.max_access_size = 1,
 518     .valid.min_access_size = 1,
 519     .valid.max_access_size = 4,
 520     .endianness = DEVICE_BIG_ENDIAN,
 521 };
 522
 523 static const VMStateDescription vmstate_m48t59 = {
 524     .name = "m48t59",
 525     .version_id = 1,
 526     .minimum_version_id = 1,
 527     .fields = (VMStateField[]) {
 528         VMSTATE_UINT8(lock, M48t59State),
 529         VMSTATE_UINT16(addr, M48t59State),
 530         VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, size),
 531         VMSTATE_END_OF_LIST()
 532     }
 533 };
 534
 535 void m48t59_reset_common(M48t59State *NVRAM)
 536 {
 537     NVRAM->addr = 0;
 538     NVRAM->lock = 0;
 539     if (NVRAM->alrm_timer != NULL)
 540         timer_del(NVRAM->alrm_timer);
 541
 542     if (NVRAM->wd_timer != NULL)
 543         timer_del(NVRAM->wd_timer);
 544 }
 545
 546 static void m48t59_reset_sysbus(DeviceState *d)
 547 {
 548     M48txxSysBusState *sys = M48TXX_SYS_BUS(d);
 549     M48t59State *NVRAM = &sys->state;
 550
 551     m48t59_reset_common(NVRAM);
 552 }
 553
 554 const MemoryRegionOps m48t59_io_ops = {
 555     .read = NVRAM_readb,
 556     .write = NVRAM_writeb,
 557     .impl = {
 558         .min_access_size = 1,
 559         .max_access_size = 1,
 560     },
 561     .endianness = DEVICE_LITTLE_ENDIAN,
 562 };
 563
 564 /* Initialisation routine */
 565 Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
 566                    uint32_t io_base, uint16_t size, int base_year,
 567                    int model)
 568 {
 569     DeviceState *dev;
 570     SysBusDevice *s;
 571     int i;
 572
 573     for (i = 0; i < ARRAY_SIZE(m48txx_sysbus_info); i++) {
 574         if (m48txx_sysbus_info[i].size != size ||
 575             m48txx_sysbus_info[i].model != model) {
 576             continue;
 577         }
 578
 579         dev = qdev_create(NULL, m48txx_sysbus_info[i].bus_name);
 580         qdev_prop_set_int32(dev, "base-year", base_year);
 581         qdev_init_nofail(dev);
 582         s = SYS_BUS_DEVICE(dev);
 583         sysbus_connect_irq(s, 0, IRQ);
 584         if (io_base != 0) {
 585             memory_region_add_subregion(get_system_io(), io_base,
 586                                         sysbus_mmio_get_region(s, 1));
 587         }
 588         if (mem_base != 0) {
 589             sysbus_mmio_map(s, 0, mem_base);
 590         }
 591
 592         return NVRAM(s);
 593     }
 594
 595     assert(false);
 596     return NULL;
 597 }
 598
 599 void m48t59_realize_common(M48t59State *s, Error **errp)
 600 {
 601     s->buffer = g_malloc0(s->size);
 602     if (s->model == 59) {
 603         s->alrm_timer = timer_new_ns(rtc_clock, &alarm_cb, s);
 604         s->wd_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &watchdog_cb, s);
 605     }
 606     qemu_get_timedate(&s->alarm, 0);
 607 }
 608
 609 static void m48t59_init1(Object *obj)
 610 {
 611     M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_GET_CLASS(obj);
 612     M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
 613     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 614     M48t59State *s = &d->state;
 615
 616     s->model = u->info.model;
 617     s->size = u->info.size;
 618     sysbus_init_irq(dev, &s->IRQ);
 619
 620     memory_region_init_io(&s->iomem, obj, &nvram_ops, s, "m48t59.nvram",
 621                           s->size);
 622     memory_region_init_io(&d->io, obj, &m48t59_io_ops, s, "m48t59", 4);
 623 }
 624
 625 static void m48t59_realize(DeviceState *dev, Error **errp)
 626 {
 627     M48txxSysBusState *d = M48TXX_SYS_BUS(dev);
 628     M48t59State *s = &d->state;
 629     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 630
 631     sysbus_init_mmio(sbd, &s->iomem);
 632     sysbus_init_mmio(sbd, &d->io);
 633     m48t59_realize_common(s, errp);
 634 }
 635
 636 static uint32_t m48txx_sysbus_read(Nvram *obj, uint32_t addr)
 637 {
 638     M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
 639     return m48t59_read(&d->state, addr);
 640 }
 641
 642 static void m48txx_sysbus_write(Nvram *obj, uint32_t addr, uint32_t val)
 643 {
 644     M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
 645     m48t59_write(&d->state, addr, val);
 646 }
 647
 648 static void m48txx_sysbus_toggle_lock(Nvram *obj, int lock)
 649 {
 650     M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
 651     m48t59_toggle_lock(&d->state, lock);
 652 }
 653
 654 static Property m48t59_sysbus_properties[] = {
 655     DEFINE_PROP_INT32("base-year", M48txxSysBusState, state.base_year, 0),
 656     DEFINE_PROP_END_OF_LIST(),
 657 };
 658
 659 static void m48txx_sysbus_class_init(ObjectClass *klass, void *data)
 660 {
 661     DeviceClass *dc = DEVICE_CLASS(klass);
 662     NvramClass *nc = NVRAM_CLASS(klass);
 663
 664     dc->realize = m48t59_realize;
 665     dc->reset = m48t59_reset_sysbus;
 666     dc->props = m48t59_sysbus_properties;
 667     dc->vmsd = &vmstate_m48t59;
 668     nc->read = m48txx_sysbus_read;
 669     nc->write = m48txx_sysbus_write;
 670     nc->toggle_lock = m48txx_sysbus_toggle_lock;
 671 }
 672
 673 static void m48txx_sysbus_concrete_class_init(ObjectClass *klass, void *data)
 674 {
 675     M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_CLASS(klass);
 676     M48txxInfo *info = data;
 677
 678     u->info = *info;
 679 }
 680
 681 static const TypeInfo nvram_info = {
 682     .name = TYPE_NVRAM,
 683     .parent = TYPE_INTERFACE,
 684     .class_size = sizeof(NvramClass),
 685 };
 686
 687 static const TypeInfo m48txx_sysbus_type_info = {
 688     .name = TYPE_M48TXX_SYS_BUS,
 689     .parent = TYPE_SYS_BUS_DEVICE,
 690     .instance_size = sizeof(M48txxSysBusState),
 691     .instance_init = m48t59_init1,
 692     .abstract = true,
 693     .class_init = m48txx_sysbus_class_init,
 694     .interfaces = (InterfaceInfo[]) {
 695         { TYPE_NVRAM },
 696         { }
 697     }
 698 };
 699
 700 static void m48t59_register_types(void)
 701 {
 702     TypeInfo sysbus_type_info = {
 703         .parent = TYPE_M48TXX_SYS_BUS,
 704         .class_size = sizeof(M48txxSysBusDeviceClass),
 705         .class_init = m48txx_sysbus_concrete_class_init,
 706     };
 707     int i;
 708
 709     type_register_static(&nvram_info);
 710     type_register_static(&m48txx_sysbus_type_info);
 711
 712     for (i = 0; i < ARRAY_SIZE(m48txx_sysbus_info); i++) {
 713         sysbus_type_info.name = m48txx_sysbus_info[i].bus_name;
 714         sysbus_type_info.class_data = &m48txx_sysbus_info[i];
 715         type_register(&sysbus_type_info);
 716     }
 717 }
 718
 719 type_init(m48t59_register_types)