hw/timer/m48t59.c

   1 /*
   2  * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
   3  *
   4  * Copyright (c) 2003-2005, 2007, 2017 Jocelyn Mayer
   5  * Copyright (c) 2013 Hervé Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25
  26 #include "qemu/osdep.h"
  27 #include "qemu-common.h"
  28 #include "hw/hw.h"
  29 #include "hw/irq.h"
  30 #include "hw/timer/m48t59.h"
  31 #include "qemu/timer.h"
  32 #include "sysemu/sysemu.h"
  33 #include "hw/sysbus.h"
  34 #include "exec/address-spaces.h"
  35 #include "qemu/bcd.h"
  36 #include "qemu/module.h"
  37
  38 #include "m48t59-internal.h"
  39
  40 #define TYPE_M48TXX_SYS_BUS "sysbus-m48txx"
  41 #define M48TXX_SYS_BUS_GET_CLASS(obj) \
  42     OBJECT_GET_CLASS(M48txxSysBusDeviceClass, (obj), TYPE_M48TXX_SYS_BUS)
  43 #define M48TXX_SYS_BUS_CLASS(klass) \
  44     OBJECT_CLASS_CHECK(M48txxSysBusDeviceClass, (klass), TYPE_M48TXX_SYS_BUS)
  45 #define M48TXX_SYS_BUS(obj) \
  46     OBJECT_CHECK(M48txxSysBusState, (obj), TYPE_M48TXX_SYS_BUS)
  47
  48 /*
  49  * Chipset docs:
  50  * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
  51  * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
  52  * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
  53  */
  54
  55 typedef struct M48txxSysBusState {
  56     SysBusDevice parent_obj;
  57     M48t59State state;
  58     MemoryRegion io;
  59 } M48txxSysBusState;
  60
  61 typedef struct M48txxSysBusDeviceClass {
  62     SysBusDeviceClass parent_class;
  63     M48txxInfo info;
  64 } M48txxSysBusDeviceClass;
  65
  66 static M48txxInfo m48txx_sysbus_info[] = {
  67     {
  68         .bus_name = "sysbus-m48t02",
  69         .model = 2,
  70         .size = 0x800,
  71     },{
  72         .bus_name = "sysbus-m48t08",
  73         .model = 8,
  74         .size = 0x2000,
  75     },{
  76         .bus_name = "sysbus-m48t59",
  77         .model = 59,
  78         .size = 0x2000,
  79     }
  80 };
  81
  82
  83 /* Fake timer functions */
  84
  85 /* Alarm management */
  86 static void alarm_cb (void *opaque)
  87 {
  88     struct tm tm;
  89     uint64_t next_time;
  90     M48t59State *NVRAM = opaque;
  91
  92     qemu_set_irq(NVRAM->IRQ, 1);
  93     if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
  94         (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
  95         (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
  96         (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
  97         /* Repeat once a month */
  98         qemu_get_timedate(&tm, NVRAM->time_offset);
  99         tm.tm_mon++;
 100         if (tm.tm_mon == 13) {
 101             tm.tm_mon = 1;
 102             tm.tm_year++;
 103         }
 104         next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset;
 105     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 106                (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
 107                (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
 108                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 109         /* Repeat once a day */
 110         next_time = 24 * 60 * 60;
 111     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 112                (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
 113                (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
 114                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 115         /* Repeat once an hour */
 116         next_time = 60 * 60;
 117     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 118                (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
 119                (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
 120                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 121         /* Repeat once a minute */
 122         next_time = 60;
 123     } else {
 124         /* Repeat once a second */
 125         next_time = 1;
 126     }
 127     timer_mod(NVRAM->alrm_timer, qemu_clock_get_ns(rtc_clock) +
 128                     next_time * 1000);
 129     qemu_set_irq(NVRAM->IRQ, 0);
 130 }
 131
 132 static void set_alarm(M48t59State *NVRAM)
 133 {
 134     int diff;
 135     if (NVRAM->alrm_timer != NULL) {
 136         timer_del(NVRAM->alrm_timer);
 137         diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
 138         if (diff > 0)
 139             timer_mod(NVRAM->alrm_timer, diff * 1000);
 140     }
 141 }
 142
 143 /* RTC management helpers */
 144 static inline void get_time(M48t59State *NVRAM, struct tm *tm)
 145 {
 146     qemu_get_timedate(tm, NVRAM->time_offset);
 147 }
 148
 149 static void set_time(M48t59State *NVRAM, struct tm *tm)
 150 {
 151     NVRAM->time_offset = qemu_timedate_diff(tm);
 152     set_alarm(NVRAM);
 153 }
 154
 155 /* Watchdog management */
 156 static void watchdog_cb (void *opaque)
 157 {
 158     M48t59State *NVRAM = opaque;
 159
 160     NVRAM->buffer[0x1FF0] |= 0x80;
 161     if (NVRAM->buffer[0x1FF7] & 0x80) {
 162         NVRAM->buffer[0x1FF7] = 0x00;
 163         NVRAM->buffer[0x1FFC] &= ~0x40;
 164         /* May it be a hw CPU Reset instead ? */
 165         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
 166     } else {
 167         qemu_set_irq(NVRAM->IRQ, 1);
 168         qemu_set_irq(NVRAM->IRQ, 0);
 169     }
 170 }
 171
 172 static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
 173 {
 174     uint64_t interval; /* in 1/16 seconds */
 175
 176     NVRAM->buffer[0x1FF0] &= ~0x80;
 177     if (NVRAM->wd_timer != NULL) {
 178         timer_del(NVRAM->wd_timer);
 179         if (value != 0) {
 180             interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
 181             timer_mod(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
 182                            ((interval * 1000) >> 4));
 183         }
 184     }
 185 }
 186
 187 /* Direct access to NVRAM */
 188 void m48t59_write(M48t59State *NVRAM, uint32_t addr, uint32_t val)
 189 {
 190     struct tm tm;
 191     int tmp;
 192
 193     if (addr > 0x1FF8 && addr < 0x2000)
 194         NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
 195
 196     /* check for NVRAM access */
 197     if ((NVRAM->model == 2 && addr < 0x7f8) ||
 198         (NVRAM->model == 8 && addr < 0x1ff8) ||
 199         (NVRAM->model == 59 && addr < 0x1ff0)) {
 200         goto do_write;
 201     }
 202
 203     /* TOD access */
 204     switch (addr) {
 205     case 0x1FF0:
 206         /* flags register : read-only */
 207         break;
 208     case 0x1FF1:
 209         /* unused */
 210         break;
 211     case 0x1FF2:
 212         /* alarm seconds */
 213         tmp = from_bcd(val & 0x7F);
 214         if (tmp >= 0 && tmp <= 59) {
 215             NVRAM->alarm.tm_sec = tmp;
 216             NVRAM->buffer[0x1FF2] = val;
 217             set_alarm(NVRAM);
 218         }
 219         break;
 220     case 0x1FF3:
 221         /* alarm minutes */
 222         tmp = from_bcd(val & 0x7F);
 223         if (tmp >= 0 && tmp <= 59) {
 224             NVRAM->alarm.tm_min = tmp;
 225             NVRAM->buffer[0x1FF3] = val;
 226             set_alarm(NVRAM);
 227         }
 228         break;
 229     case 0x1FF4:
 230         /* alarm hours */
 231         tmp = from_bcd(val & 0x3F);
 232         if (tmp >= 0 && tmp <= 23) {
 233             NVRAM->alarm.tm_hour = tmp;
 234             NVRAM->buffer[0x1FF4] = val;
 235             set_alarm(NVRAM);
 236         }
 237         break;
 238     case 0x1FF5:
 239         /* alarm date */
 240         tmp = from_bcd(val & 0x3F);
 241         if (tmp != 0) {
 242             NVRAM->alarm.tm_mday = tmp;
 243             NVRAM->buffer[0x1FF5] = val;
 244             set_alarm(NVRAM);
 245         }
 246         break;
 247     case 0x1FF6:
 248         /* interrupts */
 249         NVRAM->buffer[0x1FF6] = val;
 250         break;
 251     case 0x1FF7:
 252         /* watchdog */
 253         NVRAM->buffer[0x1FF7] = val;
 254         set_up_watchdog(NVRAM, val);
 255         break;
 256     case 0x1FF8:
 257     case 0x07F8:
 258         /* control */
 259        NVRAM->buffer[addr] = (val & ~0xA0) | 0x90;
 260         break;
 261     case 0x1FF9:
 262     case 0x07F9:
 263         /* seconds (BCD) */
 264         tmp = from_bcd(val & 0x7F);
 265         if (tmp >= 0 && tmp <= 59) {
 266             get_time(NVRAM, &tm);
 267             tm.tm_sec = tmp;
 268             set_time(NVRAM, &tm);
 269         }
 270         if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
 271             if (val & 0x80) {
 272                 NVRAM->stop_time = time(NULL);
 273             } else {
 274                 NVRAM->time_offset += NVRAM->stop_time - time(NULL);
 275                 NVRAM->stop_time = 0;
 276             }
 277         }
 278         NVRAM->buffer[addr] = val & 0x80;
 279         break;
 280     case 0x1FFA:
 281     case 0x07FA:
 282         /* minutes (BCD) */
 283         tmp = from_bcd(val & 0x7F);
 284         if (tmp >= 0 && tmp <= 59) {
 285             get_time(NVRAM, &tm);
 286             tm.tm_min = tmp;
 287             set_time(NVRAM, &tm);
 288         }
 289         break;
 290     case 0x1FFB:
 291     case 0x07FB:
 292         /* hours (BCD) */
 293         tmp = from_bcd(val & 0x3F);
 294         if (tmp >= 0 && tmp <= 23) {
 295             get_time(NVRAM, &tm);
 296             tm.tm_hour = tmp;
 297             set_time(NVRAM, &tm);
 298         }
 299         break;
 300     case 0x1FFC:
 301     case 0x07FC:
 302         /* day of the week / century */
 303         tmp = from_bcd(val & 0x07);
 304         get_time(NVRAM, &tm);
 305         tm.tm_wday = tmp;
 306         set_time(NVRAM, &tm);
 307         NVRAM->buffer[addr] = val & 0x40;
 308         break;
 309     case 0x1FFD:
 310     case 0x07FD:
 311         /* date (BCD) */
 312        tmp = from_bcd(val & 0x3F);
 313         if (tmp != 0) {
 314             get_time(NVRAM, &tm);
 315             tm.tm_mday = tmp;
 316             set_time(NVRAM, &tm);
 317         }
 318         break;
 319     case 0x1FFE:
 320     case 0x07FE:
 321         /* month */
 322         tmp = from_bcd(val & 0x1F);
 323         if (tmp >= 1 && tmp <= 12) {
 324             get_time(NVRAM, &tm);
 325             tm.tm_mon = tmp - 1;
 326             set_time(NVRAM, &tm);
 327         }
 328         break;
 329     case 0x1FFF:
 330     case 0x07FF:
 331         /* year */
 332         tmp = from_bcd(val);
 333         if (tmp >= 0 && tmp <= 99) {
 334             get_time(NVRAM, &tm);
 335             tm.tm_year = from_bcd(val) + NVRAM->base_year - 1900;
 336             set_time(NVRAM, &tm);
 337         }
 338         break;
 339     default:
 340         /* Check lock registers state */
 341         if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
 342             break;
 343         if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
 344             break;
 345     do_write:
 346         if (addr < NVRAM->size) {
 347             NVRAM->buffer[addr] = val & 0xFF;
 348         }
 349         break;
 350     }
 351 }
 352
 353 uint32_t m48t59_read(M48t59State *NVRAM, uint32_t addr)
 354 {
 355     struct tm tm;
 356     uint32_t retval = 0xFF;
 357
 358     /* check for NVRAM access */
 359     if ((NVRAM->model == 2 && addr < 0x078f) ||
 360         (NVRAM->model == 8 && addr < 0x1ff8) ||
 361         (NVRAM->model == 59 && addr < 0x1ff0)) {
 362         goto do_read;
 363     }
 364
 365     /* TOD access */
 366     switch (addr) {
 367     case 0x1FF0:
 368         /* flags register */
 369         goto do_read;
 370     case 0x1FF1:
 371         /* unused */
 372         retval = 0;
 373         break;
 374     case 0x1FF2:
 375         /* alarm seconds */
 376         goto do_read;
 377     case 0x1FF3:
 378         /* alarm minutes */
 379         goto do_read;
 380     case 0x1FF4:
 381         /* alarm hours */
 382         goto do_read;
 383     case 0x1FF5:
 384         /* alarm date */
 385         goto do_read;
 386     case 0x1FF6:
 387         /* interrupts */
 388         goto do_read;
 389     case 0x1FF7:
 390         /* A read resets the watchdog */
 391         set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
 392         goto do_read;
 393     case 0x1FF8:
 394     case 0x07F8:
 395         /* control */
 396         goto do_read;
 397     case 0x1FF9:
 398     case 0x07F9:
 399         /* seconds (BCD) */
 400         get_time(NVRAM, &tm);
 401         retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec);
 402         break;
 403     case 0x1FFA:
 404     case 0x07FA:
 405         /* minutes (BCD) */
 406         get_time(NVRAM, &tm);
 407         retval = to_bcd(tm.tm_min);
 408         break;
 409     case 0x1FFB:
 410     case 0x07FB:
 411         /* hours (BCD) */
 412         get_time(NVRAM, &tm);
 413         retval = to_bcd(tm.tm_hour);
 414         break;
 415     case 0x1FFC:
 416     case 0x07FC:
 417         /* day of the week / century */
 418         get_time(NVRAM, &tm);
 419         retval = NVRAM->buffer[addr] | tm.tm_wday;
 420         break;
 421     case 0x1FFD:
 422     case 0x07FD:
 423         /* date */
 424         get_time(NVRAM, &tm);
 425         retval = to_bcd(tm.tm_mday);
 426         break;
 427     case 0x1FFE:
 428     case 0x07FE:
 429         /* month */
 430         get_time(NVRAM, &tm);
 431         retval = to_bcd(tm.tm_mon + 1);
 432         break;
 433     case 0x1FFF:
 434     case 0x07FF:
 435         /* year */
 436         get_time(NVRAM, &tm);
 437         retval = to_bcd((tm.tm_year + 1900 - NVRAM->base_year) % 100);
 438         break;
 439     default:
 440         /* Check lock registers state */
 441         if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
 442             break;
 443         if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
 444             break;
 445     do_read:
 446         if (addr < NVRAM->size) {
 447             retval = NVRAM->buffer[addr];
 448         }
 449         break;
 450     }
 451     if (addr > 0x1FF9 && addr < 0x2000)
 452        NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
 453
 454     return retval;
 455 }
 456
 457 /* IO access to NVRAM */
 458 static void NVRAM_writeb(void *opaque, hwaddr addr, uint64_t val,
 459                          unsigned size)
 460 {
 461     M48t59State *NVRAM = opaque;
 462
 463     NVRAM_PRINTF("%s: 0x%"HWADDR_PRIx" => 0x%"PRIx64"\n", __func__, addr, val);
 464     switch (addr) {
 465     case 0:
 466         NVRAM->addr &= ~0x00FF;
 467         NVRAM->addr |= val;
 468         break;
 469     case 1:
 470         NVRAM->addr &= ~0xFF00;
 471         NVRAM->addr |= val << 8;
 472         break;
 473     case 3:
 474         m48t59_write(NVRAM, NVRAM->addr, val);
 475         NVRAM->addr = 0x0000;
 476         break;
 477     default:
 478         break;
 479     }
 480 }
 481
 482 static uint64_t NVRAM_readb(void *opaque, hwaddr addr, unsigned size)
 483 {
 484     M48t59State *NVRAM = opaque;
 485     uint32_t retval;
 486
 487     switch (addr) {
 488     case 3:
 489         retval = m48t59_read(NVRAM, NVRAM->addr);
 490         break;
 491     default:
 492         retval = -1;
 493         break;
 494     }
 495     NVRAM_PRINTF("%s: 0x%"HWADDR_PRIx" <= 0x%08x\n", __func__, addr, retval);
 496
 497     return retval;
 498 }
 499
 500 static uint64_t nvram_read(void *opaque, hwaddr addr, unsigned size)
 501 {
 502     M48t59State *NVRAM = opaque;
 503
 504     return m48t59_read(NVRAM, addr);
 505 }
 506
 507 static void nvram_write(void *opaque, hwaddr addr, uint64_t value,
 508                         unsigned size)
 509 {
 510     M48t59State *NVRAM = opaque;
 511
 512     return m48t59_write(NVRAM, addr, value);
 513 }
 514
 515 static const MemoryRegionOps nvram_ops = {
 516     .read = nvram_read,
 517     .write = nvram_write,
 518     .impl.min_access_size = 1,
 519     .impl.max_access_size = 1,
 520     .valid.min_access_size = 1,
 521     .valid.max_access_size = 4,
 522     .endianness = DEVICE_BIG_ENDIAN,
 523 };
 524
 525 static const VMStateDescription vmstate_m48t59 = {
 526     .name = "m48t59",
 527     .version_id = 1,
 528     .minimum_version_id = 1,
 529     .fields = (VMStateField[]) {
 530         VMSTATE_UINT8(lock, M48t59State),
 531         VMSTATE_UINT16(addr, M48t59State),
 532         VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, size),
 533         VMSTATE_END_OF_LIST()
 534     }
 535 };
 536
 537 void m48t59_reset_common(M48t59State *NVRAM)
 538 {
 539     NVRAM->addr = 0;
 540     NVRAM->lock = 0;
 541     if (NVRAM->alrm_timer != NULL)
 542         timer_del(NVRAM->alrm_timer);
 543
 544     if (NVRAM->wd_timer != NULL)
 545         timer_del(NVRAM->wd_timer);
 546 }
 547
 548 static void m48t59_reset_sysbus(DeviceState *d)
 549 {
 550     M48txxSysBusState *sys = M48TXX_SYS_BUS(d);
 551     M48t59State *NVRAM = &sys->state;
 552
 553     m48t59_reset_common(NVRAM);
 554 }
 555
 556 const MemoryRegionOps m48t59_io_ops = {
 557     .read = NVRAM_readb,
 558     .write = NVRAM_writeb,
 559     .impl = {
 560         .min_access_size = 1,
 561         .max_access_size = 1,
 562     },
 563     .endianness = DEVICE_LITTLE_ENDIAN,
 564 };
 565
 566 /* Initialisation routine */
 567 Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
 568                    uint32_t io_base, uint16_t size, int base_year,
 569                    int model)
 570 {
 571     DeviceState *dev;
 572     SysBusDevice *s;
 573     int i;
 574
 575     for (i = 0; i < ARRAY_SIZE(m48txx_sysbus_info); i++) {
 576         if (m48txx_sysbus_info[i].size != size ||
 577             m48txx_sysbus_info[i].model != model) {
 578             continue;
 579         }
 580
 581         dev = qdev_create(NULL, m48txx_sysbus_info[i].bus_name);
 582         qdev_prop_set_int32(dev, "base-year", base_year);
 583         qdev_init_nofail(dev);
 584         s = SYS_BUS_DEVICE(dev);
 585         sysbus_connect_irq(s, 0, IRQ);
 586         if (io_base != 0) {
 587             memory_region_add_subregion(get_system_io(), io_base,
 588                                         sysbus_mmio_get_region(s, 1));
 589         }
 590         if (mem_base != 0) {
 591             sysbus_mmio_map(s, 0, mem_base);
 592         }
 593
 594         return NVRAM(s);
 595     }
 596
 597     assert(false);
 598     return NULL;
 599 }
 600
 601 void m48t59_realize_common(M48t59State *s, Error **errp)
 602 {
 603     s->buffer = g_malloc0(s->size);
 604     if (s->model == 59) {
 605         s->alrm_timer = timer_new_ns(rtc_clock, &alarm_cb, s);
 606         s->wd_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &watchdog_cb, s);
 607     }
 608     qemu_get_timedate(&s->alarm, 0);
 609 }
 610
 611 static void m48t59_init1(Object *obj)
 612 {
 613     M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_GET_CLASS(obj);
 614     M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
 615     SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 616     M48t59State *s = &d->state;
 617
 618     s->model = u->info.model;
 619     s->size = u->info.size;
 620     sysbus_init_irq(dev, &s->IRQ);
 621
 622     memory_region_init_io(&s->iomem, obj, &nvram_ops, s, "m48t59.nvram",
 623                           s->size);
 624     memory_region_init_io(&d->io, obj, &m48t59_io_ops, s, "m48t59", 4);
 625 }
 626
 627 static void m48t59_realize(DeviceState *dev, Error **errp)
 628 {
 629     M48txxSysBusState *d = M48TXX_SYS_BUS(dev);
 630     M48t59State *s = &d->state;
 631     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 632
 633     sysbus_init_mmio(sbd, &s->iomem);
 634     sysbus_init_mmio(sbd, &d->io);
 635     m48t59_realize_common(s, errp);
 636 }
 637
 638 static uint32_t m48txx_sysbus_read(Nvram *obj, uint32_t addr)
 639 {
 640     M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
 641     return m48t59_read(&d->state, addr);
 642 }
 643
 644 static void m48txx_sysbus_write(Nvram *obj, uint32_t addr, uint32_t val)
 645 {
 646     M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
 647     m48t59_write(&d->state, addr, val);
 648 }
 649
 650 static void m48txx_sysbus_toggle_lock(Nvram *obj, int lock)
 651 {
 652     M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
 653     m48t59_toggle_lock(&d->state, lock);
 654 }
 655
 656 static Property m48t59_sysbus_properties[] = {
 657     DEFINE_PROP_INT32("base-year", M48txxSysBusState, state.base_year, 0),
 658     DEFINE_PROP_END_OF_LIST(),
 659 };
 660
 661 static void m48txx_sysbus_class_init(ObjectClass *klass, void *data)
 662 {
 663     DeviceClass *dc = DEVICE_CLASS(klass);
 664     NvramClass *nc = NVRAM_CLASS(klass);
 665
 666     dc->realize = m48t59_realize;
 667     dc->reset = m48t59_reset_sysbus;
 668     dc->props = m48t59_sysbus_properties;
 669     dc->vmsd = &vmstate_m48t59;
 670     nc->read = m48txx_sysbus_read;
 671     nc->write = m48txx_sysbus_write;
 672     nc->toggle_lock = m48txx_sysbus_toggle_lock;
 673 }
 674
 675 static void m48txx_sysbus_concrete_class_init(ObjectClass *klass, void *data)
 676 {
 677     M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_CLASS(klass);
 678     M48txxInfo *info = data;
 679
 680     u->info = *info;
 681 }
 682
 683 static const TypeInfo nvram_info = {
 684     .name = TYPE_NVRAM,
 685     .parent = TYPE_INTERFACE,
 686     .class_size = sizeof(NvramClass),
 687 };
 688
 689 static const TypeInfo m48txx_sysbus_type_info = {
 690     .name = TYPE_M48TXX_SYS_BUS,
 691     .parent = TYPE_SYS_BUS_DEVICE,
 692     .instance_size = sizeof(M48txxSysBusState),
 693     .instance_init = m48t59_init1,
 694     .abstract = true,
 695     .class_init = m48txx_sysbus_class_init,
 696     .interfaces = (InterfaceInfo[]) {
 697         { TYPE_NVRAM },
 698         { }
 699     }
 700 };
 701
 702 static void m48t59_register_types(void)
 703 {
 704     TypeInfo sysbus_type_info = {
 705         .parent = TYPE_M48TXX_SYS_BUS,
 706         .class_size = sizeof(M48txxSysBusDeviceClass),
 707         .class_init = m48txx_sysbus_concrete_class_init,
 708     };
 709     int i;
 710
 711     type_register_static(&nvram_info);
 712     type_register_static(&m48txx_sysbus_type_info);
 713
 714     for (i = 0; i < ARRAY_SIZE(m48txx_sysbus_info); i++) {
 715         sysbus_type_info.name = m48txx_sysbus_info[i].bus_name;
 716         sysbus_type_info.class_data = &m48txx_sysbus_info[i];
 717         type_register(&sysbus_type_info);
 718     }
 719 }
 720
 721 type_init(m48t59_register_types)