hw/timer/m48t59.c

   1 /*
   2  * QEMU M48T59 and M48T08 NVRAM emulation for PPC PREP and Sparc platforms
   3  *
   4  * Copyright (c) 2003-2005, 2007 Jocelyn Mayer
   5  * Copyright (c) 2013 Hervé Poussineau
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a copy
   8  * of this software and associated documentation files (the "Software"), to deal
   9  * in the Software without restriction, including without limitation the rights
  10  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11  * copies of the Software, and to permit persons to whom the Software is
  12  * furnished to do so, subject to the following conditions:
  13  *
  14  * The above copyright notice and this permission notice shall be included in
  15  * all copies or substantial portions of the Software.
  16  *
  17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23  * THE SOFTWARE.
  24  */
  25 #include "hw/hw.h"
  26 #include "hw/timer/m48t59.h"
  27 #include "qemu/timer.h"
  28 #include "sysemu/sysemu.h"
  29 #include "hw/sysbus.h"
  30 #include "hw/isa/isa.h"
  31 #include "exec/address-spaces.h"
  32
  33 //#define DEBUG_NVRAM
  34
  35 #if defined(DEBUG_NVRAM)
  36 #define NVRAM_PRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
  37 #else
  38 #define NVRAM_PRINTF(fmt, ...) do { } while (0)
  39 #endif
  40
  41 #define TYPE_M48TXX_SYS_BUS "sysbus-m48txx"
  42 #define M48TXX_SYS_BUS_GET_CLASS(obj) \
  43     OBJECT_GET_CLASS(M48txxSysBusDeviceClass, (obj), TYPE_M48TXX_SYS_BUS)
  44 #define M48TXX_SYS_BUS_CLASS(klass) \
  45     OBJECT_CLASS_CHECK(M48txxSysBusDeviceClass, (klass), TYPE_M48TXX_SYS_BUS)
  46 #define M48TXX_SYS_BUS(obj) \
  47     OBJECT_CHECK(M48txxSysBusState, (obj), TYPE_M48TXX_SYS_BUS)
  48
  49 #define TYPE_M48TXX_ISA "isa-m48txx"
  50 #define M48TXX_ISA_GET_CLASS(obj) \
  51     OBJECT_GET_CLASS(M48txxISADeviceClass, (obj), TYPE_M48TXX_ISA)
  52 #define M48TXX_ISA_CLASS(klass) \
  53     OBJECT_CLASS_CHECK(M48txxISADeviceClass, (klass), TYPE_M48TXX_ISA)
  54 #define M48TXX_ISA(obj) \
  55     OBJECT_CHECK(M48txxISAState, (obj), TYPE_M48TXX_ISA)
  56
  57 /*
  58  * The M48T02, M48T08 and M48T59 chips are very similar. The newer '59 has
  59  * alarm and a watchdog timer and related control registers. In the
  60  * PPC platform there is also a nvram lock function.
  61  */
  62
  63 typedef struct M48txxInfo {
  64     const char *isa_name;
  65     const char *sysbus_name;
  66     uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
  67     uint32_t size;
  68 } M48txxInfo;
  69
  70 /*
  71  * Chipset docs:
  72  * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
  73  * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
  74  * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
  75  */
  76
  77 typedef struct M48t59State {
  78     /* Hardware parameters */
  79     qemu_irq IRQ;
  80     MemoryRegion iomem;
  81     uint32_t size;
  82     int32_t base_year;
  83     /* RTC management */
  84     time_t   time_offset;
  85     time_t   stop_time;
  86     /* Alarm & watchdog */
  87     struct tm alarm;
  88     QEMUTimer *alrm_timer;
  89     QEMUTimer *wd_timer;
  90     /* NVRAM storage */
  91     uint8_t *buffer;
  92     /* Model parameters */
  93     uint32_t model; /* 2 = m48t02, 8 = m48t08, 59 = m48t59 */
  94     /* NVRAM storage */
  95     uint16_t addr;
  96     uint8_t  lock;
  97 } M48t59State;
  98
  99 typedef struct M48txxISAState {
 100     ISADevice parent_obj;
 101     M48t59State state;
 102     uint32_t io_base;
 103     MemoryRegion io;
 104 } M48txxISAState;
 105
 106 typedef struct M48txxISADeviceClass {
 107     ISADeviceClass parent_class;
 108     M48txxInfo info;
 109 } M48txxISADeviceClass;
 110
 111 typedef struct M48txxSysBusState {
 112     SysBusDevice parent_obj;
 113     M48t59State state;
 114     MemoryRegion io;
 115 } M48txxSysBusState;
 116
 117 typedef struct M48txxSysBusDeviceClass {
 118     SysBusDeviceClass parent_class;
 119     M48txxInfo info;
 120 } M48txxSysBusDeviceClass;
 121
 122 static M48txxInfo m48txx_info[] = {
 123     {
 124         .sysbus_name = "sysbus-m48t02",
 125         .model = 2,
 126         .size = 0x800,
 127     },{
 128         .sysbus_name = "sysbus-m48t08",
 129         .model = 8,
 130         .size = 0x2000,
 131     },{
 132         .isa_name = "isa-m48t59",
 133         .model = 59,
 134         .size = 0x2000,
 135     }
 136 };
 137
 138
 139 /* Fake timer functions */
 140
 141 /* Alarm management */
 142 static void alarm_cb (void *opaque)
 143 {
 144     struct tm tm;
 145     uint64_t next_time;
 146     M48t59State *NVRAM = opaque;
 147
 148     qemu_set_irq(NVRAM->IRQ, 1);
 149     if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
 150         (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
 151         (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
 152         (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 153         /* Repeat once a month */
 154         qemu_get_timedate(&tm, NVRAM->time_offset);
 155         tm.tm_mon++;
 156         if (tm.tm_mon == 13) {
 157             tm.tm_mon = 1;
 158             tm.tm_year++;
 159         }
 160         next_time = qemu_timedate_diff(&tm) - NVRAM->time_offset;
 161     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 162                (NVRAM->buffer[0x1FF4] & 0x80) == 0 &&
 163                (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
 164                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 165         /* Repeat once a day */
 166         next_time = 24 * 60 * 60;
 167     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 168                (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
 169                (NVRAM->buffer[0x1FF3] & 0x80) == 0 &&
 170                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 171         /* Repeat once an hour */
 172         next_time = 60 * 60;
 173     } else if ((NVRAM->buffer[0x1FF5] & 0x80) != 0 &&
 174                (NVRAM->buffer[0x1FF4] & 0x80) != 0 &&
 175                (NVRAM->buffer[0x1FF3] & 0x80) != 0 &&
 176                (NVRAM->buffer[0x1FF2] & 0x80) == 0) {
 177         /* Repeat once a minute */
 178         next_time = 60;
 179     } else {
 180         /* Repeat once a second */
 181         next_time = 1;
 182     }
 183     timer_mod(NVRAM->alrm_timer, qemu_clock_get_ns(rtc_clock) +
 184                     next_time * 1000);
 185     qemu_set_irq(NVRAM->IRQ, 0);
 186 }
 187
 188 static void set_alarm(M48t59State *NVRAM)
 189 {
 190     int diff;
 191     if (NVRAM->alrm_timer != NULL) {
 192         timer_del(NVRAM->alrm_timer);
 193         diff = qemu_timedate_diff(&NVRAM->alarm) - NVRAM->time_offset;
 194         if (diff > 0)
 195             timer_mod(NVRAM->alrm_timer, diff * 1000);
 196     }
 197 }
 198
 199 /* RTC management helpers */
 200 static inline void get_time(M48t59State *NVRAM, struct tm *tm)
 201 {
 202     qemu_get_timedate(tm, NVRAM->time_offset);
 203 }
 204
 205 static void set_time(M48t59State *NVRAM, struct tm *tm)
 206 {
 207     NVRAM->time_offset = qemu_timedate_diff(tm);
 208     set_alarm(NVRAM);
 209 }
 210
 211 /* Watchdog management */
 212 static void watchdog_cb (void *opaque)
 213 {
 214     M48t59State *NVRAM = opaque;
 215
 216     NVRAM->buffer[0x1FF0] |= 0x80;
 217     if (NVRAM->buffer[0x1FF7] & 0x80) {
 218         NVRAM->buffer[0x1FF7] = 0x00;
 219         NVRAM->buffer[0x1FFC] &= ~0x40;
 220         /* May it be a hw CPU Reset instead ? */
 221         qemu_system_reset_request();
 222     } else {
 223         qemu_set_irq(NVRAM->IRQ, 1);
 224         qemu_set_irq(NVRAM->IRQ, 0);
 225     }
 226 }
 227
 228 static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
 229 {
 230     uint64_t interval; /* in 1/16 seconds */
 231
 232     NVRAM->buffer[0x1FF0] &= ~0x80;
 233     if (NVRAM->wd_timer != NULL) {
 234         timer_del(NVRAM->wd_timer);
 235         if (value != 0) {
 236             interval = (1 << (2 * (value & 0x03))) * ((value >> 2) & 0x1F);
 237             timer_mod(NVRAM->wd_timer, ((uint64_t)time(NULL) * 1000) +
 238                            ((interval * 1000) >> 4));
 239         }
 240     }
 241 }
 242
 243 /* Direct access to NVRAM */
 244 static void m48t59_write(M48t59State *NVRAM, uint32_t addr, uint32_t val)
 245 {
 246     struct tm tm;
 247     int tmp;
 248
 249     if (addr > 0x1FF8 && addr < 0x2000)
 250         NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
 251
 252     /* check for NVRAM access */
 253     if ((NVRAM->model == 2 && addr < 0x7f8) ||
 254         (NVRAM->model == 8 && addr < 0x1ff8) ||
 255         (NVRAM->model == 59 && addr < 0x1ff0)) {
 256         goto do_write;
 257     }
 258
 259     /* TOD access */
 260     switch (addr) {
 261     case 0x1FF0:
 262         /* flags register : read-only */
 263         break;
 264     case 0x1FF1:
 265         /* unused */
 266         break;
 267     case 0x1FF2:
 268         /* alarm seconds */
 269         tmp = from_bcd(val & 0x7F);
 270         if (tmp >= 0 && tmp <= 59) {
 271             NVRAM->alarm.tm_sec = tmp;
 272             NVRAM->buffer[0x1FF2] = val;
 273             set_alarm(NVRAM);
 274         }
 275         break;
 276     case 0x1FF3:
 277         /* alarm minutes */
 278         tmp = from_bcd(val & 0x7F);
 279         if (tmp >= 0 && tmp <= 59) {
 280             NVRAM->alarm.tm_min = tmp;
 281             NVRAM->buffer[0x1FF3] = val;
 282             set_alarm(NVRAM);
 283         }
 284         break;
 285     case 0x1FF4:
 286         /* alarm hours */
 287         tmp = from_bcd(val & 0x3F);
 288         if (tmp >= 0 && tmp <= 23) {
 289             NVRAM->alarm.tm_hour = tmp;
 290             NVRAM->buffer[0x1FF4] = val;
 291             set_alarm(NVRAM);
 292         }
 293         break;
 294     case 0x1FF5:
 295         /* alarm date */
 296         tmp = from_bcd(val & 0x3F);
 297         if (tmp != 0) {
 298             NVRAM->alarm.tm_mday = tmp;
 299             NVRAM->buffer[0x1FF5] = val;
 300             set_alarm(NVRAM);
 301         }
 302         break;
 303     case 0x1FF6:
 304         /* interrupts */
 305         NVRAM->buffer[0x1FF6] = val;
 306         break;
 307     case 0x1FF7:
 308         /* watchdog */
 309         NVRAM->buffer[0x1FF7] = val;
 310         set_up_watchdog(NVRAM, val);
 311         break;
 312     case 0x1FF8:
 313     case 0x07F8:
 314         /* control */
 315        NVRAM->buffer[addr] = (val & ~0xA0) | 0x90;
 316         break;
 317     case 0x1FF9:
 318     case 0x07F9:
 319         /* seconds (BCD) */
 320         tmp = from_bcd(val & 0x7F);
 321         if (tmp >= 0 && tmp <= 59) {
 322             get_time(NVRAM, &tm);
 323             tm.tm_sec = tmp;
 324             set_time(NVRAM, &tm);
 325         }
 326         if ((val & 0x80) ^ (NVRAM->buffer[addr] & 0x80)) {
 327             if (val & 0x80) {
 328                 NVRAM->stop_time = time(NULL);
 329             } else {
 330                 NVRAM->time_offset += NVRAM->stop_time - time(NULL);
 331                 NVRAM->stop_time = 0;
 332             }
 333         }
 334         NVRAM->buffer[addr] = val & 0x80;
 335         break;
 336     case 0x1FFA:
 337     case 0x07FA:
 338         /* minutes (BCD) */
 339         tmp = from_bcd(val & 0x7F);
 340         if (tmp >= 0 && tmp <= 59) {
 341             get_time(NVRAM, &tm);
 342             tm.tm_min = tmp;
 343             set_time(NVRAM, &tm);
 344         }
 345         break;
 346     case 0x1FFB:
 347     case 0x07FB:
 348         /* hours (BCD) */
 349         tmp = from_bcd(val & 0x3F);
 350         if (tmp >= 0 && tmp <= 23) {
 351             get_time(NVRAM, &tm);
 352             tm.tm_hour = tmp;
 353             set_time(NVRAM, &tm);
 354         }
 355         break;
 356     case 0x1FFC:
 357     case 0x07FC:
 358         /* day of the week / century */
 359         tmp = from_bcd(val & 0x07);
 360         get_time(NVRAM, &tm);
 361         tm.tm_wday = tmp;
 362         set_time(NVRAM, &tm);
 363         NVRAM->buffer[addr] = val & 0x40;
 364         break;
 365     case 0x1FFD:
 366     case 0x07FD:
 367         /* date (BCD) */
 368        tmp = from_bcd(val & 0x3F);
 369         if (tmp != 0) {
 370             get_time(NVRAM, &tm);
 371             tm.tm_mday = tmp;
 372             set_time(NVRAM, &tm);
 373         }
 374         break;
 375     case 0x1FFE:
 376     case 0x07FE:
 377         /* month */
 378         tmp = from_bcd(val & 0x1F);
 379         if (tmp >= 1 && tmp <= 12) {
 380             get_time(NVRAM, &tm);
 381             tm.tm_mon = tmp - 1;
 382             set_time(NVRAM, &tm);
 383         }
 384         break;
 385     case 0x1FFF:
 386     case 0x07FF:
 387         /* year */
 388         tmp = from_bcd(val);
 389         if (tmp >= 0 && tmp <= 99) {
 390             get_time(NVRAM, &tm);
 391             tm.tm_year = from_bcd(val) + NVRAM->base_year - 1900;
 392             set_time(NVRAM, &tm);
 393         }
 394         break;
 395     default:
 396         /* Check lock registers state */
 397         if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
 398             break;
 399         if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
 400             break;
 401     do_write:
 402         if (addr < NVRAM->size) {
 403             NVRAM->buffer[addr] = val & 0xFF;
 404         }
 405         break;
 406     }
 407 }
 408
 409 static uint32_t m48t59_read(M48t59State *NVRAM, uint32_t addr)
 410 {
 411     struct tm tm;
 412     uint32_t retval = 0xFF;
 413
 414     /* check for NVRAM access */
 415     if ((NVRAM->model == 2 && addr < 0x078f) ||
 416         (NVRAM->model == 8 && addr < 0x1ff8) ||
 417         (NVRAM->model == 59 && addr < 0x1ff0)) {
 418         goto do_read;
 419     }
 420
 421     /* TOD access */
 422     switch (addr) {
 423     case 0x1FF0:
 424         /* flags register */
 425         goto do_read;
 426     case 0x1FF1:
 427         /* unused */
 428         retval = 0;
 429         break;
 430     case 0x1FF2:
 431         /* alarm seconds */
 432         goto do_read;
 433     case 0x1FF3:
 434         /* alarm minutes */
 435         goto do_read;
 436     case 0x1FF4:
 437         /* alarm hours */
 438         goto do_read;
 439     case 0x1FF5:
 440         /* alarm date */
 441         goto do_read;
 442     case 0x1FF6:
 443         /* interrupts */
 444         goto do_read;
 445     case 0x1FF7:
 446         /* A read resets the watchdog */
 447         set_up_watchdog(NVRAM, NVRAM->buffer[0x1FF7]);
 448         goto do_read;
 449     case 0x1FF8:
 450     case 0x07F8:
 451         /* control */
 452         goto do_read;
 453     case 0x1FF9:
 454     case 0x07F9:
 455         /* seconds (BCD) */
 456         get_time(NVRAM, &tm);
 457         retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec);
 458         break;
 459     case 0x1FFA:
 460     case 0x07FA:
 461         /* minutes (BCD) */
 462         get_time(NVRAM, &tm);
 463         retval = to_bcd(tm.tm_min);
 464         break;
 465     case 0x1FFB:
 466     case 0x07FB:
 467         /* hours (BCD) */
 468         get_time(NVRAM, &tm);
 469         retval = to_bcd(tm.tm_hour);
 470         break;
 471     case 0x1FFC:
 472     case 0x07FC:
 473         /* day of the week / century */
 474         get_time(NVRAM, &tm);
 475         retval = NVRAM->buffer[addr] | tm.tm_wday;
 476         break;
 477     case 0x1FFD:
 478     case 0x07FD:
 479         /* date */
 480         get_time(NVRAM, &tm);
 481         retval = to_bcd(tm.tm_mday);
 482         break;
 483     case 0x1FFE:
 484     case 0x07FE:
 485         /* month */
 486         get_time(NVRAM, &tm);
 487         retval = to_bcd(tm.tm_mon + 1);
 488         break;
 489     case 0x1FFF:
 490     case 0x07FF:
 491         /* year */
 492         get_time(NVRAM, &tm);
 493         retval = to_bcd((tm.tm_year + 1900 - NVRAM->base_year) % 100);
 494         break;
 495     default:
 496         /* Check lock registers state */
 497         if (addr >= 0x20 && addr <= 0x2F && (NVRAM->lock & 1))
 498             break;
 499         if (addr >= 0x30 && addr <= 0x3F && (NVRAM->lock & 2))
 500             break;
 501     do_read:
 502         if (addr < NVRAM->size) {
 503             retval = NVRAM->buffer[addr];
 504         }
 505         break;
 506     }
 507     if (addr > 0x1FF9 && addr < 0x2000)
 508        NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
 509
 510     return retval;
 511 }
 512
 513 static void m48t59_toggle_lock(M48t59State *NVRAM, int lock)
 514 {
 515     NVRAM->lock ^= 1 << lock;
 516 }
 517
 518 /* IO access to NVRAM */
 519 static void NVRAM_writeb(void *opaque, hwaddr addr, uint64_t val,
 520                          unsigned size)
 521 {
 522     M48t59State *NVRAM = opaque;
 523
 524     NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
 525     switch (addr) {
 526     case 0:
 527         NVRAM->addr &= ~0x00FF;
 528         NVRAM->addr |= val;
 529         break;
 530     case 1:
 531         NVRAM->addr &= ~0xFF00;
 532         NVRAM->addr |= val << 8;
 533         break;
 534     case 3:
 535         m48t59_write(NVRAM, NVRAM->addr, val);
 536         NVRAM->addr = 0x0000;
 537         break;
 538     default:
 539         break;
 540     }
 541 }
 542
 543 static uint64_t NVRAM_readb(void *opaque, hwaddr addr, unsigned size)
 544 {
 545     M48t59State *NVRAM = opaque;
 546     uint32_t retval;
 547
 548     switch (addr) {
 549     case 3:
 550         retval = m48t59_read(NVRAM, NVRAM->addr);
 551         break;
 552     default:
 553         retval = -1;
 554         break;
 555     }
 556     NVRAM_PRINTF("%s: 0x%08x <= 0x%08x\n", __func__, addr, retval);
 557
 558     return retval;
 559 }
 560
 561 static void nvram_writeb (void *opaque, hwaddr addr, uint32_t value)
 562 {
 563     M48t59State *NVRAM = opaque;
 564
 565     m48t59_write(NVRAM, addr, value & 0xff);
 566 }
 567
 568 static void nvram_writew (void *opaque, hwaddr addr, uint32_t value)
 569 {
 570     M48t59State *NVRAM = opaque;
 571
 572     m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
 573     m48t59_write(NVRAM, addr + 1, value & 0xff);
 574 }
 575
 576 static void nvram_writel (void *opaque, hwaddr addr, uint32_t value)
 577 {
 578     M48t59State *NVRAM = opaque;
 579
 580     m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
 581     m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
 582     m48t59_write(NVRAM, addr + 2, (value >> 8) & 0xff);
 583     m48t59_write(NVRAM, addr + 3, value & 0xff);
 584 }
 585
 586 static uint32_t nvram_readb (void *opaque, hwaddr addr)
 587 {
 588     M48t59State *NVRAM = opaque;
 589     uint32_t retval;
 590
 591     retval = m48t59_read(NVRAM, addr);
 592     return retval;
 593 }
 594
 595 static uint32_t nvram_readw (void *opaque, hwaddr addr)
 596 {
 597     M48t59State *NVRAM = opaque;
 598     uint32_t retval;
 599
 600     retval = m48t59_read(NVRAM, addr) << 8;
 601     retval |= m48t59_read(NVRAM, addr + 1);
 602     return retval;
 603 }
 604
 605 static uint32_t nvram_readl (void *opaque, hwaddr addr)
 606 {
 607     M48t59State *NVRAM = opaque;
 608     uint32_t retval;
 609
 610     retval = m48t59_read(NVRAM, addr) << 24;
 611     retval |= m48t59_read(NVRAM, addr + 1) << 16;
 612     retval |= m48t59_read(NVRAM, addr + 2) << 8;
 613     retval |= m48t59_read(NVRAM, addr + 3);
 614     return retval;
 615 }
 616
 617 static const MemoryRegionOps nvram_ops = {
 618     .old_mmio = {
 619         .read = { nvram_readb, nvram_readw, nvram_readl, },
 620         .write = { nvram_writeb, nvram_writew, nvram_writel, },
 621     },
 622     .endianness = DEVICE_NATIVE_ENDIAN,
 623 };
 624
 625 static const VMStateDescription vmstate_m48t59 = {
 626     .name = "m48t59",
 627     .version_id = 1,
 628     .minimum_version_id = 1,
 629     .fields = (VMStateField[]) {
 630         VMSTATE_UINT8(lock, M48t59State),
 631         VMSTATE_UINT16(addr, M48t59State),
 632         VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, 0, size),
 633         VMSTATE_END_OF_LIST()
 634     }
 635 };
 636
 637 static void m48t59_reset_common(M48t59State *NVRAM)
 638 {
 639     NVRAM->addr = 0;
 640     NVRAM->lock = 0;
 641     if (NVRAM->alrm_timer != NULL)
 642         timer_del(NVRAM->alrm_timer);
 643
 644     if (NVRAM->wd_timer != NULL)
 645         timer_del(NVRAM->wd_timer);
 646 }
 647
 648 static void m48t59_reset_isa(DeviceState *d)
 649 {
 650     M48txxISAState *isa = M48TXX_ISA(d);
 651     M48t59State *NVRAM = &isa->state;
 652
 653     m48t59_reset_common(NVRAM);
 654 }
 655
 656 static void m48t59_reset_sysbus(DeviceState *d)
 657 {
 658     M48txxSysBusState *sys = M48TXX_SYS_BUS(d);
 659     M48t59State *NVRAM = &sys->state;
 660
 661     m48t59_reset_common(NVRAM);
 662 }
 663
 664 static const MemoryRegionOps m48t59_io_ops = {
 665     .read = NVRAM_readb,
 666     .write = NVRAM_writeb,
 667     .impl = {
 668         .min_access_size = 1,
 669         .max_access_size = 1,
 670     },
 671     .endianness = DEVICE_LITTLE_ENDIAN,
 672 };
 673
 674 /* Initialisation routine */
 675 Nvram *m48t59_init(qemu_irq IRQ, hwaddr mem_base,
 676                    uint32_t io_base, uint16_t size, int base_year,
 677                    int model)
 678 {
 679     DeviceState *dev;
 680     SysBusDevice *s;
 681     int i;
 682
 683     for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
 684         if (!m48txx_info[i].sysbus_name ||
 685             m48txx_info[i].size != size ||
 686             m48txx_info[i].model != model) {
 687             continue;
 688         }
 689
 690         dev = qdev_create(NULL, m48txx_info[i].sysbus_name);
 691         qdev_prop_set_int32(dev, "base-year", base_year);
 692         qdev_init_nofail(dev);
 693         s = SYS_BUS_DEVICE(dev);
 694         sysbus_connect_irq(s, 0, IRQ);
 695         if (io_base != 0) {
 696             memory_region_add_subregion(get_system_io(), io_base,
 697                                         sysbus_mmio_get_region(s, 1));
 698         }
 699         if (mem_base != 0) {
 700             sysbus_mmio_map(s, 0, mem_base);
 701         }
 702
 703         return NVRAM(s);
 704     }
 705
 706     assert(false);
 707     return NULL;
 708 }
 709
 710 Nvram *m48t59_init_isa(ISABus *bus, uint32_t io_base, uint16_t size,
 711                        int base_year, int model)
 712 {
 713     DeviceState *dev;
 714     int i;
 715
 716     for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
 717         if (!m48txx_info[i].isa_name ||
 718             m48txx_info[i].size != size ||
 719             m48txx_info[i].model != model) {
 720             continue;
 721         }
 722
 723         dev = DEVICE(isa_create(bus, m48txx_info[i].isa_name));
 724         qdev_prop_set_uint32(dev, "iobase", io_base);
 725         qdev_prop_set_int32(dev, "base-year", base_year);
 726         qdev_init_nofail(dev);
 727         return NVRAM(dev);
 728     }
 729
 730     assert(false);
 731     return NULL;
 732 }
 733
 734 static void m48t59_realize_common(M48t59State *s, Error **errp)
 735 {
 736     s->buffer = g_malloc0(s->size);
 737     if (s->model == 59) {
 738         s->alrm_timer = timer_new_ns(rtc_clock, &alarm_cb, s);
 739         s->wd_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &watchdog_cb, s);
 740     }
 741     qemu_get_timedate(&s->alarm, 0);
 742
 743     vmstate_register(NULL, -1, &vmstate_m48t59, s);
 744 }
 745
 746 static void m48t59_isa_realize(DeviceState *dev, Error **errp)
 747 {
 748     M48txxISADeviceClass *u = M48TXX_ISA_GET_CLASS(dev);
 749     ISADevice *isadev = ISA_DEVICE(dev);
 750     M48txxISAState *d = M48TXX_ISA(dev);
 751     M48t59State *s = &d->state;
 752
 753     s->model = u->info.model;
 754     s->size = u->info.size;
 755     isa_init_irq(isadev, &s->IRQ, 8);
 756     m48t59_realize_common(s, errp);
 757     memory_region_init_io(&d->io, OBJECT(dev), &m48t59_io_ops, s, "m48t59", 4);
 758     if (d->io_base != 0) {
 759         isa_register_ioport(isadev, &d->io, d->io_base);
 760     }
 761 }
 762
 763 static int m48t59_init1(SysBusDevice *dev)
 764 {
 765     M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_GET_CLASS(dev);
 766     M48txxSysBusState *d = M48TXX_SYS_BUS(dev);
 767     Object *o = OBJECT(dev);
 768     M48t59State *s = &d->state;
 769     Error *err = NULL;
 770
 771     s->model = u->info.model;
 772     s->size = u->info.size;
 773     sysbus_init_irq(dev, &s->IRQ);
 774
 775     memory_region_init_io(&s->iomem, o, &nvram_ops, s, "m48t59.nvram",
 776                           s->size);
 777     memory_region_init_io(&d->io, o, &m48t59_io_ops, s, "m48t59", 4);
 778     sysbus_init_mmio(dev, &s->iomem);
 779     sysbus_init_mmio(dev, &d->io);
 780     m48t59_realize_common(s, &err);
 781     if (err != NULL) {
 782         error_free(err);
 783         return -1;
 784     }
 785
 786     return 0;
 787 }
 788
 789 static uint32_t m48txx_isa_read(Nvram *obj, uint32_t addr)
 790 {
 791     M48txxISAState *d = M48TXX_ISA(obj);
 792     return m48t59_read(&d->state, addr);
 793 }
 794
 795 static void m48txx_isa_write(Nvram *obj, uint32_t addr, uint32_t val)
 796 {
 797     M48txxISAState *d = M48TXX_ISA(obj);
 798     m48t59_write(&d->state, addr, val);
 799 }
 800
 801 static void m48txx_isa_toggle_lock(Nvram *obj, int lock)
 802 {
 803     M48txxISAState *d = M48TXX_ISA(obj);
 804     m48t59_toggle_lock(&d->state, lock);
 805 }
 806
 807 static Property m48t59_isa_properties[] = {
 808     DEFINE_PROP_INT32("base-year", M48txxISAState, state.base_year, 0),
 809     DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74),
 810     DEFINE_PROP_END_OF_LIST(),
 811 };
 812
 813 static void m48txx_isa_class_init(ObjectClass *klass, void *data)
 814 {
 815     DeviceClass *dc = DEVICE_CLASS(klass);
 816     NvramClass *nc = NVRAM_CLASS(klass);
 817
 818     dc->realize = m48t59_isa_realize;
 819     dc->reset = m48t59_reset_isa;
 820     dc->props = m48t59_isa_properties;
 821     nc->read = m48txx_isa_read;
 822     nc->write = m48txx_isa_write;
 823     nc->toggle_lock = m48txx_isa_toggle_lock;
 824 }
 825
 826 static void m48txx_isa_concrete_class_init(ObjectClass *klass, void *data)
 827 {
 828     M48txxISADeviceClass *u = M48TXX_ISA_CLASS(klass);
 829     M48txxInfo *info = data;
 830
 831     u->info = *info;
 832 }
 833
 834 static uint32_t m48txx_sysbus_read(Nvram *obj, uint32_t addr)
 835 {
 836     M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
 837     return m48t59_read(&d->state, addr);
 838 }
 839
 840 static void m48txx_sysbus_write(Nvram *obj, uint32_t addr, uint32_t val)
 841 {
 842     M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
 843     m48t59_write(&d->state, addr, val);
 844 }
 845
 846 static void m48txx_sysbus_toggle_lock(Nvram *obj, int lock)
 847 {
 848     M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
 849     m48t59_toggle_lock(&d->state, lock);
 850 }
 851
 852 static Property m48t59_sysbus_properties[] = {
 853     DEFINE_PROP_INT32("base-year", M48txxSysBusState, state.base_year, 0),
 854     DEFINE_PROP_END_OF_LIST(),
 855 };
 856
 857 static void m48txx_sysbus_class_init(ObjectClass *klass, void *data)
 858 {
 859     DeviceClass *dc = DEVICE_CLASS(klass);
 860     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 861     NvramClass *nc = NVRAM_CLASS(klass);
 862
 863     k->init = m48t59_init1;
 864     dc->reset = m48t59_reset_sysbus;
 865     dc->props = m48t59_sysbus_properties;
 866     nc->read = m48txx_sysbus_read;
 867     nc->write = m48txx_sysbus_write;
 868     nc->toggle_lock = m48txx_sysbus_toggle_lock;
 869 }
 870
 871 static void m48txx_sysbus_concrete_class_init(ObjectClass *klass, void *data)
 872 {
 873     M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_CLASS(klass);
 874     M48txxInfo *info = data;
 875
 876     u->info = *info;
 877 }
 878
 879 static const TypeInfo nvram_info = {
 880     .name = TYPE_NVRAM,
 881     .parent = TYPE_INTERFACE,
 882     .class_size = sizeof(NvramClass),
 883 };
 884
 885 static const TypeInfo m48txx_sysbus_type_info = {
 886     .name = TYPE_M48TXX_SYS_BUS,
 887     .parent = TYPE_SYS_BUS_DEVICE,
 888     .instance_size = sizeof(M48txxSysBusState),
 889     .abstract = true,
 890     .class_init = m48txx_sysbus_class_init,
 891     .interfaces = (InterfaceInfo[]) {
 892         { TYPE_NVRAM },
 893         { }
 894     }
 895 };
 896
 897 static const TypeInfo m48txx_isa_type_info = {
 898     .name = TYPE_M48TXX_ISA,
 899     .parent = TYPE_ISA_DEVICE,
 900     .instance_size = sizeof(M48txxISAState),
 901     .abstract = true,
 902     .class_init = m48txx_isa_class_init,
 903     .interfaces = (InterfaceInfo[]) {
 904         { TYPE_NVRAM },
 905         { }
 906     }
 907 };
 908
 909 static void m48t59_register_types(void)
 910 {
 911     TypeInfo sysbus_type_info = {
 912         .parent = TYPE_M48TXX_SYS_BUS,
 913         .class_size = sizeof(M48txxSysBusDeviceClass),
 914         .class_init = m48txx_sysbus_concrete_class_init,
 915     };
 916     TypeInfo isa_type_info = {
 917         .parent = TYPE_M48TXX_ISA,
 918         .class_size = sizeof(M48txxISADeviceClass),
 919         .class_init = m48txx_isa_concrete_class_init,
 920     };
 921     int i;
 922
 923     type_register_static(&nvram_info);
 924     type_register_static(&m48txx_sysbus_type_info);
 925     type_register_static(&m48txx_isa_type_info);
 926
 927     for (i = 0; i < ARRAY_SIZE(m48txx_info); i++) {
 928         if (m48txx_info[i].sysbus_name) {
 929             sysbus_type_info.name = m48txx_info[i].sysbus_name;
 930             sysbus_type_info.class_data = &m48txx_info[i];
 931             type_register(&sysbus_type_info);
 932         }
 933
 934         if (m48txx_info[i].isa_name) {
 935             isa_type_info.name = m48txx_info[i].isa_name;
 936             isa_type_info.class_data = &m48txx_info[i];
 937             type_register(&isa_type_info);
 938         }
 939     }
 940 }
 941
 942 type_init(m48t59_register_types)