2 * QEMU model of the Milkymist System Controller.
4 * Copyright (c) 2010-2012 Michael Walle <michael@walle.cc>
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 * Specification available at:
21 * http://milkymist.walle.cc/socdoc/sysctl.pdf
24 #include "qemu/osdep.h"
26 #include "hw/sysbus.h"
27 #include "migration/vmstate.h"
28 #include "sysemu/sysemu.h"
30 #include "qemu/timer.h"
31 #include "hw/ptimer.h"
32 #include "qemu/error-report.h"
33 #include "qemu/main-loop.h"
34 #include "qemu/module.h"
38 CTRL_AUTORESTART
= (1<<1),
56 R_DBG_SCRATCHPAD
= 20,
64 #define TYPE_MILKYMIST_SYSCTL "milkymist-sysctl"
65 #define MILKYMIST_SYSCTL(obj) \
66 OBJECT_CHECK(MilkymistSysctlState, (obj), TYPE_MILKYMIST_SYSCTL)
68 struct MilkymistSysctlState
{
69 SysBusDevice parent_obj
;
71 MemoryRegion regs_region
;
75 ptimer_state
*ptimer0
;
76 ptimer_state
*ptimer1
;
79 uint32_t capabilities
;
89 typedef struct MilkymistSysctlState MilkymistSysctlState
;
91 static void sysctl_icap_write(MilkymistSysctlState
*s
, uint32_t value
)
93 trace_milkymist_sysctl_icap_write(value
);
94 switch (value
& 0xffff) {
96 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN
);
101 static uint64_t sysctl_read(void *opaque
, hwaddr addr
,
104 MilkymistSysctlState
*s
= opaque
;
109 case R_TIMER0_COUNTER
:
110 r
= (uint32_t)ptimer_get_count(s
->ptimer0
);
111 /* milkymist timer counts up */
112 r
= s
->regs
[R_TIMER0_COMPARE
] - r
;
114 case R_TIMER1_COUNTER
:
115 r
= (uint32_t)ptimer_get_count(s
->ptimer1
);
116 /* milkymist timer counts up */
117 r
= s
->regs
[R_TIMER1_COMPARE
] - r
;
122 case R_TIMER0_CONTROL
:
123 case R_TIMER0_COMPARE
:
124 case R_TIMER1_CONTROL
:
125 case R_TIMER1_COMPARE
:
127 case R_DBG_SCRATCHPAD
:
128 case R_DBG_WRITE_LOCK
:
129 case R_CLK_FREQUENCY
:
136 error_report("milkymist_sysctl: read access to unknown register 0x"
137 TARGET_FMT_plx
, addr
<< 2);
141 trace_milkymist_sysctl_memory_read(addr
<< 2, r
);
146 static void sysctl_write(void *opaque
, hwaddr addr
, uint64_t value
,
149 MilkymistSysctlState
*s
= opaque
;
151 trace_milkymist_sysctl_memory_write(addr
, value
);
157 case R_TIMER0_COUNTER
:
158 case R_TIMER1_COUNTER
:
159 case R_DBG_SCRATCHPAD
:
160 s
->regs
[addr
] = value
;
162 case R_TIMER0_COMPARE
:
163 ptimer_set_limit(s
->ptimer0
, value
, 0);
164 s
->regs
[addr
] = value
;
166 case R_TIMER1_COMPARE
:
167 ptimer_set_limit(s
->ptimer1
, value
, 0);
168 s
->regs
[addr
] = value
;
170 case R_TIMER0_CONTROL
:
171 s
->regs
[addr
] = value
;
172 if (s
->regs
[R_TIMER0_CONTROL
] & CTRL_ENABLE
) {
173 trace_milkymist_sysctl_start_timer0();
174 ptimer_set_count(s
->ptimer0
,
175 s
->regs
[R_TIMER0_COMPARE
] - s
->regs
[R_TIMER0_COUNTER
]);
176 ptimer_run(s
->ptimer0
, 0);
178 trace_milkymist_sysctl_stop_timer0();
179 ptimer_stop(s
->ptimer0
);
182 case R_TIMER1_CONTROL
:
183 s
->regs
[addr
] = value
;
184 if (s
->regs
[R_TIMER1_CONTROL
] & CTRL_ENABLE
) {
185 trace_milkymist_sysctl_start_timer1();
186 ptimer_set_count(s
->ptimer1
,
187 s
->regs
[R_TIMER1_COMPARE
] - s
->regs
[R_TIMER1_COUNTER
]);
188 ptimer_run(s
->ptimer1
, 0);
190 trace_milkymist_sysctl_stop_timer1();
191 ptimer_stop(s
->ptimer1
);
195 sysctl_icap_write(s
, value
);
197 case R_DBG_WRITE_LOCK
:
201 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
205 case R_CLK_FREQUENCY
:
207 error_report("milkymist_sysctl: write to read-only register 0x"
208 TARGET_FMT_plx
, addr
<< 2);
212 error_report("milkymist_sysctl: write access to unknown register 0x"
213 TARGET_FMT_plx
, addr
<< 2);
218 static const MemoryRegionOps sysctl_mmio_ops
= {
220 .write
= sysctl_write
,
222 .min_access_size
= 4,
223 .max_access_size
= 4,
225 .endianness
= DEVICE_NATIVE_ENDIAN
,
228 static void timer0_hit(void *opaque
)
230 MilkymistSysctlState
*s
= opaque
;
232 if (!(s
->regs
[R_TIMER0_CONTROL
] & CTRL_AUTORESTART
)) {
233 s
->regs
[R_TIMER0_CONTROL
] &= ~CTRL_ENABLE
;
234 trace_milkymist_sysctl_stop_timer0();
235 ptimer_stop(s
->ptimer0
);
238 trace_milkymist_sysctl_pulse_irq_timer0();
239 qemu_irq_pulse(s
->timer0_irq
);
242 static void timer1_hit(void *opaque
)
244 MilkymistSysctlState
*s
= opaque
;
246 if (!(s
->regs
[R_TIMER1_CONTROL
] & CTRL_AUTORESTART
)) {
247 s
->regs
[R_TIMER1_CONTROL
] &= ~CTRL_ENABLE
;
248 trace_milkymist_sysctl_stop_timer1();
249 ptimer_stop(s
->ptimer1
);
252 trace_milkymist_sysctl_pulse_irq_timer1();
253 qemu_irq_pulse(s
->timer1_irq
);
256 static void milkymist_sysctl_reset(DeviceState
*d
)
258 MilkymistSysctlState
*s
= MILKYMIST_SYSCTL(d
);
261 for (i
= 0; i
< R_MAX
; i
++) {
265 ptimer_stop(s
->ptimer0
);
266 ptimer_stop(s
->ptimer1
);
269 s
->regs
[R_ICAP
] = ICAP_READY
;
270 s
->regs
[R_SYSTEM_ID
] = s
->systemid
;
271 s
->regs
[R_CLK_FREQUENCY
] = s
->freq_hz
;
272 s
->regs
[R_CAPABILITIES
] = s
->capabilities
;
273 s
->regs
[R_GPIO_IN
] = s
->strappings
;
276 static void milkymist_sysctl_init(Object
*obj
)
278 MilkymistSysctlState
*s
= MILKYMIST_SYSCTL(obj
);
279 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
281 sysbus_init_irq(dev
, &s
->gpio_irq
);
282 sysbus_init_irq(dev
, &s
->timer0_irq
);
283 sysbus_init_irq(dev
, &s
->timer1_irq
);
285 s
->bh0
= qemu_bh_new(timer0_hit
, s
);
286 s
->bh1
= qemu_bh_new(timer1_hit
, s
);
287 s
->ptimer0
= ptimer_init(s
->bh0
, PTIMER_POLICY_DEFAULT
);
288 s
->ptimer1
= ptimer_init(s
->bh1
, PTIMER_POLICY_DEFAULT
);
290 memory_region_init_io(&s
->regs_region
, obj
, &sysctl_mmio_ops
, s
,
291 "milkymist-sysctl", R_MAX
* 4);
292 sysbus_init_mmio(dev
, &s
->regs_region
);
295 static void milkymist_sysctl_realize(DeviceState
*dev
, Error
**errp
)
297 MilkymistSysctlState
*s
= MILKYMIST_SYSCTL(dev
);
299 ptimer_set_freq(s
->ptimer0
, s
->freq_hz
);
300 ptimer_set_freq(s
->ptimer1
, s
->freq_hz
);
303 static const VMStateDescription vmstate_milkymist_sysctl
= {
304 .name
= "milkymist-sysctl",
306 .minimum_version_id
= 1,
307 .fields
= (VMStateField
[]) {
308 VMSTATE_UINT32_ARRAY(regs
, MilkymistSysctlState
, R_MAX
),
309 VMSTATE_PTIMER(ptimer0
, MilkymistSysctlState
),
310 VMSTATE_PTIMER(ptimer1
, MilkymistSysctlState
),
311 VMSTATE_END_OF_LIST()
315 static Property milkymist_sysctl_properties
[] = {
316 DEFINE_PROP_UINT32("frequency", MilkymistSysctlState
,
318 DEFINE_PROP_UINT32("capabilities", MilkymistSysctlState
,
319 capabilities
, 0x00000000),
320 DEFINE_PROP_UINT32("systemid", MilkymistSysctlState
,
321 systemid
, 0x10014d31),
322 DEFINE_PROP_UINT32("gpio_strappings", MilkymistSysctlState
,
323 strappings
, 0x00000001),
324 DEFINE_PROP_END_OF_LIST(),
327 static void milkymist_sysctl_class_init(ObjectClass
*klass
, void *data
)
329 DeviceClass
*dc
= DEVICE_CLASS(klass
);
331 dc
->realize
= milkymist_sysctl_realize
;
332 dc
->reset
= milkymist_sysctl_reset
;
333 dc
->vmsd
= &vmstate_milkymist_sysctl
;
334 dc
->props
= milkymist_sysctl_properties
;
337 static const TypeInfo milkymist_sysctl_info
= {
338 .name
= TYPE_MILKYMIST_SYSCTL
,
339 .parent
= TYPE_SYS_BUS_DEVICE
,
340 .instance_size
= sizeof(MilkymistSysctlState
),
341 .instance_init
= milkymist_sysctl_init
,
342 .class_init
= milkymist_sysctl_class_init
,
345 static void milkymist_sysctl_register_types(void)
347 type_register_static(&milkymist_sysctl_info
);
350 type_init(milkymist_sysctl_register_types
)