2 * Nuvoton NPCM7xx Timer Controller
4 * Copyright 2020 Google LLC
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 #include "qemu/osdep.h"
20 #include "hw/qdev-properties.h"
21 #include "hw/misc/npcm7xx_clk.h"
22 #include "hw/timer/npcm7xx_timer.h"
23 #include "migration/vmstate.h"
24 #include "qemu/bitops.h"
25 #include "qemu/error-report.h"
27 #include "qemu/module.h"
28 #include "qemu/timer.h"
29 #include "qemu/units.h"
32 /* 32-bit register indices. */
33 enum NPCM7xxTimerRegisters
{
48 NPCM7XX_TIMER_TCSR4
= 0x0040 / sizeof(uint32_t),
49 NPCM7XX_TIMER_TICR4
= 0x0048 / sizeof(uint32_t),
50 NPCM7XX_TIMER_TDR4
= 0x0050 / sizeof(uint32_t),
51 NPCM7XX_TIMER_REGS_END
,
54 /* Register field definitions. */
55 #define NPCM7XX_TCSR_CEN BIT(30)
56 #define NPCM7XX_TCSR_IE BIT(29)
57 #define NPCM7XX_TCSR_PERIODIC BIT(27)
58 #define NPCM7XX_TCSR_CRST BIT(26)
59 #define NPCM7XX_TCSR_CACT BIT(25)
60 #define NPCM7XX_TCSR_RSVD 0x01ffff00
61 #define NPCM7XX_TCSR_PRESCALE_START 0
62 #define NPCM7XX_TCSR_PRESCALE_LEN 8
64 #define NPCM7XX_WTCR_WTCLK(rv) extract32(rv, 10, 2)
65 #define NPCM7XX_WTCR_FREEZE_EN BIT(9)
66 #define NPCM7XX_WTCR_WTE BIT(7)
67 #define NPCM7XX_WTCR_WTIE BIT(6)
68 #define NPCM7XX_WTCR_WTIS(rv) extract32(rv, 4, 2)
69 #define NPCM7XX_WTCR_WTIF BIT(3)
70 #define NPCM7XX_WTCR_WTRF BIT(2)
71 #define NPCM7XX_WTCR_WTRE BIT(1)
72 #define NPCM7XX_WTCR_WTR BIT(0)
75 * The number of clock cycles between interrupt and reset in watchdog, used
76 * by the software to handle the interrupt before system is reset.
78 #define NPCM7XX_WATCHDOG_INTERRUPT_TO_RESET_CYCLES 1024
80 /* Start or resume the timer. */
81 static void npcm7xx_timer_start(NPCM7xxBaseTimer
*t
)
85 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
86 t
->expires_ns
= now
+ t
->remaining_ns
;
87 timer_mod(&t
->qtimer
, t
->expires_ns
);
90 /* Stop counting. Record the time remaining so we can continue later. */
91 static void npcm7xx_timer_pause(NPCM7xxBaseTimer
*t
)
95 timer_del(&t
->qtimer
);
96 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
97 t
->remaining_ns
= t
->expires_ns
- now
;
100 /* Delete the timer and reset it to default state. */
101 static void npcm7xx_timer_clear(NPCM7xxBaseTimer
*t
)
103 timer_del(&t
->qtimer
);
109 * Returns the index of timer in the tc->timer array. This can be used to
110 * locate the registers that belong to this timer.
112 static int npcm7xx_timer_index(NPCM7xxTimerCtrlState
*tc
, NPCM7xxTimer
*timer
)
114 int index
= timer
- tc
->timer
;
116 g_assert(index
>= 0 && index
< NPCM7XX_TIMERS_PER_CTRL
);
121 /* Return the value by which to divide the reference clock rate. */
122 static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr
)
124 return extract32(tcsr
, NPCM7XX_TCSR_PRESCALE_START
,
125 NPCM7XX_TCSR_PRESCALE_LEN
) + 1;
128 /* Convert a timer cycle count to a time interval in nanoseconds. */
129 static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer
*t
, uint32_t count
)
133 ns
*= NANOSECONDS_PER_SECOND
/ NPCM7XX_TIMER_REF_HZ
;
134 ns
*= npcm7xx_tcsr_prescaler(t
->tcsr
);
139 /* Convert a time interval in nanoseconds to a timer cycle count. */
140 static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer
*t
, int64_t ns
)
144 count
= ns
/ (NANOSECONDS_PER_SECOND
/ NPCM7XX_TIMER_REF_HZ
);
145 count
/= npcm7xx_tcsr_prescaler(t
->tcsr
);
150 static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer
*t
)
152 switch (NPCM7XX_WTCR_WTCLK(t
->wtcr
)) {
162 g_assert_not_reached();
166 static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer
*t
,
169 uint32_t prescaler
= npcm7xx_watchdog_timer_prescaler(t
);
170 int64_t ns
= (NANOSECONDS_PER_SECOND
/ NPCM7XX_TIMER_REF_HZ
) * cycles
;
173 * The reset function always clears the current timer. The caller of the
174 * this needs to decide whether to start the watchdog timer based on
175 * specific flag in WTCR.
177 npcm7xx_timer_clear(&t
->base_timer
);
180 t
->base_timer
.remaining_ns
= ns
;
183 static void npcm7xx_watchdog_timer_reset(NPCM7xxWatchdogTimer
*t
)
186 uint32_t s
= NPCM7XX_WTCR_WTIS(t
->wtcr
);
190 cycles
<<= NPCM7XX_WATCHDOG_BASETIME_SHIFT
;
193 npcm7xx_watchdog_timer_reset_cycles(t
, cycles
);
197 * Raise the interrupt line if there's a pending interrupt and interrupts are
198 * enabled for this timer. If not, lower it.
200 static void npcm7xx_timer_check_interrupt(NPCM7xxTimer
*t
)
202 NPCM7xxTimerCtrlState
*tc
= t
->ctrl
;
203 int index
= npcm7xx_timer_index(tc
, t
);
204 bool pending
= (t
->tcsr
& NPCM7XX_TCSR_IE
) && (tc
->tisr
& BIT(index
));
206 qemu_set_irq(t
->irq
, pending
);
207 trace_npcm7xx_timer_irq(DEVICE(tc
)->canonical_path
, index
, pending
);
211 * Called when the counter reaches zero. Sets the interrupt flag, and either
212 * restarts or disables the timer.
214 static void npcm7xx_timer_reached_zero(NPCM7xxTimer
*t
)
216 NPCM7xxTimerCtrlState
*tc
= t
->ctrl
;
217 int index
= npcm7xx_timer_index(tc
, t
);
219 tc
->tisr
|= BIT(index
);
221 if (t
->tcsr
& NPCM7XX_TCSR_PERIODIC
) {
222 t
->base_timer
.remaining_ns
= npcm7xx_timer_count_to_ns(t
, t
->ticr
);
223 if (t
->tcsr
& NPCM7XX_TCSR_CEN
) {
224 npcm7xx_timer_start(&t
->base_timer
);
227 t
->tcsr
&= ~(NPCM7XX_TCSR_CEN
| NPCM7XX_TCSR_CACT
);
230 npcm7xx_timer_check_interrupt(t
);
235 * Restart the timer from its initial value. If the timer was enabled and stays
236 * enabled, adjust the QEMU timer according to the new count. If the timer is
237 * transitioning from disabled to enabled, the caller is expected to start the
240 static void npcm7xx_timer_restart(NPCM7xxTimer
*t
, uint32_t old_tcsr
)
242 t
->base_timer
.remaining_ns
= npcm7xx_timer_count_to_ns(t
, t
->ticr
);
244 if (old_tcsr
& t
->tcsr
& NPCM7XX_TCSR_CEN
) {
245 npcm7xx_timer_start(&t
->base_timer
);
249 /* Register read and write handlers */
251 static uint32_t npcm7xx_timer_read_tdr(NPCM7xxTimer
*t
)
253 if (t
->tcsr
& NPCM7XX_TCSR_CEN
) {
254 int64_t now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
256 return npcm7xx_timer_ns_to_count(t
, t
->base_timer
.expires_ns
- now
);
259 return npcm7xx_timer_ns_to_count(t
, t
->base_timer
.remaining_ns
);
262 static void npcm7xx_timer_write_tcsr(NPCM7xxTimer
*t
, uint32_t new_tcsr
)
264 uint32_t old_tcsr
= t
->tcsr
;
267 if (new_tcsr
& NPCM7XX_TCSR_RSVD
) {
268 qemu_log_mask(LOG_GUEST_ERROR
, "%s: reserved bits in 0x%08x ignored\n",
270 new_tcsr
&= ~NPCM7XX_TCSR_RSVD
;
272 if (new_tcsr
& NPCM7XX_TCSR_CACT
) {
273 qemu_log_mask(LOG_GUEST_ERROR
, "%s: read-only bits in 0x%08x ignored\n",
275 new_tcsr
&= ~NPCM7XX_TCSR_CACT
;
277 if ((new_tcsr
& NPCM7XX_TCSR_CRST
) && (new_tcsr
& NPCM7XX_TCSR_CEN
)) {
278 qemu_log_mask(LOG_GUEST_ERROR
,
279 "%s: both CRST and CEN set; ignoring CEN.\n",
281 new_tcsr
&= ~NPCM7XX_TCSR_CEN
;
284 /* Calculate the value of TDR before potentially changing the prescaler. */
285 tdr
= npcm7xx_timer_read_tdr(t
);
287 t
->tcsr
= (t
->tcsr
& NPCM7XX_TCSR_CACT
) | new_tcsr
;
289 if (npcm7xx_tcsr_prescaler(old_tcsr
) != npcm7xx_tcsr_prescaler(new_tcsr
)) {
290 /* Recalculate time remaining based on the current TDR value. */
291 t
->base_timer
.remaining_ns
= npcm7xx_timer_count_to_ns(t
, tdr
);
292 if (old_tcsr
& t
->tcsr
& NPCM7XX_TCSR_CEN
) {
293 npcm7xx_timer_start(&t
->base_timer
);
297 if ((old_tcsr
^ new_tcsr
) & NPCM7XX_TCSR_IE
) {
298 npcm7xx_timer_check_interrupt(t
);
300 if (new_tcsr
& NPCM7XX_TCSR_CRST
) {
301 npcm7xx_timer_restart(t
, old_tcsr
);
302 t
->tcsr
&= ~NPCM7XX_TCSR_CRST
;
304 if ((old_tcsr
^ new_tcsr
) & NPCM7XX_TCSR_CEN
) {
305 if (new_tcsr
& NPCM7XX_TCSR_CEN
) {
306 t
->tcsr
|= NPCM7XX_TCSR_CACT
;
307 npcm7xx_timer_start(&t
->base_timer
);
309 t
->tcsr
&= ~NPCM7XX_TCSR_CACT
;
310 npcm7xx_timer_pause(&t
->base_timer
);
311 if (t
->base_timer
.remaining_ns
<= 0) {
312 npcm7xx_timer_reached_zero(t
);
318 static void npcm7xx_timer_write_ticr(NPCM7xxTimer
*t
, uint32_t new_ticr
)
322 npcm7xx_timer_restart(t
, t
->tcsr
);
325 static void npcm7xx_timer_write_tisr(NPCM7xxTimerCtrlState
*s
, uint32_t value
)
330 for (i
= 0; i
< ARRAY_SIZE(s
->timer
); i
++) {
331 if (value
& (1U << i
)) {
332 npcm7xx_timer_check_interrupt(&s
->timer
[i
]);
338 static void npcm7xx_timer_write_wtcr(NPCM7xxWatchdogTimer
*t
, uint32_t new_wtcr
)
340 uint32_t old_wtcr
= t
->wtcr
;
343 * WTIF and WTRF are cleared by writing 1. Writing 0 makes these bits
346 if (new_wtcr
& NPCM7XX_WTCR_WTIF
) {
347 new_wtcr
&= ~NPCM7XX_WTCR_WTIF
;
348 } else if (old_wtcr
& NPCM7XX_WTCR_WTIF
) {
349 new_wtcr
|= NPCM7XX_WTCR_WTIF
;
351 if (new_wtcr
& NPCM7XX_WTCR_WTRF
) {
352 new_wtcr
&= ~NPCM7XX_WTCR_WTRF
;
353 } else if (old_wtcr
& NPCM7XX_WTCR_WTRF
) {
354 new_wtcr
|= NPCM7XX_WTCR_WTRF
;
359 if (new_wtcr
& NPCM7XX_WTCR_WTR
) {
360 t
->wtcr
&= ~NPCM7XX_WTCR_WTR
;
361 npcm7xx_watchdog_timer_reset(t
);
362 if (new_wtcr
& NPCM7XX_WTCR_WTE
) {
363 npcm7xx_timer_start(&t
->base_timer
);
365 } else if ((old_wtcr
^ new_wtcr
) & NPCM7XX_WTCR_WTE
) {
366 if (new_wtcr
& NPCM7XX_WTCR_WTE
) {
367 npcm7xx_timer_start(&t
->base_timer
);
369 npcm7xx_timer_pause(&t
->base_timer
);
375 static hwaddr
npcm7xx_tcsr_index(hwaddr reg
)
378 case NPCM7XX_TIMER_TCSR0
:
380 case NPCM7XX_TIMER_TCSR1
:
382 case NPCM7XX_TIMER_TCSR2
:
384 case NPCM7XX_TIMER_TCSR3
:
386 case NPCM7XX_TIMER_TCSR4
:
389 g_assert_not_reached();
393 static hwaddr
npcm7xx_ticr_index(hwaddr reg
)
396 case NPCM7XX_TIMER_TICR0
:
398 case NPCM7XX_TIMER_TICR1
:
400 case NPCM7XX_TIMER_TICR2
:
402 case NPCM7XX_TIMER_TICR3
:
404 case NPCM7XX_TIMER_TICR4
:
407 g_assert_not_reached();
411 static hwaddr
npcm7xx_tdr_index(hwaddr reg
)
414 case NPCM7XX_TIMER_TDR0
:
416 case NPCM7XX_TIMER_TDR1
:
418 case NPCM7XX_TIMER_TDR2
:
420 case NPCM7XX_TIMER_TDR3
:
422 case NPCM7XX_TIMER_TDR4
:
425 g_assert_not_reached();
429 static uint64_t npcm7xx_timer_read(void *opaque
, hwaddr offset
, unsigned size
)
431 NPCM7xxTimerCtrlState
*s
= opaque
;
435 reg
= offset
/ sizeof(uint32_t);
437 case NPCM7XX_TIMER_TCSR0
:
438 case NPCM7XX_TIMER_TCSR1
:
439 case NPCM7XX_TIMER_TCSR2
:
440 case NPCM7XX_TIMER_TCSR3
:
441 case NPCM7XX_TIMER_TCSR4
:
442 value
= s
->timer
[npcm7xx_tcsr_index(reg
)].tcsr
;
445 case NPCM7XX_TIMER_TICR0
:
446 case NPCM7XX_TIMER_TICR1
:
447 case NPCM7XX_TIMER_TICR2
:
448 case NPCM7XX_TIMER_TICR3
:
449 case NPCM7XX_TIMER_TICR4
:
450 value
= s
->timer
[npcm7xx_ticr_index(reg
)].ticr
;
453 case NPCM7XX_TIMER_TDR0
:
454 case NPCM7XX_TIMER_TDR1
:
455 case NPCM7XX_TIMER_TDR2
:
456 case NPCM7XX_TIMER_TDR3
:
457 case NPCM7XX_TIMER_TDR4
:
458 value
= npcm7xx_timer_read_tdr(&s
->timer
[npcm7xx_tdr_index(reg
)]);
461 case NPCM7XX_TIMER_TISR
:
465 case NPCM7XX_TIMER_WTCR
:
466 value
= s
->watchdog_timer
.wtcr
;
470 qemu_log_mask(LOG_GUEST_ERROR
,
471 "%s: invalid offset 0x%04" HWADDR_PRIx
"\n",
476 trace_npcm7xx_timer_read(DEVICE(s
)->canonical_path
, offset
, value
);
481 static void npcm7xx_timer_write(void *opaque
, hwaddr offset
,
482 uint64_t v
, unsigned size
)
484 uint32_t reg
= offset
/ sizeof(uint32_t);
485 NPCM7xxTimerCtrlState
*s
= opaque
;
488 trace_npcm7xx_timer_write(DEVICE(s
)->canonical_path
, offset
, value
);
491 case NPCM7XX_TIMER_TCSR0
:
492 case NPCM7XX_TIMER_TCSR1
:
493 case NPCM7XX_TIMER_TCSR2
:
494 case NPCM7XX_TIMER_TCSR3
:
495 case NPCM7XX_TIMER_TCSR4
:
496 npcm7xx_timer_write_tcsr(&s
->timer
[npcm7xx_tcsr_index(reg
)], value
);
499 case NPCM7XX_TIMER_TICR0
:
500 case NPCM7XX_TIMER_TICR1
:
501 case NPCM7XX_TIMER_TICR2
:
502 case NPCM7XX_TIMER_TICR3
:
503 case NPCM7XX_TIMER_TICR4
:
504 npcm7xx_timer_write_ticr(&s
->timer
[npcm7xx_ticr_index(reg
)], value
);
507 case NPCM7XX_TIMER_TDR0
:
508 case NPCM7XX_TIMER_TDR1
:
509 case NPCM7XX_TIMER_TDR2
:
510 case NPCM7XX_TIMER_TDR3
:
511 case NPCM7XX_TIMER_TDR4
:
512 qemu_log_mask(LOG_GUEST_ERROR
,
513 "%s: register @ 0x%04" HWADDR_PRIx
" is read-only\n",
517 case NPCM7XX_TIMER_TISR
:
518 npcm7xx_timer_write_tisr(s
, value
);
521 case NPCM7XX_TIMER_WTCR
:
522 npcm7xx_timer_write_wtcr(&s
->watchdog_timer
, value
);
526 qemu_log_mask(LOG_GUEST_ERROR
,
527 "%s: invalid offset 0x%04" HWADDR_PRIx
"\n",
531 static const struct MemoryRegionOps npcm7xx_timer_ops
= {
532 .read
= npcm7xx_timer_read
,
533 .write
= npcm7xx_timer_write
,
534 .endianness
= DEVICE_LITTLE_ENDIAN
,
536 .min_access_size
= 4,
537 .max_access_size
= 4,
542 /* Called when the QEMU timer expires. */
543 static void npcm7xx_timer_expired(void *opaque
)
545 NPCM7xxTimer
*t
= opaque
;
547 if (t
->tcsr
& NPCM7XX_TCSR_CEN
) {
548 npcm7xx_timer_reached_zero(t
);
552 static void npcm7xx_timer_enter_reset(Object
*obj
, ResetType type
)
554 NPCM7xxTimerCtrlState
*s
= NPCM7XX_TIMER(obj
);
557 for (i
= 0; i
< NPCM7XX_TIMERS_PER_CTRL
; i
++) {
558 NPCM7xxTimer
*t
= &s
->timer
[i
];
560 npcm7xx_timer_clear(&t
->base_timer
);
561 t
->tcsr
= 0x00000005;
562 t
->ticr
= 0x00000000;
565 s
->tisr
= 0x00000000;
567 * Set WTCLK to 1(default) and reset all flags except WTRF.
568 * WTRF is not reset during a core domain reset.
570 s
->watchdog_timer
.wtcr
= 0x00000400 | (s
->watchdog_timer
.wtcr
&
574 static void npcm7xx_watchdog_timer_expired(void *opaque
)
576 NPCM7xxWatchdogTimer
*t
= opaque
;
578 if (t
->wtcr
& NPCM7XX_WTCR_WTE
) {
579 if (t
->wtcr
& NPCM7XX_WTCR_WTIF
) {
580 if (t
->wtcr
& NPCM7XX_WTCR_WTRE
) {
581 t
->wtcr
|= NPCM7XX_WTCR_WTRF
;
582 /* send reset signal to CLK module*/
583 qemu_irq_raise(t
->reset_signal
);
586 t
->wtcr
|= NPCM7XX_WTCR_WTIF
;
587 if (t
->wtcr
& NPCM7XX_WTCR_WTIE
) {
589 qemu_irq_raise(t
->irq
);
591 npcm7xx_watchdog_timer_reset_cycles(t
,
592 NPCM7XX_WATCHDOG_INTERRUPT_TO_RESET_CYCLES
);
593 npcm7xx_timer_start(&t
->base_timer
);
598 static void npcm7xx_timer_hold_reset(Object
*obj
)
600 NPCM7xxTimerCtrlState
*s
= NPCM7XX_TIMER(obj
);
603 for (i
= 0; i
< NPCM7XX_TIMERS_PER_CTRL
; i
++) {
604 qemu_irq_lower(s
->timer
[i
].irq
);
606 qemu_irq_lower(s
->watchdog_timer
.irq
);
609 static void npcm7xx_timer_realize(DeviceState
*dev
, Error
**errp
)
611 NPCM7xxTimerCtrlState
*s
= NPCM7XX_TIMER(dev
);
612 SysBusDevice
*sbd
= &s
->parent
;
614 NPCM7xxWatchdogTimer
*w
;
616 for (i
= 0; i
< NPCM7XX_TIMERS_PER_CTRL
; i
++) {
617 NPCM7xxTimer
*t
= &s
->timer
[i
];
619 timer_init_ns(&t
->base_timer
.qtimer
, QEMU_CLOCK_VIRTUAL
,
620 npcm7xx_timer_expired
, t
);
621 sysbus_init_irq(sbd
, &t
->irq
);
624 w
= &s
->watchdog_timer
;
626 timer_init_ns(&w
->base_timer
.qtimer
, QEMU_CLOCK_VIRTUAL
,
627 npcm7xx_watchdog_timer_expired
, w
);
628 sysbus_init_irq(sbd
, &w
->irq
);
630 memory_region_init_io(&s
->iomem
, OBJECT(s
), &npcm7xx_timer_ops
, s
,
631 TYPE_NPCM7XX_TIMER
, 4 * KiB
);
632 sysbus_init_mmio(sbd
, &s
->iomem
);
633 qdev_init_gpio_out_named(dev
, &w
->reset_signal
,
634 NPCM7XX_WATCHDOG_RESET_GPIO_OUT
, 1);
637 static const VMStateDescription vmstate_npcm7xx_base_timer
= {
638 .name
= "npcm7xx-base-timer",
640 .minimum_version_id
= 0,
641 .fields
= (VMStateField
[]) {
642 VMSTATE_TIMER(qtimer
, NPCM7xxBaseTimer
),
643 VMSTATE_INT64(expires_ns
, NPCM7xxBaseTimer
),
644 VMSTATE_INT64(remaining_ns
, NPCM7xxBaseTimer
),
645 VMSTATE_END_OF_LIST(),
649 static const VMStateDescription vmstate_npcm7xx_timer
= {
650 .name
= "npcm7xx-timer",
652 .minimum_version_id
= 1,
653 .fields
= (VMStateField
[]) {
654 VMSTATE_STRUCT(base_timer
, NPCM7xxTimer
,
655 0, vmstate_npcm7xx_base_timer
,
657 VMSTATE_UINT32(tcsr
, NPCM7xxTimer
),
658 VMSTATE_UINT32(ticr
, NPCM7xxTimer
),
659 VMSTATE_END_OF_LIST(),
663 static const VMStateDescription vmstate_npcm7xx_watchdog_timer
= {
664 .name
= "npcm7xx-watchdog-timer",
666 .minimum_version_id
= 0,
667 .fields
= (VMStateField
[]) {
668 VMSTATE_STRUCT(base_timer
, NPCM7xxWatchdogTimer
,
669 0, vmstate_npcm7xx_base_timer
,
671 VMSTATE_UINT32(wtcr
, NPCM7xxWatchdogTimer
),
672 VMSTATE_END_OF_LIST(),
676 static const VMStateDescription vmstate_npcm7xx_timer_ctrl
= {
677 .name
= "npcm7xx-timer-ctrl",
679 .minimum_version_id
= 1,
680 .fields
= (VMStateField
[]) {
681 VMSTATE_UINT32(tisr
, NPCM7xxTimerCtrlState
),
682 VMSTATE_STRUCT_ARRAY(timer
, NPCM7xxTimerCtrlState
,
683 NPCM7XX_TIMERS_PER_CTRL
, 0, vmstate_npcm7xx_timer
,
685 VMSTATE_STRUCT(watchdog_timer
, NPCM7xxTimerCtrlState
,
686 0, vmstate_npcm7xx_watchdog_timer
,
687 NPCM7xxWatchdogTimer
),
688 VMSTATE_END_OF_LIST(),
692 static void npcm7xx_timer_class_init(ObjectClass
*klass
, void *data
)
694 ResettableClass
*rc
= RESETTABLE_CLASS(klass
);
695 DeviceClass
*dc
= DEVICE_CLASS(klass
);
697 QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END
> NPCM7XX_TIMER_NR_REGS
);
699 dc
->desc
= "NPCM7xx Timer Controller";
700 dc
->realize
= npcm7xx_timer_realize
;
701 dc
->vmsd
= &vmstate_npcm7xx_timer_ctrl
;
702 rc
->phases
.enter
= npcm7xx_timer_enter_reset
;
703 rc
->phases
.hold
= npcm7xx_timer_hold_reset
;
706 static const TypeInfo npcm7xx_timer_info
= {
707 .name
= TYPE_NPCM7XX_TIMER
,
708 .parent
= TYPE_SYS_BUS_DEVICE
,
709 .instance_size
= sizeof(NPCM7xxTimerCtrlState
),
710 .class_init
= npcm7xx_timer_class_init
,
713 static void npcm7xx_timer_register_type(void)
715 type_register_static(&npcm7xx_timer_info
);
717 type_init(npcm7xx_timer_register_type
);