2 * Intel XScale PXA255/270 OS Timers.
4 * Copyright (c) 2006 Openedhand Ltd.
5 * Copyright (c) 2006 Thorsten Zitterell
7 * This code is licensed under the GPL.
10 #include "qemu/osdep.h"
12 #include "hw/qdev-properties.h"
13 #include "qemu/timer.h"
14 #include "sysemu/runstate.h"
15 #include "hw/arm/pxa.h"
16 #include "hw/sysbus.h"
17 #include "migration/vmstate.h"
19 #include "qemu/module.h"
20 #include "qom/object.h"
34 #define OSCR 0x10 /* OS Timer Count */
43 #define OSSR 0x14 /* Timer status register */
45 #define OIER 0x1c /* Interrupt enable register 3-0 to E3-E0 */
46 #define OMCR4 0xc0 /* OS Match Control registers */
56 #define PXA25X_FREQ 3686400 /* 3.6864 MHz */
57 #define PXA27X_FREQ 3250000 /* 3.25 MHz */
59 static int pxa2xx_timer4_freq
[8] = {
65 /* [5] is the "Externally supplied clock". Assign if necessary. */
69 #define TYPE_PXA2XX_TIMER "pxa2xx-timer"
70 typedef struct PXA2xxTimerInfo PXA2xxTimerInfo
;
71 DECLARE_INSTANCE_CHECKER(PXA2xxTimerInfo
, PXA2XX_TIMER
,
80 PXA2xxTimerInfo
*info
;
92 struct PXA2xxTimerInfo
{
93 SysBusDevice parent_obj
;
102 PXA2xxTimer0 timer
[4];
104 uint32_t irq_enabled
;
112 #define PXA2XX_TIMER_HAVE_TM4 0
114 static inline int pxa2xx_timer_has_tm4(PXA2xxTimerInfo
*s
)
116 return s
->flags
& (1 << PXA2XX_TIMER_HAVE_TM4
);
119 static void pxa2xx_timer_update(void *opaque
, uint64_t now_qemu
)
121 PXA2xxTimerInfo
*s
= (PXA2xxTimerInfo
*) opaque
;
127 muldiv64(now_qemu
- s
->lastload
, s
->freq
, NANOSECONDS_PER_SECOND
);
129 for (i
= 0; i
< 4; i
++) {
130 new_qemu
= now_qemu
+ muldiv64((uint32_t) (s
->timer
[i
].value
- now_vm
),
131 NANOSECONDS_PER_SECOND
, s
->freq
);
132 timer_mod(s
->timer
[i
].qtimer
, new_qemu
);
136 static void pxa2xx_timer_update4(void *opaque
, uint64_t now_qemu
, int n
)
138 PXA2xxTimerInfo
*s
= (PXA2xxTimerInfo
*) opaque
;
141 static const int counters
[8] = { 0, 0, 0, 0, 4, 4, 6, 6 };
144 assert(n
< ARRAY_SIZE(counters
));
145 if (s
->tm4
[n
].control
& (1 << 7))
148 counter
= counters
[n
];
150 if (!s
->tm4
[counter
].freq
) {
151 timer_del(s
->tm4
[n
].tm
.qtimer
);
155 now_vm
= s
->tm4
[counter
].clock
+ muldiv64(now_qemu
-
156 s
->tm4
[counter
].lastload
,
157 s
->tm4
[counter
].freq
, NANOSECONDS_PER_SECOND
);
159 new_qemu
= now_qemu
+ muldiv64((uint32_t) (s
->tm4
[n
].tm
.value
- now_vm
),
160 NANOSECONDS_PER_SECOND
, s
->tm4
[counter
].freq
);
161 timer_mod(s
->tm4
[n
].tm
.qtimer
, new_qemu
);
164 static uint64_t pxa2xx_timer_read(void *opaque
, hwaddr offset
,
167 PXA2xxTimerInfo
*s
= (PXA2xxTimerInfo
*) opaque
;
178 return s
->timer
[tm
].value
;
194 if (!pxa2xx_timer_has_tm4(s
))
196 return s
->tm4
[tm
].tm
.value
;
198 return s
->clock
+ muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) -
199 s
->lastload
, s
->freq
, NANOSECONDS_PER_SECOND
);
215 if (!pxa2xx_timer_has_tm4(s
))
218 if ((tm
== 9 - 4 || tm
== 11 - 4) && (s
->tm4
[tm
].control
& (1 << 9))) {
219 if (s
->tm4
[tm
- 1].freq
)
220 s
->snapshot
= s
->tm4
[tm
- 1].clock
+ muldiv64(
221 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) -
222 s
->tm4
[tm
- 1].lastload
,
223 s
->tm4
[tm
- 1].freq
, NANOSECONDS_PER_SECOND
);
225 s
->snapshot
= s
->tm4
[tm
- 1].clock
;
228 if (!s
->tm4
[tm
].freq
)
229 return s
->tm4
[tm
].clock
;
230 return s
->tm4
[tm
].clock
+
231 muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
) -
232 s
->tm4
[tm
].lastload
, s
->tm4
[tm
].freq
,
233 NANOSECONDS_PER_SECOND
);
235 return s
->irq_enabled
;
236 case OSSR
: /* Status register */
255 if (!pxa2xx_timer_has_tm4(s
))
257 return s
->tm4
[tm
].control
;
261 qemu_log_mask(LOG_UNIMP
,
262 "%s: unknown register 0x%02" HWADDR_PRIx
"\n",
266 qemu_log_mask(LOG_GUEST_ERROR
,
267 "%s: incorrect register 0x%02" HWADDR_PRIx
"\n",
274 static void pxa2xx_timer_write(void *opaque
, hwaddr offset
,
275 uint64_t value
, unsigned size
)
278 PXA2xxTimerInfo
*s
= (PXA2xxTimerInfo
*) opaque
;
288 s
->timer
[tm
].value
= value
;
289 pxa2xx_timer_update(s
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
));
306 if (!pxa2xx_timer_has_tm4(s
))
308 s
->tm4
[tm
].tm
.value
= value
;
309 pxa2xx_timer_update4(s
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), tm
);
312 s
->oldclock
= s
->clock
;
313 s
->lastload
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
315 pxa2xx_timer_update(s
, s
->lastload
);
332 if (!pxa2xx_timer_has_tm4(s
))
334 s
->tm4
[tm
].oldclock
= s
->tm4
[tm
].clock
;
335 s
->tm4
[tm
].lastload
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
336 s
->tm4
[tm
].clock
= value
;
337 pxa2xx_timer_update4(s
, s
->tm4
[tm
].lastload
, tm
);
340 s
->irq_enabled
= value
& 0xfff;
342 case OSSR
: /* Status register */
345 for (i
= 0; i
< 4; i
++, value
>>= 1)
347 qemu_irq_lower(s
->timer
[i
].irq
);
348 if (pxa2xx_timer_has_tm4(s
) && !(s
->events
& 0xff0) && value
)
349 qemu_irq_lower(s
->irq4
);
351 case OWER
: /* XXX: Reset on OSMR3 match? */
361 if (!pxa2xx_timer_has_tm4(s
))
363 s
->tm4
[tm
].control
= value
& 0x0ff;
364 /* XXX Stop if running (shouldn't happen) */
365 if ((value
& (1 << 7)) || tm
== 0)
366 s
->tm4
[tm
].freq
= pxa2xx_timer4_freq
[value
& 7];
369 pxa2xx_timer_update4(s
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), tm
);
379 if (!pxa2xx_timer_has_tm4(s
))
381 s
->tm4
[tm
].control
= value
& 0x3ff;
382 /* XXX Stop if running (shouldn't happen) */
383 if ((value
& (1 << 7)) || !(tm
& 1))
385 pxa2xx_timer4_freq
[(value
& (1 << 8)) ? 0 : (value
& 7)];
388 pxa2xx_timer_update4(s
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), tm
);
392 qemu_log_mask(LOG_UNIMP
,
393 "%s: unknown register 0x%02" HWADDR_PRIx
" "
394 "(value 0x%08" PRIx64
")\n", __func__
, offset
, value
);
397 qemu_log_mask(LOG_GUEST_ERROR
,
398 "%s: incorrect register 0x%02" HWADDR_PRIx
" "
399 "(value 0x%08" PRIx64
")\n", __func__
, offset
, value
);
403 static const MemoryRegionOps pxa2xx_timer_ops
= {
404 .read
= pxa2xx_timer_read
,
405 .write
= pxa2xx_timer_write
,
406 .endianness
= DEVICE_NATIVE_ENDIAN
,
409 static void pxa2xx_timer_tick(void *opaque
)
411 PXA2xxTimer0
*t
= (PXA2xxTimer0
*) opaque
;
412 PXA2xxTimerInfo
*i
= t
->info
;
414 if (i
->irq_enabled
& (1 << t
->num
)) {
415 i
->events
|= 1 << t
->num
;
416 qemu_irq_raise(t
->irq
);
422 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
426 static void pxa2xx_timer_tick4(void *opaque
)
428 PXA2xxTimer4
*t
= (PXA2xxTimer4
*) opaque
;
429 PXA2xxTimerInfo
*i
= (PXA2xxTimerInfo
*) t
->tm
.info
;
431 pxa2xx_timer_tick(&t
->tm
);
432 if (t
->control
& (1 << 3))
434 if (t
->control
& (1 << 6))
435 pxa2xx_timer_update4(i
, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
), t
->tm
.num
- 4);
436 if (i
->events
& 0xff0)
437 qemu_irq_raise(i
->irq4
);
440 static int pxa25x_timer_post_load(void *opaque
, int version_id
)
442 PXA2xxTimerInfo
*s
= (PXA2xxTimerInfo
*) opaque
;
446 now
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
447 pxa2xx_timer_update(s
, now
);
449 if (pxa2xx_timer_has_tm4(s
))
450 for (i
= 0; i
< 8; i
++)
451 pxa2xx_timer_update4(s
, now
, i
);
456 static void pxa2xx_timer_init(Object
*obj
)
458 PXA2xxTimerInfo
*s
= PXA2XX_TIMER(obj
);
459 SysBusDevice
*dev
= SYS_BUS_DEVICE(obj
);
464 s
->lastload
= qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL
);
467 memory_region_init_io(&s
->iomem
, obj
, &pxa2xx_timer_ops
, s
,
468 "pxa2xx-timer", 0x00001000);
469 sysbus_init_mmio(dev
, &s
->iomem
);
472 static void pxa2xx_timer_realize(DeviceState
*dev
, Error
**errp
)
474 PXA2xxTimerInfo
*s
= PXA2XX_TIMER(dev
);
475 SysBusDevice
*sbd
= SYS_BUS_DEVICE(dev
);
478 for (i
= 0; i
< 4; i
++) {
479 s
->timer
[i
].value
= 0;
480 sysbus_init_irq(sbd
, &s
->timer
[i
].irq
);
481 s
->timer
[i
].info
= s
;
483 s
->timer
[i
].qtimer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
,
484 pxa2xx_timer_tick
, &s
->timer
[i
]);
487 if (s
->flags
& (1 << PXA2XX_TIMER_HAVE_TM4
)) {
488 sysbus_init_irq(sbd
, &s
->irq4
);
490 for (i
= 0; i
< 8; i
++) {
491 s
->tm4
[i
].tm
.value
= 0;
492 s
->tm4
[i
].tm
.info
= s
;
493 s
->tm4
[i
].tm
.num
= i
+ 4;
495 s
->tm4
[i
].control
= 0x0;
496 s
->tm4
[i
].tm
.qtimer
= timer_new_ns(QEMU_CLOCK_VIRTUAL
,
497 pxa2xx_timer_tick4
, &s
->tm4
[i
]);
502 static const VMStateDescription vmstate_pxa2xx_timer0_regs
= {
503 .name
= "pxa2xx_timer0",
505 .minimum_version_id
= 2,
506 .fields
= (VMStateField
[]) {
507 VMSTATE_UINT32(value
, PXA2xxTimer0
),
508 VMSTATE_END_OF_LIST(),
512 static const VMStateDescription vmstate_pxa2xx_timer4_regs
= {
513 .name
= "pxa2xx_timer4",
515 .minimum_version_id
= 1,
516 .fields
= (VMStateField
[]) {
517 VMSTATE_STRUCT(tm
, PXA2xxTimer4
, 1,
518 vmstate_pxa2xx_timer0_regs
, PXA2xxTimer0
),
519 VMSTATE_INT32(oldclock
, PXA2xxTimer4
),
520 VMSTATE_INT32(clock
, PXA2xxTimer4
),
521 VMSTATE_UINT64(lastload
, PXA2xxTimer4
),
522 VMSTATE_UINT32(freq
, PXA2xxTimer4
),
523 VMSTATE_UINT32(control
, PXA2xxTimer4
),
524 VMSTATE_END_OF_LIST(),
528 static bool pxa2xx_timer_has_tm4_test(void *opaque
, int version_id
)
530 return pxa2xx_timer_has_tm4(opaque
);
533 static const VMStateDescription vmstate_pxa2xx_timer_regs
= {
534 .name
= "pxa2xx_timer",
536 .minimum_version_id
= 1,
537 .post_load
= pxa25x_timer_post_load
,
538 .fields
= (VMStateField
[]) {
539 VMSTATE_INT32(clock
, PXA2xxTimerInfo
),
540 VMSTATE_INT32(oldclock
, PXA2xxTimerInfo
),
541 VMSTATE_UINT64(lastload
, PXA2xxTimerInfo
),
542 VMSTATE_STRUCT_ARRAY(timer
, PXA2xxTimerInfo
, 4, 1,
543 vmstate_pxa2xx_timer0_regs
, PXA2xxTimer0
),
544 VMSTATE_UINT32(events
, PXA2xxTimerInfo
),
545 VMSTATE_UINT32(irq_enabled
, PXA2xxTimerInfo
),
546 VMSTATE_UINT32(reset3
, PXA2xxTimerInfo
),
547 VMSTATE_UINT32(snapshot
, PXA2xxTimerInfo
),
548 VMSTATE_STRUCT_ARRAY_TEST(tm4
, PXA2xxTimerInfo
, 8,
549 pxa2xx_timer_has_tm4_test
, 0,
550 vmstate_pxa2xx_timer4_regs
, PXA2xxTimer4
),
551 VMSTATE_END_OF_LIST(),
555 static Property pxa25x_timer_dev_properties
[] = {
556 DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo
, freq
, PXA25X_FREQ
),
557 DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo
, flags
,
558 PXA2XX_TIMER_HAVE_TM4
, false),
559 DEFINE_PROP_END_OF_LIST(),
562 static void pxa25x_timer_dev_class_init(ObjectClass
*klass
, void *data
)
564 DeviceClass
*dc
= DEVICE_CLASS(klass
);
566 dc
->desc
= "PXA25x timer";
567 device_class_set_props(dc
, pxa25x_timer_dev_properties
);
570 static const TypeInfo pxa25x_timer_dev_info
= {
571 .name
= "pxa25x-timer",
572 .parent
= TYPE_PXA2XX_TIMER
,
573 .instance_size
= sizeof(PXA2xxTimerInfo
),
574 .class_init
= pxa25x_timer_dev_class_init
,
577 static Property pxa27x_timer_dev_properties
[] = {
578 DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo
, freq
, PXA27X_FREQ
),
579 DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo
, flags
,
580 PXA2XX_TIMER_HAVE_TM4
, true),
581 DEFINE_PROP_END_OF_LIST(),
584 static void pxa27x_timer_dev_class_init(ObjectClass
*klass
, void *data
)
586 DeviceClass
*dc
= DEVICE_CLASS(klass
);
588 dc
->desc
= "PXA27x timer";
589 device_class_set_props(dc
, pxa27x_timer_dev_properties
);
592 static const TypeInfo pxa27x_timer_dev_info
= {
593 .name
= "pxa27x-timer",
594 .parent
= TYPE_PXA2XX_TIMER
,
595 .instance_size
= sizeof(PXA2xxTimerInfo
),
596 .class_init
= pxa27x_timer_dev_class_init
,
599 static void pxa2xx_timer_class_init(ObjectClass
*oc
, void *data
)
601 DeviceClass
*dc
= DEVICE_CLASS(oc
);
603 dc
->realize
= pxa2xx_timer_realize
;
604 dc
->vmsd
= &vmstate_pxa2xx_timer_regs
;
607 static const TypeInfo pxa2xx_timer_type_info
= {
608 .name
= TYPE_PXA2XX_TIMER
,
609 .parent
= TYPE_SYS_BUS_DEVICE
,
610 .instance_size
= sizeof(PXA2xxTimerInfo
),
611 .instance_init
= pxa2xx_timer_init
,
613 .class_init
= pxa2xx_timer_class_init
,
616 static void pxa2xx_timer_register_types(void)
618 type_register_static(&pxa2xx_timer_type_info
);
619 type_register_static(&pxa25x_timer_dev_info
);
620 type_register_static(&pxa27x_timer_dev_info
);
623 type_init(pxa2xx_timer_register_types
)