hw/timer/xilinx_timer.c

   1 /*
   2  * QEMU model of the Xilinx timer block.
   3  *
   4  * Copyright (c) 2009 Edgar E. Iglesias.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "hw/sysbus.h"
  26 #include "hw/ptimer.h"
  27 #include "qemu/log.h"
  28
  29 #define D(x)
  30
  31 #define R_TCSR     0
  32 #define R_TLR      1
  33 #define R_TCR      2
  34 #define R_MAX      4
  35
  36 #define TCSR_MDT        (1<<0)
  37 #define TCSR_UDT        (1<<1)
  38 #define TCSR_GENT       (1<<2)
  39 #define TCSR_CAPT       (1<<3)
  40 #define TCSR_ARHT       (1<<4)
  41 #define TCSR_LOAD       (1<<5)
  42 #define TCSR_ENIT       (1<<6)
  43 #define TCSR_ENT        (1<<7)
  44 #define TCSR_TINT       (1<<8)
  45 #define TCSR_PWMA       (1<<9)
  46 #define TCSR_ENALL      (1<<10)
  47
  48 struct xlx_timer
  49 {
  50     QEMUBH *bh;
  51     ptimer_state *ptimer;
  52     void *parent;
  53     int nr; /* for debug.  */
  54
  55     unsigned long timer_div;
  56
  57     uint32_t regs[R_MAX];
  58 };
  59
  60 #define TYPE_XILINX_TIMER "xlnx.xps-timer"
  61 #define XILINX_TIMER(obj) \
  62     OBJECT_CHECK(struct timerblock, (obj), TYPE_XILINX_TIMER)
  63
  64 struct timerblock
  65 {
  66     SysBusDevice parent_obj;
  67
  68     MemoryRegion mmio;
  69     qemu_irq irq;
  70     uint8_t one_timer_only;
  71     uint32_t freq_hz;
  72     struct xlx_timer *timers;
  73 };
  74
  75 static inline unsigned int num_timers(struct timerblock *t)
  76 {
  77     return 2 - t->one_timer_only;
  78 }
  79
  80 static inline unsigned int timer_from_addr(hwaddr addr)
  81 {
  82     /* Timers get a 4x32bit control reg area each.  */
  83     return addr >> 2;
  84 }
  85
  86 static void timer_update_irq(struct timerblock *t)
  87 {
  88     unsigned int i, irq = 0;
  89     uint32_t csr;
  90
  91     for (i = 0; i < num_timers(t); i++) {
  92         csr = t->timers[i].regs[R_TCSR];
  93         irq |= (csr & TCSR_TINT) && (csr & TCSR_ENIT);
  94     }
  95
  96     /* All timers within the same slave share a single IRQ line.  */
  97     qemu_set_irq(t->irq, !!irq);
  98 }
  99
 100 static uint64_t
 101 timer_read(void *opaque, hwaddr addr, unsigned int size)
 102 {
 103     struct timerblock *t = opaque;
 104     struct xlx_timer *xt;
 105     uint32_t r = 0;
 106     unsigned int timer;
 107
 108     addr >>= 2;
 109     timer = timer_from_addr(addr);
 110     xt = &t->timers[timer];
 111     /* Further decoding to address a specific timers reg.  */
 112     addr &= 0x3;
 113     switch (addr)
 114     {
 115         case R_TCR:
 116                 r = ptimer_get_count(xt->ptimer);
 117                 if (!(xt->regs[R_TCSR] & TCSR_UDT))
 118                     r = ~r;
 119                 D(qemu_log("xlx_timer t=%d read counter=%x udt=%d\n",
 120                          timer, r, xt->regs[R_TCSR] & TCSR_UDT));
 121             break;
 122         default:
 123             if (addr < ARRAY_SIZE(xt->regs))
 124                 r = xt->regs[addr];
 125             break;
 126
 127     }
 128     D(fprintf(stderr, "%s timer=%d %x=%x\n", __func__, timer, addr * 4, r));
 129     return r;
 130 }
 131
 132 static void timer_enable(struct xlx_timer *xt)
 133 {
 134     uint64_t count;
 135
 136     D(fprintf(stderr, "%s timer=%d down=%d\n", __func__,
 137               xt->nr, xt->regs[R_TCSR] & TCSR_UDT));
 138
 139     ptimer_stop(xt->ptimer);
 140
 141     if (xt->regs[R_TCSR] & TCSR_UDT)
 142         count = xt->regs[R_TLR];
 143     else
 144         count = ~0 - xt->regs[R_TLR];
 145     ptimer_set_limit(xt->ptimer, count, 1);
 146     ptimer_run(xt->ptimer, 1);
 147 }
 148
 149 static void
 150 timer_write(void *opaque, hwaddr addr,
 151             uint64_t val64, unsigned int size)
 152 {
 153     struct timerblock *t = opaque;
 154     struct xlx_timer *xt;
 155     unsigned int timer;
 156     uint32_t value = val64;
 157
 158     addr >>= 2;
 159     timer = timer_from_addr(addr);
 160     xt = &t->timers[timer];
 161     D(fprintf(stderr, "%s addr=%x val=%x (timer=%d off=%d)\n",
 162              __func__, addr * 4, value, timer, addr & 3));
 163     /* Further decoding to address a specific timers reg.  */
 164     addr &= 3;
 165     switch (addr)
 166     {
 167         case R_TCSR:
 168             if (value & TCSR_TINT)
 169                 value &= ~TCSR_TINT;
 170
 171             xt->regs[addr] = value;
 172             if (value & TCSR_ENT)
 173                 timer_enable(xt);
 174             break;
 175
 176         default:
 177             if (addr < ARRAY_SIZE(xt->regs))
 178                 xt->regs[addr] = value;
 179             break;
 180     }
 181     timer_update_irq(t);
 182 }
 183
 184 static const MemoryRegionOps timer_ops = {
 185     .read = timer_read,
 186     .write = timer_write,
 187     .endianness = DEVICE_NATIVE_ENDIAN,
 188     .valid = {
 189         .min_access_size = 4,
 190         .max_access_size = 4
 191     }
 192 };
 193
 194 static void timer_hit(void *opaque)
 195 {
 196     struct xlx_timer *xt = opaque;
 197     struct timerblock *t = xt->parent;
 198     D(fprintf(stderr, "%s %d\n", __func__, xt->nr));
 199     xt->regs[R_TCSR] |= TCSR_TINT;
 200
 201     if (xt->regs[R_TCSR] & TCSR_ARHT)
 202         timer_enable(xt);
 203     timer_update_irq(t);
 204 }
 205
 206 static int xilinx_timer_init(SysBusDevice *dev)
 207 {
 208     struct timerblock *t = XILINX_TIMER(dev);
 209     unsigned int i;
 210
 211     /* All timers share a single irq line.  */
 212     sysbus_init_irq(dev, &t->irq);
 213
 214     /* Init all the ptimers.  */
 215     t->timers = g_malloc0(sizeof t->timers[0] * num_timers(t));
 216     for (i = 0; i < num_timers(t); i++) {
 217         struct xlx_timer *xt = &t->timers[i];
 218
 219         xt->parent = t;
 220         xt->nr = i;
 221         xt->bh = qemu_bh_new(timer_hit, xt);
 222         xt->ptimer = ptimer_init(xt->bh);
 223         ptimer_set_freq(xt->ptimer, t->freq_hz);
 224     }
 225
 226     memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t, "xlnx.xps-timer",
 227                           R_MAX * 4 * num_timers(t));
 228     sysbus_init_mmio(dev, &t->mmio);
 229     return 0;
 230 }
 231
 232 static Property xilinx_timer_properties[] = {
 233     DEFINE_PROP_UINT32("clock-frequency", struct timerblock, freq_hz,
 234                                                                 62 * 1000000),
 235     DEFINE_PROP_UINT8("one-timer-only", struct timerblock, one_timer_only, 0),
 236     DEFINE_PROP_END_OF_LIST(),
 237 };
 238
 239 static void xilinx_timer_class_init(ObjectClass *klass, void *data)
 240 {
 241     DeviceClass *dc = DEVICE_CLASS(klass);
 242     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 243
 244     k->init = xilinx_timer_init;
 245     dc->props = xilinx_timer_properties;
 246 }
 247
 248 static const TypeInfo xilinx_timer_info = {
 249     .name          = TYPE_XILINX_TIMER,
 250     .parent        = TYPE_SYS_BUS_DEVICE,
 251     .instance_size = sizeof(struct timerblock),
 252     .class_init    = xilinx_timer_class_init,
 253 };
 254
 255 static void xilinx_timer_register_types(void)
 256 {
 257     type_register_static(&xilinx_timer_info);
 258 }
 259
 260 type_init(xilinx_timer_register_types)