2 * QEMU Uninorth PCI host (for all Mac99 and newer machines)
4 * Copyright (c) 2006 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
32 #define UNIN_DPRINTF(fmt, ...) \
33 do { printf("UNIN: " fmt , ## __VA_ARGS__); } while (0)
35 #define UNIN_DPRINTF(fmt, ...)
38 typedef target_phys_addr_t pci_addr_t
;
41 typedef struct UNINState
{
43 PCIHostState host_state
;
46 static void pci_unin_main_config_writel (void *opaque
, target_phys_addr_t addr
,
49 UNINState
*s
= opaque
;
51 UNIN_DPRINTF("config_writel addr " TARGET_FMT_plx
" val %x\n", addr
, val
);
52 #ifdef TARGET_WORDS_BIGENDIAN
56 s
->host_state
.config_reg
= val
;
59 static uint32_t pci_unin_main_config_readl (void *opaque
,
60 target_phys_addr_t addr
)
62 UNINState
*s
= opaque
;
65 val
= s
->host_state
.config_reg
;
66 #ifdef TARGET_WORDS_BIGENDIAN
69 UNIN_DPRINTF("config_readl addr " TARGET_FMT_plx
" val %x\n", addr
, val
);
74 static CPUWriteMemoryFunc
* const pci_unin_main_config_write
[] = {
75 &pci_unin_main_config_writel
,
76 &pci_unin_main_config_writel
,
77 &pci_unin_main_config_writel
,
80 static CPUReadMemoryFunc
* const pci_unin_main_config_read
[] = {
81 &pci_unin_main_config_readl
,
82 &pci_unin_main_config_readl
,
83 &pci_unin_main_config_readl
,
86 static CPUWriteMemoryFunc
* const pci_unin_main_write
[] = {
87 &pci_host_data_writeb
,
88 &pci_host_data_writew
,
89 &pci_host_data_writel
,
92 static CPUReadMemoryFunc
* const pci_unin_main_read
[] = {
98 static void pci_unin_config_writel (void *opaque
, target_phys_addr_t addr
,
101 UNINState
*s
= opaque
;
103 s
->host_state
.config_reg
= val
;
106 static uint32_t pci_unin_config_readl (void *opaque
,
107 target_phys_addr_t addr
)
109 UNINState
*s
= opaque
;
111 return s
->host_state
.config_reg
;
114 static CPUWriteMemoryFunc
* const pci_unin_config_write
[] = {
115 &pci_unin_config_writel
,
116 &pci_unin_config_writel
,
117 &pci_unin_config_writel
,
120 static CPUReadMemoryFunc
* const pci_unin_config_read
[] = {
121 &pci_unin_config_readl
,
122 &pci_unin_config_readl
,
123 &pci_unin_config_readl
,
126 static CPUWriteMemoryFunc
* const pci_unin_write
[] = {
127 &pci_host_data_writeb
,
128 &pci_host_data_writew
,
129 &pci_host_data_writel
,
132 static CPUReadMemoryFunc
* const pci_unin_read
[] = {
133 &pci_host_data_readb
,
134 &pci_host_data_readw
,
135 &pci_host_data_readl
,
138 /* Don't know if this matches real hardware, but it agrees with OHW. */
139 static int pci_unin_map_irq(PCIDevice
*pci_dev
, int irq_num
)
141 return (irq_num
+ (pci_dev
->devfn
>> 3)) & 3;
144 static void pci_unin_set_irq(qemu_irq
*pic
, int irq_num
, int level
)
146 qemu_set_irq(pic
[irq_num
+ 8], level
);
149 static void pci_unin_save(QEMUFile
* f
, void *opaque
)
151 PCIDevice
*d
= opaque
;
153 pci_device_save(d
, f
);
156 static int pci_unin_load(QEMUFile
* f
, void *opaque
, int version_id
)
158 PCIDevice
*d
= opaque
;
163 return pci_device_load(d
, f
);
166 static void pci_unin_reset(void *opaque
)
170 static int pci_unin_main_init_device(SysBusDevice
*dev
)
173 int pci_mem_config
, pci_mem_data
;
175 /* Use values found on a real PowerMac */
176 /* Uninorth main bus */
177 s
= FROM_SYSBUS(UNINState
, dev
);
179 pci_mem_config
= cpu_register_io_memory(pci_unin_main_config_read
,
180 pci_unin_main_config_write
, s
);
181 pci_mem_data
= cpu_register_io_memory(pci_unin_main_read
,
182 pci_unin_main_write
, &s
->host_state
);
184 sysbus_init_mmio(dev
, 0x1000, pci_mem_config
);
185 sysbus_init_mmio(dev
, 0x1000, pci_mem_data
);
187 register_savevm("uninorth", 0, 1, pci_unin_save
, pci_unin_load
, &s
->host_state
);
188 qemu_register_reset(pci_unin_reset
, &s
->host_state
);
189 pci_unin_reset(&s
->host_state
);
193 static int pci_dec_21154_init_device(SysBusDevice
*dev
)
196 int pci_mem_config
, pci_mem_data
;
198 /* Uninorth bridge */
199 s
= FROM_SYSBUS(UNINState
, dev
);
201 // XXX: s = &pci_bridge[2];
202 pci_mem_config
= cpu_register_io_memory(pci_unin_config_read
,
203 pci_unin_config_write
, s
);
204 pci_mem_data
= cpu_register_io_memory(pci_unin_main_read
,
205 pci_unin_main_write
, &s
->host_state
);
206 sysbus_init_mmio(dev
, 0x1000, pci_mem_config
);
207 sysbus_init_mmio(dev
, 0x1000, pci_mem_data
);
211 static int pci_unin_agp_init_device(SysBusDevice
*dev
)
214 int pci_mem_config
, pci_mem_data
;
216 /* Uninorth AGP bus */
217 s
= FROM_SYSBUS(UNINState
, dev
);
219 pci_mem_config
= cpu_register_io_memory(pci_unin_config_read
,
220 pci_unin_config_write
, s
);
221 pci_mem_data
= cpu_register_io_memory(pci_unin_main_read
,
222 pci_unin_main_write
, &s
->host_state
);
223 sysbus_init_mmio(dev
, 0x1000, pci_mem_config
);
224 sysbus_init_mmio(dev
, 0x1000, pci_mem_data
);
228 static int pci_unin_internal_init_device(SysBusDevice
*dev
)
231 int pci_mem_config
, pci_mem_data
;
233 /* Uninorth internal bus */
234 s
= FROM_SYSBUS(UNINState
, dev
);
236 pci_mem_config
= cpu_register_io_memory(pci_unin_config_read
,
237 pci_unin_config_write
, s
);
238 pci_mem_data
= cpu_register_io_memory(pci_unin_read
,
240 sysbus_init_mmio(dev
, 0x1000, pci_mem_config
);
241 sysbus_init_mmio(dev
, 0x1000, pci_mem_data
);
245 PCIBus
*pci_pmac_init(qemu_irq
*pic
)
251 /* Use values found on a real PowerMac */
252 /* Uninorth main bus */
253 dev
= qdev_create(NULL
, "Uni-north main");
255 s
= sysbus_from_qdev(dev
);
256 d
= FROM_SYSBUS(UNINState
, s
);
257 d
->host_state
.bus
= pci_register_bus(NULL
, "pci",
258 pci_unin_set_irq
, pci_unin_map_irq
,
261 pci_create_simple(d
->host_state
.bus
, 11 << 3, "Uni-north main");
263 sysbus_mmio_map(s
, 0, 0xf2800000);
264 sysbus_mmio_map(s
, 1, 0xf2c00000);
266 /* DEC 21154 bridge */
268 /* XXX: not activated as PPC BIOS doesn't handle multiple buses properly */
269 pci_create_simple(d
->host_state
.bus
, 12 << 3, "DEC 21154");
272 /* Uninorth AGP bus */
273 pci_create_simple(d
->host_state
.bus
, 13 << 3, "Uni-north AGP");
275 /* Uninorth internal bus */
277 /* XXX: not needed for now */
278 pci_create_simple(d
->host_state
.bus
, 14 << 3, "Uni-north internal");
281 return d
->host_state
.bus
;
284 static int unin_main_pci_host_init(PCIDevice
*d
)
286 pci_config_set_vendor_id(d
->config
, PCI_VENDOR_ID_APPLE
);
287 pci_config_set_device_id(d
->config
, PCI_DEVICE_ID_APPLE_UNI_N_PCI
);
288 d
->config
[0x08] = 0x00; // revision
289 pci_config_set_class(d
->config
, PCI_CLASS_BRIDGE_HOST
);
290 d
->config
[0x0C] = 0x08; // cache_line_size
291 d
->config
[0x0D] = 0x10; // latency_timer
292 d
->config
[PCI_HEADER_TYPE
] = PCI_HEADER_TYPE_NORMAL
; // header_type
293 d
->config
[0x34] = 0x00; // capabilities_pointer
297 static int dec_21154_pci_host_init(PCIDevice
*d
)
299 /* pci-to-pci bridge */
300 pci_config_set_vendor_id(d
->config
, PCI_VENDOR_ID_DEC
);
301 pci_config_set_device_id(d
->config
, PCI_DEVICE_ID_DEC_21154
);
302 d
->config
[0x08] = 0x05; // revision
303 pci_config_set_class(d
->config
, PCI_CLASS_BRIDGE_PCI
);
304 d
->config
[0x0C] = 0x08; // cache_line_size
305 d
->config
[0x0D] = 0x20; // latency_timer
306 d
->config
[PCI_HEADER_TYPE
] = PCI_HEADER_TYPE_BRIDGE
; // header_type
308 d
->config
[0x18] = 0x01; // primary_bus
309 d
->config
[0x19] = 0x02; // secondary_bus
310 d
->config
[0x1A] = 0x02; // subordinate_bus
311 d
->config
[0x1B] = 0x20; // secondary_latency_timer
312 d
->config
[0x1C] = 0x11; // io_base
313 d
->config
[0x1D] = 0x01; // io_limit
314 d
->config
[0x20] = 0x00; // memory_base
315 d
->config
[0x21] = 0x80;
316 d
->config
[0x22] = 0x00; // memory_limit
317 d
->config
[0x23] = 0x80;
318 d
->config
[0x24] = 0x01; // prefetchable_memory_base
319 d
->config
[0x25] = 0x80;
320 d
->config
[0x26] = 0xF1; // prefectchable_memory_limit
321 d
->config
[0x27] = 0x7F;
322 // d->config[0x34] = 0xdc // capabilities_pointer
326 static int unin_agp_pci_host_init(PCIDevice
*d
)
328 pci_config_set_vendor_id(d
->config
, PCI_VENDOR_ID_APPLE
);
329 pci_config_set_device_id(d
->config
, PCI_DEVICE_ID_APPLE_UNI_N_AGP
);
330 d
->config
[0x08] = 0x00; // revision
331 pci_config_set_class(d
->config
, PCI_CLASS_BRIDGE_HOST
);
332 d
->config
[0x0C] = 0x08; // cache_line_size
333 d
->config
[0x0D] = 0x10; // latency_timer
334 d
->config
[PCI_HEADER_TYPE
] = PCI_HEADER_TYPE_NORMAL
; // header_type
335 // d->config[0x34] = 0x80; // capabilities_pointer
339 static int unin_internal_pci_host_init(PCIDevice
*d
)
341 pci_config_set_vendor_id(d
->config
, PCI_VENDOR_ID_APPLE
);
342 pci_config_set_device_id(d
->config
, PCI_DEVICE_ID_APPLE_UNI_N_I_PCI
);
343 d
->config
[0x08] = 0x00; // revision
344 pci_config_set_class(d
->config
, PCI_CLASS_BRIDGE_HOST
);
345 d
->config
[0x0C] = 0x08; // cache_line_size
346 d
->config
[0x0D] = 0x10; // latency_timer
347 d
->config
[PCI_HEADER_TYPE
] = PCI_HEADER_TYPE_NORMAL
; // header_type
348 d
->config
[0x34] = 0x00; // capabilities_pointer
352 static PCIDeviceInfo unin_main_pci_host_info
= {
353 .qdev
.name
= "Uni-north main",
354 .qdev
.size
= sizeof(PCIDevice
),
355 .init
= unin_main_pci_host_init
,
358 static PCIDeviceInfo dec_21154_pci_host_info
= {
359 .qdev
.name
= "DEC 21154",
360 .qdev
.size
= sizeof(PCIDevice
),
361 .init
= dec_21154_pci_host_init
,
364 static PCIDeviceInfo unin_agp_pci_host_info
= {
365 .qdev
.name
= "Uni-north AGP",
366 .qdev
.size
= sizeof(PCIDevice
),
367 .init
= unin_agp_pci_host_init
,
370 static PCIDeviceInfo unin_internal_pci_host_info
= {
371 .qdev
.name
= "Uni-north internal",
372 .qdev
.size
= sizeof(PCIDevice
),
373 .init
= unin_internal_pci_host_init
,
376 static void unin_register_devices(void)
378 sysbus_register_dev("Uni-north main", sizeof(UNINState
),
379 pci_unin_main_init_device
);
380 pci_qdev_register(&unin_main_pci_host_info
);
381 sysbus_register_dev("DEC 21154", sizeof(UNINState
),
382 pci_dec_21154_init_device
);
383 pci_qdev_register(&dec_21154_pci_host_info
);
384 sysbus_register_dev("Uni-north AGP", sizeof(UNINState
),
385 pci_unin_agp_init_device
);
386 pci_qdev_register(&unin_agp_pci_host_info
);
387 sysbus_register_dev("Uni-north internal", sizeof(UNINState
),
388 pci_unin_internal_init_device
);
389 pci_qdev_register(&unin_internal_pci_host_info
);
392 device_init(unin_register_devices
)