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ehci: trace guest bugs
[mirror_qemu.git] / hw / usb / hcd-ehci.c
1 /*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 * Copyright(c) 2011-2012 Red Hat, Inc.
6 *
7 * Red Hat Authors:
8 * Gerd Hoffmann <kraxel@redhat.com>
9 * Hans de Goede <hdegoede@redhat.com>
10 *
11 * EHCI project was started by Mark Burkley, with contributions by
12 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
13 * Jan Kiszka and Vincent Palatin contributed bugfixes.
14 *
15 *
16 * This library is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU Lesser General Public
18 * License as published by the Free Software Foundation; either
19 * version 2 of the License, or(at your option) any later version.
20 *
21 * This library is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
24 * Lesser General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, see <http://www.gnu.org/licenses/>.
28 */
29
30 #include "hw/hw.h"
31 #include "qemu-timer.h"
32 #include "hw/usb.h"
33 #include "hw/pci.h"
34 #include "monitor.h"
35 #include "trace.h"
36 #include "dma.h"
37
38 #define EHCI_DEBUG 0
39
40 #if EHCI_DEBUG
41 #define DPRINTF printf
42 #else
43 #define DPRINTF(...)
44 #endif
45
46 /* internal processing - reset HC to try and recover */
47 #define USB_RET_PROCERR (-99)
48
49 #define MMIO_SIZE 0x1000
50
51 /* Capability Registers Base Address - section 2.2 */
52 #define CAPREGBASE 0x0000
53 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
54 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
55 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
56 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
57 #define EECP HCCPARAMS + 1
58 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
59 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
60
61 #define OPREGBASE 0x0020 // Operational Registers Base Address
62
63 #define USBCMD OPREGBASE + 0x0000
64 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
65 #define USBCMD_HCRESET (1 << 1) // HC Reset
66 #define USBCMD_FLS (3 << 2) // Frame List Size
67 #define USBCMD_FLS_SH 2 // Frame List Size Shift
68 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
69 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
70 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
71 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
72 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
73 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
74 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
75 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
76
77 #define USBSTS OPREGBASE + 0x0004
78 #define USBSTS_RO_MASK 0x0000003f
79 #define USBSTS_INT (1 << 0) // USB Interrupt
80 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
81 #define USBSTS_PCD (1 << 2) // Port Change Detect
82 #define USBSTS_FLR (1 << 3) // Frame List Rollover
83 #define USBSTS_HSE (1 << 4) // Host System Error
84 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
85 #define USBSTS_HALT (1 << 12) // HC Halted
86 #define USBSTS_REC (1 << 13) // Reclamation
87 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
88 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
89
90 /*
91 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
92 * so no need to redefine here.
93 */
94 #define USBINTR OPREGBASE + 0x0008
95 #define USBINTR_MASK 0x0000003f
96
97 #define FRINDEX OPREGBASE + 0x000c
98 #define CTRLDSSEGMENT OPREGBASE + 0x0010
99 #define PERIODICLISTBASE OPREGBASE + 0x0014
100 #define ASYNCLISTADDR OPREGBASE + 0x0018
101 #define ASYNCLISTADDR_MASK 0xffffffe0
102
103 #define CONFIGFLAG OPREGBASE + 0x0040
104
105 #define PORTSC (OPREGBASE + 0x0044)
106 #define PORTSC_BEGIN PORTSC
107 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
108 /*
109 * Bits that are reserved or are read-only are masked out of values
110 * written to us by software
111 */
112 #define PORTSC_RO_MASK 0x007001c0
113 #define PORTSC_RWC_MASK 0x0000002a
114 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
115 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
116 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
117 #define PORTSC_PTC (15 << 16) // Port Test Control
118 #define PORTSC_PTC_SH 16 // Port Test Control shift
119 #define PORTSC_PIC (3 << 14) // Port Indicator Control
120 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
121 #define PORTSC_POWNER (1 << 13) // Port Owner
122 #define PORTSC_PPOWER (1 << 12) // Port Power
123 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
124 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
125 #define PORTSC_PRESET (1 << 8) // Port Reset
126 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
127 #define PORTSC_FPRES (1 << 6) // Force Port Resume
128 #define PORTSC_OCC (1 << 5) // Over Current Change
129 #define PORTSC_OCA (1 << 4) // Over Current Active
130 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
131 #define PORTSC_PED (1 << 2) // Port Enable/Disable
132 #define PORTSC_CSC (1 << 1) // Connect Status Change
133 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
134
135 #define FRAME_TIMER_FREQ 1000
136 #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ)
137
138 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
139 #define NB_PORTS 6 // Number of downstream ports
140 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
141 #define MAX_QH 100 // Max allowable queue heads in a chain
142
143 /* Internal periodic / asynchronous schedule state machine states
144 */
145 typedef enum {
146 EST_INACTIVE = 1000,
147 EST_ACTIVE,
148 EST_EXECUTING,
149 EST_SLEEPING,
150 /* The following states are internal to the state machine function
151 */
152 EST_WAITLISTHEAD,
153 EST_FETCHENTRY,
154 EST_FETCHQH,
155 EST_FETCHITD,
156 EST_FETCHSITD,
157 EST_ADVANCEQUEUE,
158 EST_FETCHQTD,
159 EST_EXECUTE,
160 EST_WRITEBACK,
161 EST_HORIZONTALQH
162 } EHCI_STATES;
163
164 /* macros for accessing fields within next link pointer entry */
165 #define NLPTR_GET(x) ((x) & 0xffffffe0)
166 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
167 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
168
169 /* link pointer types */
170 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
171 #define NLPTR_TYPE_QH 1 // queue head
172 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
173 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
174
175
176 /* EHCI spec version 1.0 Section 3.3
177 */
178 typedef struct EHCIitd {
179 uint32_t next;
180
181 uint32_t transact[8];
182 #define ITD_XACT_ACTIVE (1 << 31)
183 #define ITD_XACT_DBERROR (1 << 30)
184 #define ITD_XACT_BABBLE (1 << 29)
185 #define ITD_XACT_XACTERR (1 << 28)
186 #define ITD_XACT_LENGTH_MASK 0x0fff0000
187 #define ITD_XACT_LENGTH_SH 16
188 #define ITD_XACT_IOC (1 << 15)
189 #define ITD_XACT_PGSEL_MASK 0x00007000
190 #define ITD_XACT_PGSEL_SH 12
191 #define ITD_XACT_OFFSET_MASK 0x00000fff
192
193 uint32_t bufptr[7];
194 #define ITD_BUFPTR_MASK 0xfffff000
195 #define ITD_BUFPTR_SH 12
196 #define ITD_BUFPTR_EP_MASK 0x00000f00
197 #define ITD_BUFPTR_EP_SH 8
198 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
199 #define ITD_BUFPTR_DEVADDR_SH 0
200 #define ITD_BUFPTR_DIRECTION (1 << 11)
201 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
202 #define ITD_BUFPTR_MAXPKT_SH 0
203 #define ITD_BUFPTR_MULT_MASK 0x00000003
204 #define ITD_BUFPTR_MULT_SH 0
205 } EHCIitd;
206
207 /* EHCI spec version 1.0 Section 3.4
208 */
209 typedef struct EHCIsitd {
210 uint32_t next; // Standard next link pointer
211 uint32_t epchar;
212 #define SITD_EPCHAR_IO (1 << 31)
213 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
214 #define SITD_EPCHAR_PORTNUM_SH 24
215 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
216 #define SITD_EPCHAR_HUBADDR_SH 16
217 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
218 #define SITD_EPCHAR_EPNUM_SH 8
219 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
220
221 uint32_t uframe;
222 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
223 #define SITD_UFRAME_CMASK_SH 8
224 #define SITD_UFRAME_SMASK_MASK 0x000000ff
225
226 uint32_t results;
227 #define SITD_RESULTS_IOC (1 << 31)
228 #define SITD_RESULTS_PGSEL (1 << 30)
229 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
230 #define SITD_RESULTS_TYBYTES_SH 16
231 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
232 #define SITD_RESULTS_CPROGMASK_SH 8
233 #define SITD_RESULTS_ACTIVE (1 << 7)
234 #define SITD_RESULTS_ERR (1 << 6)
235 #define SITD_RESULTS_DBERR (1 << 5)
236 #define SITD_RESULTS_BABBLE (1 << 4)
237 #define SITD_RESULTS_XACTERR (1 << 3)
238 #define SITD_RESULTS_MISSEDUF (1 << 2)
239 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
240
241 uint32_t bufptr[2];
242 #define SITD_BUFPTR_MASK 0xfffff000
243 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
244 #define SITD_BUFPTR_TPOS_MASK 0x00000018
245 #define SITD_BUFPTR_TPOS_SH 3
246 #define SITD_BUFPTR_TCNT_MASK 0x00000007
247
248 uint32_t backptr; // Standard next link pointer
249 } EHCIsitd;
250
251 /* EHCI spec version 1.0 Section 3.5
252 */
253 typedef struct EHCIqtd {
254 uint32_t next; // Standard next link pointer
255 uint32_t altnext; // Standard next link pointer
256 uint32_t token;
257 #define QTD_TOKEN_DTOGGLE (1 << 31)
258 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
259 #define QTD_TOKEN_TBYTES_SH 16
260 #define QTD_TOKEN_IOC (1 << 15)
261 #define QTD_TOKEN_CPAGE_MASK 0x00007000
262 #define QTD_TOKEN_CPAGE_SH 12
263 #define QTD_TOKEN_CERR_MASK 0x00000c00
264 #define QTD_TOKEN_CERR_SH 10
265 #define QTD_TOKEN_PID_MASK 0x00000300
266 #define QTD_TOKEN_PID_SH 8
267 #define QTD_TOKEN_ACTIVE (1 << 7)
268 #define QTD_TOKEN_HALT (1 << 6)
269 #define QTD_TOKEN_DBERR (1 << 5)
270 #define QTD_TOKEN_BABBLE (1 << 4)
271 #define QTD_TOKEN_XACTERR (1 << 3)
272 #define QTD_TOKEN_MISSEDUF (1 << 2)
273 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
274 #define QTD_TOKEN_PING (1 << 0)
275
276 uint32_t bufptr[5]; // Standard buffer pointer
277 #define QTD_BUFPTR_MASK 0xfffff000
278 #define QTD_BUFPTR_SH 12
279 } EHCIqtd;
280
281 /* EHCI spec version 1.0 Section 3.6
282 */
283 typedef struct EHCIqh {
284 uint32_t next; // Standard next link pointer
285
286 /* endpoint characteristics */
287 uint32_t epchar;
288 #define QH_EPCHAR_RL_MASK 0xf0000000
289 #define QH_EPCHAR_RL_SH 28
290 #define QH_EPCHAR_C (1 << 27)
291 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
292 #define QH_EPCHAR_MPLEN_SH 16
293 #define QH_EPCHAR_H (1 << 15)
294 #define QH_EPCHAR_DTC (1 << 14)
295 #define QH_EPCHAR_EPS_MASK 0x00003000
296 #define QH_EPCHAR_EPS_SH 12
297 #define EHCI_QH_EPS_FULL 0
298 #define EHCI_QH_EPS_LOW 1
299 #define EHCI_QH_EPS_HIGH 2
300 #define EHCI_QH_EPS_RESERVED 3
301
302 #define QH_EPCHAR_EP_MASK 0x00000f00
303 #define QH_EPCHAR_EP_SH 8
304 #define QH_EPCHAR_I (1 << 7)
305 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
306 #define QH_EPCHAR_DEVADDR_SH 0
307
308 /* endpoint capabilities */
309 uint32_t epcap;
310 #define QH_EPCAP_MULT_MASK 0xc0000000
311 #define QH_EPCAP_MULT_SH 30
312 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
313 #define QH_EPCAP_PORTNUM_SH 23
314 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
315 #define QH_EPCAP_HUBADDR_SH 16
316 #define QH_EPCAP_CMASK_MASK 0x0000ff00
317 #define QH_EPCAP_CMASK_SH 8
318 #define QH_EPCAP_SMASK_MASK 0x000000ff
319 #define QH_EPCAP_SMASK_SH 0
320
321 uint32_t current_qtd; // Standard next link pointer
322 uint32_t next_qtd; // Standard next link pointer
323 uint32_t altnext_qtd;
324 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
325 #define QH_ALTNEXT_NAKCNT_SH 1
326
327 uint32_t token; // Same as QTD token
328 uint32_t bufptr[5]; // Standard buffer pointer
329 #define BUFPTR_CPROGMASK_MASK 0x000000ff
330 #define BUFPTR_FRAMETAG_MASK 0x0000001f
331 #define BUFPTR_SBYTES_MASK 0x00000fe0
332 #define BUFPTR_SBYTES_SH 5
333 } EHCIqh;
334
335 /* EHCI spec version 1.0 Section 3.7
336 */
337 typedef struct EHCIfstn {
338 uint32_t next; // Standard next link pointer
339 uint32_t backptr; // Standard next link pointer
340 } EHCIfstn;
341
342 typedef struct EHCIPacket EHCIPacket;
343 typedef struct EHCIQueue EHCIQueue;
344 typedef struct EHCIState EHCIState;
345
346 enum async_state {
347 EHCI_ASYNC_NONE = 0,
348 EHCI_ASYNC_INFLIGHT,
349 EHCI_ASYNC_FINISHED,
350 };
351
352 struct EHCIPacket {
353 EHCIQueue *queue;
354 QTAILQ_ENTRY(EHCIPacket) next;
355
356 EHCIqtd qtd; /* copy of current QTD (being worked on) */
357 uint32_t qtdaddr; /* address QTD read from */
358
359 USBPacket packet;
360 QEMUSGList sgl;
361 int pid;
362 uint32_t tbytes;
363 enum async_state async;
364 int usb_status;
365 };
366
367 struct EHCIQueue {
368 EHCIState *ehci;
369 QTAILQ_ENTRY(EHCIQueue) next;
370 uint32_t seen;
371 uint64_t ts;
372 int async;
373
374 /* cached data from guest - needs to be flushed
375 * when guest removes an entry (doorbell, handshake sequence)
376 */
377 EHCIqh qh; /* copy of current QH (being worked on) */
378 uint32_t qhaddr; /* address QH read from */
379 uint32_t qtdaddr; /* address QTD read from */
380 USBDevice *dev;
381 QTAILQ_HEAD(, EHCIPacket) packets;
382 };
383
384 typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead;
385
386 struct EHCIState {
387 PCIDevice dev;
388 USBBus bus;
389 qemu_irq irq;
390 MemoryRegion mem;
391 int companion_count;
392
393 /* properties */
394 uint32_t maxframes;
395
396 /*
397 * EHCI spec version 1.0 Section 2.3
398 * Host Controller Operational Registers
399 */
400 union {
401 uint8_t mmio[MMIO_SIZE];
402 struct {
403 uint8_t cap[OPREGBASE];
404 uint32_t usbcmd;
405 uint32_t usbsts;
406 uint32_t usbintr;
407 uint32_t frindex;
408 uint32_t ctrldssegment;
409 uint32_t periodiclistbase;
410 uint32_t asynclistaddr;
411 uint32_t notused[9];
412 uint32_t configflag;
413 uint32_t portsc[NB_PORTS];
414 };
415 };
416
417 /*
418 * Internal states, shadow registers, etc
419 */
420 QEMUTimer *frame_timer;
421 QEMUBH *async_bh;
422 uint32_t astate; /* Current state in asynchronous schedule */
423 uint32_t pstate; /* Current state in periodic schedule */
424 USBPort ports[NB_PORTS];
425 USBPort *companion_ports[NB_PORTS];
426 uint32_t usbsts_pending;
427 uint32_t usbsts_frindex;
428 EHCIQueueHead aqueues;
429 EHCIQueueHead pqueues;
430
431 /* which address to look at next */
432 uint32_t a_fetch_addr;
433 uint32_t p_fetch_addr;
434
435 USBPacket ipacket;
436 QEMUSGList isgl;
437
438 uint64_t last_run_ns;
439 uint32_t async_stepdown;
440 };
441
442 #define SET_LAST_RUN_CLOCK(s) \
443 (s)->last_run_ns = qemu_get_clock_ns(vm_clock);
444
445 /* nifty macros from Arnon's EHCI version */
446 #define get_field(data, field) \
447 (((data) & field##_MASK) >> field##_SH)
448
449 #define set_field(data, newval, field) do { \
450 uint32_t val = *data; \
451 val &= ~ field##_MASK; \
452 val |= ((newval) << field##_SH) & field##_MASK; \
453 *data = val; \
454 } while(0)
455
456 static const char *ehci_state_names[] = {
457 [EST_INACTIVE] = "INACTIVE",
458 [EST_ACTIVE] = "ACTIVE",
459 [EST_EXECUTING] = "EXECUTING",
460 [EST_SLEEPING] = "SLEEPING",
461 [EST_WAITLISTHEAD] = "WAITLISTHEAD",
462 [EST_FETCHENTRY] = "FETCH ENTRY",
463 [EST_FETCHQH] = "FETCH QH",
464 [EST_FETCHITD] = "FETCH ITD",
465 [EST_ADVANCEQUEUE] = "ADVANCEQUEUE",
466 [EST_FETCHQTD] = "FETCH QTD",
467 [EST_EXECUTE] = "EXECUTE",
468 [EST_WRITEBACK] = "WRITEBACK",
469 [EST_HORIZONTALQH] = "HORIZONTALQH",
470 };
471
472 static const char *ehci_mmio_names[] = {
473 [CAPLENGTH] = "CAPLENGTH",
474 [HCIVERSION] = "HCIVERSION",
475 [HCSPARAMS] = "HCSPARAMS",
476 [HCCPARAMS] = "HCCPARAMS",
477 [USBCMD] = "USBCMD",
478 [USBSTS] = "USBSTS",
479 [USBINTR] = "USBINTR",
480 [FRINDEX] = "FRINDEX",
481 [PERIODICLISTBASE] = "P-LIST BASE",
482 [ASYNCLISTADDR] = "A-LIST ADDR",
483 [PORTSC_BEGIN] = "PORTSC #0",
484 [PORTSC_BEGIN + 4] = "PORTSC #1",
485 [PORTSC_BEGIN + 8] = "PORTSC #2",
486 [PORTSC_BEGIN + 12] = "PORTSC #3",
487 [PORTSC_BEGIN + 16] = "PORTSC #4",
488 [PORTSC_BEGIN + 20] = "PORTSC #5",
489 [CONFIGFLAG] = "CONFIGFLAG",
490 };
491
492 static int ehci_state_executing(EHCIQueue *q);
493 static int ehci_state_writeback(EHCIQueue *q);
494
495 static const char *nr2str(const char **n, size_t len, uint32_t nr)
496 {
497 if (nr < len && n[nr] != NULL) {
498 return n[nr];
499 } else {
500 return "unknown";
501 }
502 }
503
504 static const char *state2str(uint32_t state)
505 {
506 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
507 }
508
509 static const char *addr2str(target_phys_addr_t addr)
510 {
511 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
512 }
513
514 static void ehci_trace_usbsts(uint32_t mask, int state)
515 {
516 /* interrupts */
517 if (mask & USBSTS_INT) {
518 trace_usb_ehci_usbsts("INT", state);
519 }
520 if (mask & USBSTS_ERRINT) {
521 trace_usb_ehci_usbsts("ERRINT", state);
522 }
523 if (mask & USBSTS_PCD) {
524 trace_usb_ehci_usbsts("PCD", state);
525 }
526 if (mask & USBSTS_FLR) {
527 trace_usb_ehci_usbsts("FLR", state);
528 }
529 if (mask & USBSTS_HSE) {
530 trace_usb_ehci_usbsts("HSE", state);
531 }
532 if (mask & USBSTS_IAA) {
533 trace_usb_ehci_usbsts("IAA", state);
534 }
535
536 /* status */
537 if (mask & USBSTS_HALT) {
538 trace_usb_ehci_usbsts("HALT", state);
539 }
540 if (mask & USBSTS_REC) {
541 trace_usb_ehci_usbsts("REC", state);
542 }
543 if (mask & USBSTS_PSS) {
544 trace_usb_ehci_usbsts("PSS", state);
545 }
546 if (mask & USBSTS_ASS) {
547 trace_usb_ehci_usbsts("ASS", state);
548 }
549 }
550
551 static inline void ehci_set_usbsts(EHCIState *s, int mask)
552 {
553 if ((s->usbsts & mask) == mask) {
554 return;
555 }
556 ehci_trace_usbsts(mask, 1);
557 s->usbsts |= mask;
558 }
559
560 static inline void ehci_clear_usbsts(EHCIState *s, int mask)
561 {
562 if ((s->usbsts & mask) == 0) {
563 return;
564 }
565 ehci_trace_usbsts(mask, 0);
566 s->usbsts &= ~mask;
567 }
568
569 /* update irq line */
570 static inline void ehci_update_irq(EHCIState *s)
571 {
572 int level = 0;
573
574 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
575 level = 1;
576 }
577
578 trace_usb_ehci_irq(level, s->frindex, s->usbsts, s->usbintr);
579 qemu_set_irq(s->irq, level);
580 }
581
582 /* flag interrupt condition */
583 static inline void ehci_raise_irq(EHCIState *s, int intr)
584 {
585 if (intr & (USBSTS_PCD | USBSTS_FLR | USBSTS_HSE)) {
586 s->usbsts |= intr;
587 ehci_update_irq(s);
588 } else {
589 s->usbsts_pending |= intr;
590 }
591 }
592
593 /*
594 * Commit pending interrupts (added via ehci_raise_irq),
595 * at the rate allowed by "Interrupt Threshold Control".
596 */
597 static inline void ehci_commit_irq(EHCIState *s)
598 {
599 uint32_t itc;
600
601 if (!s->usbsts_pending) {
602 return;
603 }
604 if (s->usbsts_frindex > s->frindex) {
605 return;
606 }
607
608 itc = (s->usbcmd >> 16) & 0xff;
609 s->usbsts |= s->usbsts_pending;
610 s->usbsts_pending = 0;
611 s->usbsts_frindex = s->frindex + itc;
612 ehci_update_irq(s);
613 }
614
615 static void ehci_update_halt(EHCIState *s)
616 {
617 if (s->usbcmd & USBCMD_RUNSTOP) {
618 ehci_clear_usbsts(s, USBSTS_HALT);
619 } else {
620 if (s->astate == EST_INACTIVE && s->pstate == EST_INACTIVE) {
621 ehci_set_usbsts(s, USBSTS_HALT);
622 }
623 }
624 }
625
626 static void ehci_set_state(EHCIState *s, int async, int state)
627 {
628 if (async) {
629 trace_usb_ehci_state("async", state2str(state));
630 s->astate = state;
631 if (s->astate == EST_INACTIVE) {
632 ehci_clear_usbsts(s, USBSTS_ASS);
633 ehci_update_halt(s);
634 } else {
635 ehci_set_usbsts(s, USBSTS_ASS);
636 }
637 } else {
638 trace_usb_ehci_state("periodic", state2str(state));
639 s->pstate = state;
640 if (s->pstate == EST_INACTIVE) {
641 ehci_clear_usbsts(s, USBSTS_PSS);
642 ehci_update_halt(s);
643 } else {
644 ehci_set_usbsts(s, USBSTS_PSS);
645 }
646 }
647 }
648
649 static int ehci_get_state(EHCIState *s, int async)
650 {
651 return async ? s->astate : s->pstate;
652 }
653
654 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr)
655 {
656 if (async) {
657 s->a_fetch_addr = addr;
658 } else {
659 s->p_fetch_addr = addr;
660 }
661 }
662
663 static int ehci_get_fetch_addr(EHCIState *s, int async)
664 {
665 return async ? s->a_fetch_addr : s->p_fetch_addr;
666 }
667
668 static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh)
669 {
670 /* need three here due to argument count limits */
671 trace_usb_ehci_qh_ptrs(q, addr, qh->next,
672 qh->current_qtd, qh->next_qtd, qh->altnext_qtd);
673 trace_usb_ehci_qh_fields(addr,
674 get_field(qh->epchar, QH_EPCHAR_RL),
675 get_field(qh->epchar, QH_EPCHAR_MPLEN),
676 get_field(qh->epchar, QH_EPCHAR_EPS),
677 get_field(qh->epchar, QH_EPCHAR_EP),
678 get_field(qh->epchar, QH_EPCHAR_DEVADDR));
679 trace_usb_ehci_qh_bits(addr,
680 (bool)(qh->epchar & QH_EPCHAR_C),
681 (bool)(qh->epchar & QH_EPCHAR_H),
682 (bool)(qh->epchar & QH_EPCHAR_DTC),
683 (bool)(qh->epchar & QH_EPCHAR_I));
684 }
685
686 static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd)
687 {
688 /* need three here due to argument count limits */
689 trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext);
690 trace_usb_ehci_qtd_fields(addr,
691 get_field(qtd->token, QTD_TOKEN_TBYTES),
692 get_field(qtd->token, QTD_TOKEN_CPAGE),
693 get_field(qtd->token, QTD_TOKEN_CERR),
694 get_field(qtd->token, QTD_TOKEN_PID));
695 trace_usb_ehci_qtd_bits(addr,
696 (bool)(qtd->token & QTD_TOKEN_IOC),
697 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
698 (bool)(qtd->token & QTD_TOKEN_HALT),
699 (bool)(qtd->token & QTD_TOKEN_BABBLE),
700 (bool)(qtd->token & QTD_TOKEN_XACTERR));
701 }
702
703 static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
704 {
705 trace_usb_ehci_itd(addr, itd->next,
706 get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
707 get_field(itd->bufptr[2], ITD_BUFPTR_MULT),
708 get_field(itd->bufptr[0], ITD_BUFPTR_EP),
709 get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
710 }
711
712 static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr,
713 EHCIsitd *sitd)
714 {
715 trace_usb_ehci_sitd(addr, sitd->next,
716 (bool)(sitd->results & SITD_RESULTS_ACTIVE));
717 }
718
719 static void ehci_trace_guest_bug(EHCIState *s, const char *message)
720 {
721 trace_usb_ehci_guest_bug(message);
722 fprintf(stderr, "ehci warning: %s\n", message);
723 }
724
725 static inline bool ehci_enabled(EHCIState *s)
726 {
727 return s->usbcmd & USBCMD_RUNSTOP;
728 }
729
730 static inline bool ehci_async_enabled(EHCIState *s)
731 {
732 return ehci_enabled(s) && (s->usbcmd & USBCMD_ASE);
733 }
734
735 static inline bool ehci_periodic_enabled(EHCIState *s)
736 {
737 return ehci_enabled(s) && (s->usbcmd & USBCMD_PSE);
738 }
739
740 /* packet management */
741
742 static EHCIPacket *ehci_alloc_packet(EHCIQueue *q)
743 {
744 EHCIPacket *p;
745
746 p = g_new0(EHCIPacket, 1);
747 p->queue = q;
748 usb_packet_init(&p->packet);
749 QTAILQ_INSERT_TAIL(&q->packets, p, next);
750 trace_usb_ehci_packet_action(p->queue, p, "alloc");
751 return p;
752 }
753
754 static void ehci_free_packet(EHCIPacket *p)
755 {
756 if (p->async == EHCI_ASYNC_FINISHED) {
757 int state = ehci_get_state(p->queue->ehci, p->queue->async);
758 /* This is a normal, but rare condition (cancel racing completion) */
759 fprintf(stderr, "EHCI: Warning packet completed but not processed\n");
760 ehci_state_executing(p->queue);
761 ehci_state_writeback(p->queue);
762 ehci_set_state(p->queue->ehci, p->queue->async, state);
763 /* state_writeback recurses into us with async == EHCI_ASYNC_NONE!! */
764 return;
765 }
766 trace_usb_ehci_packet_action(p->queue, p, "free");
767 if (p->async == EHCI_ASYNC_INFLIGHT) {
768 usb_cancel_packet(&p->packet);
769 usb_packet_unmap(&p->packet, &p->sgl);
770 qemu_sglist_destroy(&p->sgl);
771 }
772 QTAILQ_REMOVE(&p->queue->packets, p, next);
773 usb_packet_cleanup(&p->packet);
774 g_free(p);
775 }
776
777 /* queue management */
778
779 static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint32_t addr, int async)
780 {
781 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
782 EHCIQueue *q;
783
784 q = g_malloc0(sizeof(*q));
785 q->ehci = ehci;
786 q->qhaddr = addr;
787 q->async = async;
788 QTAILQ_INIT(&q->packets);
789 QTAILQ_INSERT_HEAD(head, q, next);
790 trace_usb_ehci_queue_action(q, "alloc");
791 return q;
792 }
793
794 static int ehci_cancel_queue(EHCIQueue *q)
795 {
796 EHCIPacket *p;
797 int packets = 0;
798
799 p = QTAILQ_FIRST(&q->packets);
800 if (p == NULL) {
801 return 0;
802 }
803
804 trace_usb_ehci_queue_action(q, "cancel");
805 do {
806 ehci_free_packet(p);
807 packets++;
808 } while ((p = QTAILQ_FIRST(&q->packets)) != NULL);
809 return packets;
810 }
811
812 static int ehci_reset_queue(EHCIQueue *q)
813 {
814 int packets;
815
816 trace_usb_ehci_queue_action(q, "reset");
817 packets = ehci_cancel_queue(q);
818 q->dev = NULL;
819 q->qtdaddr = 0;
820 return packets;
821 }
822
823 static void ehci_free_queue(EHCIQueue *q)
824 {
825 EHCIQueueHead *head = q->async ? &q->ehci->aqueues : &q->ehci->pqueues;
826
827 trace_usb_ehci_queue_action(q, "free");
828 ehci_cancel_queue(q);
829 QTAILQ_REMOVE(head, q, next);
830 g_free(q);
831 }
832
833 static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr,
834 int async)
835 {
836 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
837 EHCIQueue *q;
838
839 QTAILQ_FOREACH(q, head, next) {
840 if (addr == q->qhaddr) {
841 return q;
842 }
843 }
844 return NULL;
845 }
846
847 static void ehci_queues_rip_unused(EHCIState *ehci, int async, int flush)
848 {
849 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
850 uint64_t maxage = FRAME_TIMER_NS * ehci->maxframes * 4;
851 EHCIQueue *q, *tmp;
852
853 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
854 if (q->seen) {
855 q->seen = 0;
856 q->ts = ehci->last_run_ns;
857 continue;
858 }
859 if (!flush && ehci->last_run_ns < q->ts + maxage) {
860 continue;
861 }
862 ehci_free_queue(q);
863 }
864 }
865
866 static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async)
867 {
868 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
869 EHCIQueue *q, *tmp;
870
871 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
872 if (q->dev != dev) {
873 continue;
874 }
875 ehci_free_queue(q);
876 }
877 }
878
879 static void ehci_queues_rip_all(EHCIState *ehci, int async)
880 {
881 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
882 EHCIQueue *q, *tmp;
883
884 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
885 ehci_free_queue(q);
886 }
887 }
888
889 /* Attach or detach a device on root hub */
890
891 static void ehci_attach(USBPort *port)
892 {
893 EHCIState *s = port->opaque;
894 uint32_t *portsc = &s->portsc[port->index];
895 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci";
896
897 trace_usb_ehci_port_attach(port->index, owner, port->dev->product_desc);
898
899 if (*portsc & PORTSC_POWNER) {
900 USBPort *companion = s->companion_ports[port->index];
901 companion->dev = port->dev;
902 companion->ops->attach(companion);
903 return;
904 }
905
906 *portsc |= PORTSC_CONNECT;
907 *portsc |= PORTSC_CSC;
908
909 ehci_raise_irq(s, USBSTS_PCD);
910 ehci_commit_irq(s);
911 }
912
913 static void ehci_detach(USBPort *port)
914 {
915 EHCIState *s = port->opaque;
916 uint32_t *portsc = &s->portsc[port->index];
917 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci";
918
919 trace_usb_ehci_port_detach(port->index, owner);
920
921 if (*portsc & PORTSC_POWNER) {
922 USBPort *companion = s->companion_ports[port->index];
923 companion->ops->detach(companion);
924 companion->dev = NULL;
925 /*
926 * EHCI spec 4.2.2: "When a disconnect occurs... On the event,
927 * the port ownership is returned immediately to the EHCI controller."
928 */
929 *portsc &= ~PORTSC_POWNER;
930 return;
931 }
932
933 ehci_queues_rip_device(s, port->dev, 0);
934 ehci_queues_rip_device(s, port->dev, 1);
935
936 *portsc &= ~(PORTSC_CONNECT|PORTSC_PED);
937 *portsc |= PORTSC_CSC;
938
939 ehci_raise_irq(s, USBSTS_PCD);
940 ehci_commit_irq(s);
941 }
942
943 static void ehci_child_detach(USBPort *port, USBDevice *child)
944 {
945 EHCIState *s = port->opaque;
946 uint32_t portsc = s->portsc[port->index];
947
948 if (portsc & PORTSC_POWNER) {
949 USBPort *companion = s->companion_ports[port->index];
950 companion->ops->child_detach(companion, child);
951 return;
952 }
953
954 ehci_queues_rip_device(s, child, 0);
955 ehci_queues_rip_device(s, child, 1);
956 }
957
958 static void ehci_wakeup(USBPort *port)
959 {
960 EHCIState *s = port->opaque;
961 uint32_t portsc = s->portsc[port->index];
962
963 if (portsc & PORTSC_POWNER) {
964 USBPort *companion = s->companion_ports[port->index];
965 if (companion->ops->wakeup) {
966 companion->ops->wakeup(companion);
967 }
968 return;
969 }
970
971 qemu_bh_schedule(s->async_bh);
972 }
973
974 static int ehci_register_companion(USBBus *bus, USBPort *ports[],
975 uint32_t portcount, uint32_t firstport)
976 {
977 EHCIState *s = container_of(bus, EHCIState, bus);
978 uint32_t i;
979
980 if (firstport + portcount > NB_PORTS) {
981 qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport",
982 "firstport on masterbus");
983 error_printf_unless_qmp(
984 "firstport value of %u makes companion take ports %u - %u, which "
985 "is outside of the valid range of 0 - %u\n", firstport, firstport,
986 firstport + portcount - 1, NB_PORTS - 1);
987 return -1;
988 }
989
990 for (i = 0; i < portcount; i++) {
991 if (s->companion_ports[firstport + i]) {
992 qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus",
993 "an USB masterbus");
994 error_printf_unless_qmp(
995 "port %u on masterbus %s already has a companion assigned\n",
996 firstport + i, bus->qbus.name);
997 return -1;
998 }
999 }
1000
1001 for (i = 0; i < portcount; i++) {
1002 s->companion_ports[firstport + i] = ports[i];
1003 s->ports[firstport + i].speedmask |=
1004 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL;
1005 /* Ensure devs attached before the initial reset go to the companion */
1006 s->portsc[firstport + i] = PORTSC_POWNER;
1007 }
1008
1009 s->companion_count++;
1010 s->mmio[0x05] = (s->companion_count << 4) | portcount;
1011
1012 return 0;
1013 }
1014
1015 static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr)
1016 {
1017 USBDevice *dev;
1018 USBPort *port;
1019 int i;
1020
1021 for (i = 0; i < NB_PORTS; i++) {
1022 port = &ehci->ports[i];
1023 if (!(ehci->portsc[i] & PORTSC_PED)) {
1024 DPRINTF("Port %d not enabled\n", i);
1025 continue;
1026 }
1027 dev = usb_find_device(port, addr);
1028 if (dev != NULL) {
1029 return dev;
1030 }
1031 }
1032 return NULL;
1033 }
1034
1035 /* 4.1 host controller initialization */
1036 static void ehci_reset(void *opaque)
1037 {
1038 EHCIState *s = opaque;
1039 int i;
1040 USBDevice *devs[NB_PORTS];
1041
1042 trace_usb_ehci_reset();
1043
1044 /*
1045 * Do the detach before touching portsc, so that it correctly gets send to
1046 * us or to our companion based on PORTSC_POWNER before the reset.
1047 */
1048 for(i = 0; i < NB_PORTS; i++) {
1049 devs[i] = s->ports[i].dev;
1050 if (devs[i] && devs[i]->attached) {
1051 usb_detach(&s->ports[i]);
1052 }
1053 }
1054
1055 memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
1056
1057 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
1058 s->usbsts = USBSTS_HALT;
1059 s->usbsts_pending = 0;
1060 s->usbsts_frindex = 0;
1061
1062 s->astate = EST_INACTIVE;
1063 s->pstate = EST_INACTIVE;
1064
1065 for(i = 0; i < NB_PORTS; i++) {
1066 if (s->companion_ports[i]) {
1067 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
1068 } else {
1069 s->portsc[i] = PORTSC_PPOWER;
1070 }
1071 if (devs[i] && devs[i]->attached) {
1072 usb_attach(&s->ports[i]);
1073 usb_device_reset(devs[i]);
1074 }
1075 }
1076 ehci_queues_rip_all(s, 0);
1077 ehci_queues_rip_all(s, 1);
1078 qemu_del_timer(s->frame_timer);
1079 qemu_bh_cancel(s->async_bh);
1080 }
1081
1082 static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
1083 {
1084 EHCIState *s = ptr;
1085 uint32_t val;
1086
1087 val = s->mmio[addr];
1088
1089 return val;
1090 }
1091
1092 static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
1093 {
1094 EHCIState *s = ptr;
1095 uint32_t val;
1096
1097 val = s->mmio[addr] | (s->mmio[addr+1] << 8);
1098
1099 return val;
1100 }
1101
1102 static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
1103 {
1104 EHCIState *s = ptr;
1105 uint32_t val;
1106
1107 val = s->mmio[addr] | (s->mmio[addr+1] << 8) |
1108 (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);
1109
1110 trace_usb_ehci_mmio_readl(addr, addr2str(addr), val);
1111 return val;
1112 }
1113
1114 static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
1115 {
1116 fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
1117 exit(1);
1118 }
1119
1120 static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
1121 {
1122 fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
1123 exit(1);
1124 }
1125
1126 static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner)
1127 {
1128 USBDevice *dev = s->ports[port].dev;
1129 uint32_t *portsc = &s->portsc[port];
1130 uint32_t orig;
1131
1132 if (s->companion_ports[port] == NULL)
1133 return;
1134
1135 owner = owner & PORTSC_POWNER;
1136 orig = *portsc & PORTSC_POWNER;
1137
1138 if (!(owner ^ orig)) {
1139 return;
1140 }
1141
1142 if (dev && dev->attached) {
1143 usb_detach(&s->ports[port]);
1144 }
1145
1146 *portsc &= ~PORTSC_POWNER;
1147 *portsc |= owner;
1148
1149 if (dev && dev->attached) {
1150 usb_attach(&s->ports[port]);
1151 }
1152 }
1153
1154 static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
1155 {
1156 uint32_t *portsc = &s->portsc[port];
1157 USBDevice *dev = s->ports[port].dev;
1158
1159 /* Clear rwc bits */
1160 *portsc &= ~(val & PORTSC_RWC_MASK);
1161 /* The guest may clear, but not set the PED bit */
1162 *portsc &= val | ~PORTSC_PED;
1163 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */
1164 handle_port_owner_write(s, port, val);
1165 /* And finally apply RO_MASK */
1166 val &= PORTSC_RO_MASK;
1167
1168 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
1169 trace_usb_ehci_port_reset(port, 1);
1170 }
1171
1172 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
1173 trace_usb_ehci_port_reset(port, 0);
1174 if (dev && dev->attached) {
1175 usb_port_reset(&s->ports[port]);
1176 *portsc &= ~PORTSC_CSC;
1177 }
1178
1179 /*
1180 * Table 2.16 Set the enable bit(and enable bit change) to indicate
1181 * to SW that this port has a high speed device attached
1182 */
1183 if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) {
1184 val |= PORTSC_PED;
1185 }
1186 }
1187
1188 *portsc &= ~PORTSC_RO_MASK;
1189 *portsc |= val;
1190 }
1191
1192 static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
1193 {
1194 EHCIState *s = ptr;
1195 uint32_t *mmio = (uint32_t *)(&s->mmio[addr]);
1196 uint32_t old = *mmio;
1197 int i;
1198
1199 trace_usb_ehci_mmio_writel(addr, addr2str(addr), val);
1200
1201 /* Only aligned reads are allowed on OHCI */
1202 if (addr & 3) {
1203 fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
1204 TARGET_FMT_plx "\n", addr);
1205 return;
1206 }
1207
1208 if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
1209 handle_port_status_write(s, (addr-PORTSC)/4, val);
1210 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1211 return;
1212 }
1213
1214 if (addr < OPREGBASE) {
1215 fprintf(stderr, "usb-ehci: write attempt to read-only register"
1216 TARGET_FMT_plx "\n", addr);
1217 return;
1218 }
1219
1220
1221 /* Do any register specific pre-write processing here. */
1222 switch(addr) {
1223 case USBCMD:
1224 if (val & USBCMD_HCRESET) {
1225 ehci_reset(s);
1226 val = s->usbcmd;
1227 break;
1228 }
1229
1230 /* not supporting dynamic frame list size at the moment */
1231 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
1232 fprintf(stderr, "attempt to set frame list size -- value %d\n",
1233 val & USBCMD_FLS);
1234 val &= ~USBCMD_FLS;
1235 }
1236
1237 if (val & USBCMD_IAAD) {
1238 /*
1239 * Process IAAD immediately, otherwise the Linux IAAD watchdog may
1240 * trigger and re-use a qh without us seeing the unlink.
1241 */
1242 s->async_stepdown = 0;
1243 qemu_bh_schedule(s->async_bh);
1244 }
1245
1246 if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & val) !=
1247 ((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) {
1248 if (s->pstate == EST_INACTIVE) {
1249 SET_LAST_RUN_CLOCK(s);
1250 }
1251 s->usbcmd = val; /* Set usbcmd for ehci_update_halt() */
1252 ehci_update_halt(s);
1253 s->async_stepdown = 0;
1254 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
1255 }
1256 break;
1257
1258 case USBSTS:
1259 val &= USBSTS_RO_MASK; // bits 6 through 31 are RO
1260 ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC
1261 val = s->usbsts;
1262 ehci_update_irq(s);
1263 break;
1264
1265 case USBINTR:
1266 val &= USBINTR_MASK;
1267 break;
1268
1269 case FRINDEX:
1270 val &= 0x00003ff8; /* frindex is 14bits and always a multiple of 8 */
1271 break;
1272
1273 case CONFIGFLAG:
1274 val &= 0x1;
1275 if (val) {
1276 for(i = 0; i < NB_PORTS; i++)
1277 handle_port_owner_write(s, i, 0);
1278 }
1279 break;
1280
1281 case PERIODICLISTBASE:
1282 if (ehci_periodic_enabled(s)) {
1283 fprintf(stderr,
1284 "ehci: PERIODIC list base register set while periodic schedule\n"
1285 " is enabled and HC is enabled\n");
1286 }
1287 break;
1288
1289 case ASYNCLISTADDR:
1290 if (ehci_async_enabled(s)) {
1291 fprintf(stderr,
1292 "ehci: ASYNC list address register set while async schedule\n"
1293 " is enabled and HC is enabled\n");
1294 }
1295 break;
1296 }
1297
1298 *mmio = val;
1299 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1300 }
1301
1302
1303 // TODO : Put in common header file, duplication from usb-ohci.c
1304
1305 /* Get an array of dwords from main memory */
1306 static inline int get_dwords(EHCIState *ehci, uint32_t addr,
1307 uint32_t *buf, int num)
1308 {
1309 int i;
1310
1311 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1312 pci_dma_read(&ehci->dev, addr, buf, sizeof(*buf));
1313 *buf = le32_to_cpu(*buf);
1314 }
1315
1316 return 1;
1317 }
1318
1319 /* Put an array of dwords in to main memory */
1320 static inline int put_dwords(EHCIState *ehci, uint32_t addr,
1321 uint32_t *buf, int num)
1322 {
1323 int i;
1324
1325 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1326 uint32_t tmp = cpu_to_le32(*buf);
1327 pci_dma_write(&ehci->dev, addr, &tmp, sizeof(tmp));
1328 }
1329
1330 return 1;
1331 }
1332
1333 /*
1334 * Write the qh back to guest physical memory. This step isn't
1335 * in the EHCI spec but we need to do it since we don't share
1336 * physical memory with our guest VM.
1337 *
1338 * The first three dwords are read-only for the EHCI, so skip them
1339 * when writing back the qh.
1340 */
1341 static void ehci_flush_qh(EHCIQueue *q)
1342 {
1343 uint32_t *qh = (uint32_t *) &q->qh;
1344 uint32_t dwords = sizeof(EHCIqh) >> 2;
1345 uint32_t addr = NLPTR_GET(q->qhaddr);
1346
1347 put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3);
1348 }
1349
1350 // 4.10.2
1351
1352 static int ehci_qh_do_overlay(EHCIQueue *q)
1353 {
1354 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1355 int i;
1356 int dtoggle;
1357 int ping;
1358 int eps;
1359 int reload;
1360
1361 assert(p != NULL);
1362 assert(p->qtdaddr == q->qtdaddr);
1363
1364 // remember values in fields to preserve in qh after overlay
1365
1366 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE;
1367 ping = q->qh.token & QTD_TOKEN_PING;
1368
1369 q->qh.current_qtd = p->qtdaddr;
1370 q->qh.next_qtd = p->qtd.next;
1371 q->qh.altnext_qtd = p->qtd.altnext;
1372 q->qh.token = p->qtd.token;
1373
1374
1375 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS);
1376 if (eps == EHCI_QH_EPS_HIGH) {
1377 q->qh.token &= ~QTD_TOKEN_PING;
1378 q->qh.token |= ping;
1379 }
1380
1381 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1382 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1383
1384 for (i = 0; i < 5; i++) {
1385 q->qh.bufptr[i] = p->qtd.bufptr[i];
1386 }
1387
1388 if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
1389 // preserve QH DT bit
1390 q->qh.token &= ~QTD_TOKEN_DTOGGLE;
1391 q->qh.token |= dtoggle;
1392 }
1393
1394 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
1395 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
1396
1397 ehci_flush_qh(q);
1398
1399 return 0;
1400 }
1401
1402 static int ehci_init_transfer(EHCIPacket *p)
1403 {
1404 uint32_t cpage, offset, bytes, plen;
1405 dma_addr_t page;
1406
1407 cpage = get_field(p->qtd.token, QTD_TOKEN_CPAGE);
1408 bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES);
1409 offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK;
1410 pci_dma_sglist_init(&p->sgl, &p->queue->ehci->dev, 5);
1411
1412 while (bytes > 0) {
1413 if (cpage > 4) {
1414 fprintf(stderr, "cpage out of range (%d)\n", cpage);
1415 return USB_RET_PROCERR;
1416 }
1417
1418 page = p->qtd.bufptr[cpage] & QTD_BUFPTR_MASK;
1419 page += offset;
1420 plen = bytes;
1421 if (plen > 4096 - offset) {
1422 plen = 4096 - offset;
1423 offset = 0;
1424 cpage++;
1425 }
1426
1427 qemu_sglist_add(&p->sgl, page, plen);
1428 bytes -= plen;
1429 }
1430 return 0;
1431 }
1432
1433 static void ehci_finish_transfer(EHCIQueue *q, int status)
1434 {
1435 uint32_t cpage, offset;
1436
1437 if (status > 0) {
1438 /* update cpage & offset */
1439 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1440 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1441
1442 offset += status;
1443 cpage += offset >> QTD_BUFPTR_SH;
1444 offset &= ~QTD_BUFPTR_MASK;
1445
1446 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE);
1447 q->qh.bufptr[0] &= QTD_BUFPTR_MASK;
1448 q->qh.bufptr[0] |= offset;
1449 }
1450 }
1451
1452 static void ehci_async_complete_packet(USBPort *port, USBPacket *packet)
1453 {
1454 EHCIPacket *p;
1455 EHCIState *s = port->opaque;
1456 uint32_t portsc = s->portsc[port->index];
1457
1458 if (portsc & PORTSC_POWNER) {
1459 USBPort *companion = s->companion_ports[port->index];
1460 companion->ops->complete(companion, packet);
1461 return;
1462 }
1463
1464 p = container_of(packet, EHCIPacket, packet);
1465 trace_usb_ehci_packet_action(p->queue, p, "wakeup");
1466 assert(p->async == EHCI_ASYNC_INFLIGHT);
1467 p->async = EHCI_ASYNC_FINISHED;
1468 p->usb_status = packet->result;
1469
1470 if (p->queue->async) {
1471 qemu_bh_schedule(p->queue->ehci->async_bh);
1472 }
1473 }
1474
1475 static void ehci_execute_complete(EHCIQueue *q)
1476 {
1477 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1478
1479 assert(p != NULL);
1480 assert(p->qtdaddr == q->qtdaddr);
1481 assert(p->async != EHCI_ASYNC_INFLIGHT);
1482 p->async = EHCI_ASYNC_NONE;
1483
1484 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1485 q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status);
1486
1487 if (p->usb_status < 0) {
1488 switch (p->usb_status) {
1489 case USB_RET_IOERROR:
1490 case USB_RET_NODEV:
1491 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR);
1492 set_field(&q->qh.token, 0, QTD_TOKEN_CERR);
1493 ehci_raise_irq(q->ehci, USBSTS_ERRINT);
1494 break;
1495 case USB_RET_STALL:
1496 q->qh.token |= QTD_TOKEN_HALT;
1497 ehci_raise_irq(q->ehci, USBSTS_ERRINT);
1498 break;
1499 case USB_RET_NAK:
1500 set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT);
1501 return; /* We're not done yet with this transaction */
1502 case USB_RET_BABBLE:
1503 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1504 ehci_raise_irq(q->ehci, USBSTS_ERRINT);
1505 break;
1506 default:
1507 /* should not be triggerable */
1508 fprintf(stderr, "USB invalid response %d\n", p->usb_status);
1509 assert(0);
1510 break;
1511 }
1512 } else {
1513 // TODO check 4.12 for splits
1514
1515 if (p->tbytes && p->pid == USB_TOKEN_IN) {
1516 p->tbytes -= p->usb_status;
1517 } else {
1518 p->tbytes = 0;
1519 }
1520
1521 DPRINTF("updating tbytes to %d\n", p->tbytes);
1522 set_field(&q->qh.token, p->tbytes, QTD_TOKEN_TBYTES);
1523 }
1524 ehci_finish_transfer(q, p->usb_status);
1525 usb_packet_unmap(&p->packet, &p->sgl);
1526 qemu_sglist_destroy(&p->sgl);
1527
1528 q->qh.token ^= QTD_TOKEN_DTOGGLE;
1529 q->qh.token &= ~QTD_TOKEN_ACTIVE;
1530
1531 if (q->qh.token & QTD_TOKEN_IOC) {
1532 ehci_raise_irq(q->ehci, USBSTS_INT);
1533 }
1534 }
1535
1536 // 4.10.3
1537
1538 static int ehci_execute(EHCIPacket *p, const char *action)
1539 {
1540 USBEndpoint *ep;
1541 int ret;
1542 int endp;
1543
1544 if (!(p->qtd.token & QTD_TOKEN_ACTIVE)) {
1545 fprintf(stderr, "Attempting to execute inactive qtd\n");
1546 return USB_RET_PROCERR;
1547 }
1548
1549 p->tbytes = (p->qtd.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH;
1550 if (p->tbytes > BUFF_SIZE) {
1551 fprintf(stderr, "Request for more bytes than allowed\n");
1552 return USB_RET_PROCERR;
1553 }
1554
1555 p->pid = (p->qtd.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
1556 switch (p->pid) {
1557 case 0:
1558 p->pid = USB_TOKEN_OUT;
1559 break;
1560 case 1:
1561 p->pid = USB_TOKEN_IN;
1562 break;
1563 case 2:
1564 p->pid = USB_TOKEN_SETUP;
1565 break;
1566 default:
1567 fprintf(stderr, "bad token\n");
1568 break;
1569 }
1570
1571 if (ehci_init_transfer(p) != 0) {
1572 return USB_RET_PROCERR;
1573 }
1574
1575 endp = get_field(p->queue->qh.epchar, QH_EPCHAR_EP);
1576 ep = usb_ep_get(p->queue->dev, p->pid, endp);
1577
1578 usb_packet_setup(&p->packet, p->pid, ep, p->qtdaddr);
1579 usb_packet_map(&p->packet, &p->sgl);
1580
1581 trace_usb_ehci_packet_action(p->queue, p, action);
1582 ret = usb_handle_packet(p->queue->dev, &p->packet);
1583 DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd "
1584 "(total %d) endp %x ret %d\n",
1585 q->qhaddr, q->qh.next, q->qtdaddr, q->pid,
1586 q->packet.iov.size, q->tbytes, endp, ret);
1587
1588 if (ret > BUFF_SIZE) {
1589 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1590 return USB_RET_PROCERR;
1591 }
1592
1593 return ret;
1594 }
1595
1596 /* 4.7.2
1597 */
1598
1599 static int ehci_process_itd(EHCIState *ehci,
1600 EHCIitd *itd,
1601 uint32_t addr)
1602 {
1603 USBDevice *dev;
1604 USBEndpoint *ep;
1605 int ret;
1606 uint32_t i, len, pid, dir, devaddr, endp;
1607 uint32_t pg, off, ptr1, ptr2, max, mult;
1608
1609 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1610 devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1611 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1612 max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1613 mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);
1614
1615 for(i = 0; i < 8; i++) {
1616 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1617 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1618 off = itd->transact[i] & ITD_XACT_OFFSET_MASK;
1619 ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK);
1620 ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK);
1621 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1622
1623 if (len > max * mult) {
1624 len = max * mult;
1625 }
1626
1627 if (len > BUFF_SIZE) {
1628 return USB_RET_PROCERR;
1629 }
1630
1631 pci_dma_sglist_init(&ehci->isgl, &ehci->dev, 2);
1632 if (off + len > 4096) {
1633 /* transfer crosses page border */
1634 uint32_t len2 = off + len - 4096;
1635 uint32_t len1 = len - len2;
1636 qemu_sglist_add(&ehci->isgl, ptr1 + off, len1);
1637 qemu_sglist_add(&ehci->isgl, ptr2, len2);
1638 } else {
1639 qemu_sglist_add(&ehci->isgl, ptr1 + off, len);
1640 }
1641
1642 pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT;
1643
1644 dev = ehci_find_device(ehci, devaddr);
1645 ep = usb_ep_get(dev, pid, endp);
1646 if (ep && ep->type == USB_ENDPOINT_XFER_ISOC) {
1647 usb_packet_setup(&ehci->ipacket, pid, ep, addr);
1648 usb_packet_map(&ehci->ipacket, &ehci->isgl);
1649 ret = usb_handle_packet(dev, &ehci->ipacket);
1650 assert(ret != USB_RET_ASYNC);
1651 usb_packet_unmap(&ehci->ipacket, &ehci->isgl);
1652 } else {
1653 DPRINTF("ISOCH: attempt to addess non-iso endpoint\n");
1654 ret = USB_RET_NAK;
1655 }
1656 qemu_sglist_destroy(&ehci->isgl);
1657
1658 if (ret < 0) {
1659 switch (ret) {
1660 default:
1661 fprintf(stderr, "Unexpected iso usb result: %d\n", ret);
1662 /* Fall through */
1663 case USB_RET_IOERROR:
1664 case USB_RET_NODEV:
1665 /* 3.3.2: XACTERR is only allowed on IN transactions */
1666 if (dir) {
1667 itd->transact[i] |= ITD_XACT_XACTERR;
1668 ehci_raise_irq(ehci, USBSTS_ERRINT);
1669 }
1670 break;
1671 case USB_RET_BABBLE:
1672 itd->transact[i] |= ITD_XACT_BABBLE;
1673 ehci_raise_irq(ehci, USBSTS_ERRINT);
1674 break;
1675 case USB_RET_NAK:
1676 /* no data for us, so do a zero-length transfer */
1677 ret = 0;
1678 break;
1679 }
1680 }
1681 if (ret >= 0) {
1682 if (!dir) {
1683 /* OUT */
1684 set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH);
1685 } else {
1686 /* IN */
1687 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH);
1688 }
1689 }
1690 if (itd->transact[i] & ITD_XACT_IOC) {
1691 ehci_raise_irq(ehci, USBSTS_INT);
1692 }
1693 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1694 }
1695 }
1696 return 0;
1697 }
1698
1699
1700 /* This state is the entry point for asynchronous schedule
1701 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1702 */
1703 static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1704 {
1705 EHCIqh qh;
1706 int i = 0;
1707 int again = 0;
1708 uint32_t entry = ehci->asynclistaddr;
1709
1710 /* set reclamation flag at start event (4.8.6) */
1711 if (async) {
1712 ehci_set_usbsts(ehci, USBSTS_REC);
1713 }
1714
1715 ehci_queues_rip_unused(ehci, async, 0);
1716
1717 /* Find the head of the list (4.9.1.1) */
1718 for(i = 0; i < MAX_QH; i++) {
1719 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh,
1720 sizeof(EHCIqh) >> 2);
1721 ehci_trace_qh(NULL, NLPTR_GET(entry), &qh);
1722
1723 if (qh.epchar & QH_EPCHAR_H) {
1724 if (async) {
1725 entry |= (NLPTR_TYPE_QH << 1);
1726 }
1727
1728 ehci_set_fetch_addr(ehci, async, entry);
1729 ehci_set_state(ehci, async, EST_FETCHENTRY);
1730 again = 1;
1731 goto out;
1732 }
1733
1734 entry = qh.next;
1735 if (entry == ehci->asynclistaddr) {
1736 break;
1737 }
1738 }
1739
1740 /* no head found for list. */
1741
1742 ehci_set_state(ehci, async, EST_ACTIVE);
1743
1744 out:
1745 return again;
1746 }
1747
1748
1749 /* This state is the entry point for periodic schedule processing as
1750 * well as being a continuation state for async processing.
1751 */
1752 static int ehci_state_fetchentry(EHCIState *ehci, int async)
1753 {
1754 int again = 0;
1755 uint32_t entry = ehci_get_fetch_addr(ehci, async);
1756
1757 if (NLPTR_TBIT(entry)) {
1758 ehci_set_state(ehci, async, EST_ACTIVE);
1759 goto out;
1760 }
1761
1762 /* section 4.8, only QH in async schedule */
1763 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1764 fprintf(stderr, "non queue head request in async schedule\n");
1765 return -1;
1766 }
1767
1768 switch (NLPTR_TYPE_GET(entry)) {
1769 case NLPTR_TYPE_QH:
1770 ehci_set_state(ehci, async, EST_FETCHQH);
1771 again = 1;
1772 break;
1773
1774 case NLPTR_TYPE_ITD:
1775 ehci_set_state(ehci, async, EST_FETCHITD);
1776 again = 1;
1777 break;
1778
1779 case NLPTR_TYPE_STITD:
1780 ehci_set_state(ehci, async, EST_FETCHSITD);
1781 again = 1;
1782 break;
1783
1784 default:
1785 /* TODO: handle FSTN type */
1786 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1787 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1788 return -1;
1789 }
1790
1791 out:
1792 return again;
1793 }
1794
1795 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)
1796 {
1797 EHCIPacket *p;
1798 uint32_t entry, devaddr, endp;
1799 EHCIQueue *q;
1800 EHCIqh qh;
1801
1802 entry = ehci_get_fetch_addr(ehci, async);
1803 q = ehci_find_queue_by_qh(ehci, entry, async);
1804 if (NULL == q) {
1805 q = ehci_alloc_queue(ehci, entry, async);
1806 }
1807 p = QTAILQ_FIRST(&q->packets);
1808
1809 q->seen++;
1810 if (q->seen > 1) {
1811 /* we are going in circles -- stop processing */
1812 ehci_set_state(ehci, async, EST_ACTIVE);
1813 q = NULL;
1814 goto out;
1815 }
1816
1817 get_dwords(ehci, NLPTR_GET(q->qhaddr),
1818 (uint32_t *) &qh, sizeof(EHCIqh) >> 2);
1819 ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &qh);
1820
1821 /*
1822 * The overlay area of the qh should never be changed by the guest,
1823 * except when idle, in which case the reset is a nop.
1824 */
1825 devaddr = get_field(qh.epchar, QH_EPCHAR_DEVADDR);
1826 endp = get_field(qh.epchar, QH_EPCHAR_EP);
1827 if ((devaddr != get_field(q->qh.epchar, QH_EPCHAR_DEVADDR)) ||
1828 (endp != get_field(q->qh.epchar, QH_EPCHAR_EP)) ||
1829 (memcmp(&qh.current_qtd, &q->qh.current_qtd,
1830 9 * sizeof(uint32_t)) != 0) ||
1831 (q->dev != NULL && q->dev->addr != devaddr)) {
1832 if (ehci_reset_queue(q) > 0) {
1833 ehci_trace_guest_bug(ehci, "guest updated active QH");
1834 }
1835 p = NULL;
1836 }
1837 q->qh = qh;
1838
1839 if (q->dev == NULL) {
1840 q->dev = ehci_find_device(q->ehci, devaddr);
1841 }
1842
1843 if (p && p->async == EHCI_ASYNC_FINISHED) {
1844 /* I/O finished -- continue processing queue */
1845 trace_usb_ehci_packet_action(p->queue, p, "complete");
1846 ehci_set_state(ehci, async, EST_EXECUTING);
1847 goto out;
1848 }
1849
1850 if (async && (q->qh.epchar & QH_EPCHAR_H)) {
1851
1852 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1853 if (ehci->usbsts & USBSTS_REC) {
1854 ehci_clear_usbsts(ehci, USBSTS_REC);
1855 } else {
1856 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1857 " - done processing\n", q->qhaddr);
1858 ehci_set_state(ehci, async, EST_ACTIVE);
1859 q = NULL;
1860 goto out;
1861 }
1862 }
1863
1864 #if EHCI_DEBUG
1865 if (q->qhaddr != q->qh.next) {
1866 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1867 q->qhaddr,
1868 q->qh.epchar & QH_EPCHAR_H,
1869 q->qh.token & QTD_TOKEN_HALT,
1870 q->qh.token & QTD_TOKEN_ACTIVE,
1871 q->qh.next);
1872 }
1873 #endif
1874
1875 if (q->qh.token & QTD_TOKEN_HALT) {
1876 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1877
1878 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) &&
1879 (NLPTR_TBIT(q->qh.current_qtd) == 0)) {
1880 q->qtdaddr = q->qh.current_qtd;
1881 ehci_set_state(ehci, async, EST_FETCHQTD);
1882
1883 } else {
1884 /* EHCI spec version 1.0 Section 4.10.2 */
1885 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1886 }
1887
1888 out:
1889 return q;
1890 }
1891
1892 static int ehci_state_fetchitd(EHCIState *ehci, int async)
1893 {
1894 uint32_t entry;
1895 EHCIitd itd;
1896
1897 assert(!async);
1898 entry = ehci_get_fetch_addr(ehci, async);
1899
1900 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1901 sizeof(EHCIitd) >> 2);
1902 ehci_trace_itd(ehci, entry, &itd);
1903
1904 if (ehci_process_itd(ehci, &itd, entry) != 0) {
1905 return -1;
1906 }
1907
1908 put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1909 sizeof(EHCIitd) >> 2);
1910 ehci_set_fetch_addr(ehci, async, itd.next);
1911 ehci_set_state(ehci, async, EST_FETCHENTRY);
1912
1913 return 1;
1914 }
1915
1916 static int ehci_state_fetchsitd(EHCIState *ehci, int async)
1917 {
1918 uint32_t entry;
1919 EHCIsitd sitd;
1920
1921 assert(!async);
1922 entry = ehci_get_fetch_addr(ehci, async);
1923
1924 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd,
1925 sizeof(EHCIsitd) >> 2);
1926 ehci_trace_sitd(ehci, entry, &sitd);
1927
1928 if (!(sitd.results & SITD_RESULTS_ACTIVE)) {
1929 /* siTD is not active, nothing to do */;
1930 } else {
1931 /* TODO: split transfers are not implemented */
1932 fprintf(stderr, "WARNING: Skipping active siTD\n");
1933 }
1934
1935 ehci_set_fetch_addr(ehci, async, sitd.next);
1936 ehci_set_state(ehci, async, EST_FETCHENTRY);
1937 return 1;
1938 }
1939
1940 /* Section 4.10.2 - paragraph 3 */
1941 static int ehci_state_advqueue(EHCIQueue *q)
1942 {
1943 #if 0
1944 /* TO-DO: 4.10.2 - paragraph 2
1945 * if I-bit is set to 1 and QH is not active
1946 * go to horizontal QH
1947 */
1948 if (I-bit set) {
1949 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1950 goto out;
1951 }
1952 #endif
1953
1954 /*
1955 * want data and alt-next qTD is valid
1956 */
1957 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1958 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
1959 q->qtdaddr = q->qh.altnext_qtd;
1960 ehci_set_state(q->ehci, q->async, EST_FETCHQTD);
1961
1962 /*
1963 * next qTD is valid
1964 */
1965 } else if (NLPTR_TBIT(q->qh.next_qtd) == 0) {
1966 q->qtdaddr = q->qh.next_qtd;
1967 ehci_set_state(q->ehci, q->async, EST_FETCHQTD);
1968
1969 /*
1970 * no valid qTD, try next QH
1971 */
1972 } else {
1973 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1974 }
1975
1976 return 1;
1977 }
1978
1979 /* Section 4.10.2 - paragraph 4 */
1980 static int ehci_state_fetchqtd(EHCIQueue *q)
1981 {
1982 EHCIqtd qtd;
1983 EHCIPacket *p;
1984 int again = 0;
1985
1986 get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &qtd,
1987 sizeof(EHCIqtd) >> 2);
1988 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &qtd);
1989
1990 p = QTAILQ_FIRST(&q->packets);
1991 if (p != NULL) {
1992 if (p->qtdaddr != q->qtdaddr ||
1993 (!NLPTR_TBIT(p->qtd.next) && (p->qtd.next != qtd.next)) ||
1994 (!NLPTR_TBIT(p->qtd.altnext) && (p->qtd.altnext != qtd.altnext)) ||
1995 p->qtd.bufptr[0] != qtd.bufptr[0]) {
1996 ehci_cancel_queue(q);
1997 ehci_trace_guest_bug(q->ehci, "guest updated active QH or qTD");
1998 p = NULL;
1999 } else {
2000 p->qtd = qtd;
2001 ehci_qh_do_overlay(q);
2002 }
2003 }
2004
2005 if (!(qtd.token & QTD_TOKEN_ACTIVE)) {
2006 if (p != NULL) {
2007 /* transfer canceled by guest (clear active) */
2008 ehci_cancel_queue(q);
2009 p = NULL;
2010 }
2011 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2012 again = 1;
2013 } else if (p != NULL) {
2014 switch (p->async) {
2015 case EHCI_ASYNC_NONE:
2016 /* Previously nacked packet (likely interrupt ep) */
2017 ehci_set_state(q->ehci, q->async, EST_EXECUTE);
2018 break;
2019 case EHCI_ASYNC_INFLIGHT:
2020 /* Unfinyshed async handled packet, go horizontal */
2021 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2022 break;
2023 case EHCI_ASYNC_FINISHED:
2024 /* Should never happen, as this case is caught by fetchqh */
2025 ehci_set_state(q->ehci, q->async, EST_EXECUTING);
2026 break;
2027 }
2028 again = 1;
2029 } else {
2030 p = ehci_alloc_packet(q);
2031 p->qtdaddr = q->qtdaddr;
2032 p->qtd = qtd;
2033 ehci_set_state(q->ehci, q->async, EST_EXECUTE);
2034 again = 1;
2035 }
2036
2037 return again;
2038 }
2039
2040 static int ehci_state_horizqh(EHCIQueue *q)
2041 {
2042 int again = 0;
2043
2044 if (ehci_get_fetch_addr(q->ehci, q->async) != q->qh.next) {
2045 ehci_set_fetch_addr(q->ehci, q->async, q->qh.next);
2046 ehci_set_state(q->ehci, q->async, EST_FETCHENTRY);
2047 again = 1;
2048 } else {
2049 ehci_set_state(q->ehci, q->async, EST_ACTIVE);
2050 }
2051
2052 return again;
2053 }
2054
2055 static void ehci_fill_queue(EHCIPacket *p)
2056 {
2057 EHCIQueue *q = p->queue;
2058 EHCIqtd qtd = p->qtd;
2059 uint32_t qtdaddr;
2060
2061 for (;;) {
2062 if (NLPTR_TBIT(qtd.altnext) == 0) {
2063 break;
2064 }
2065 if (NLPTR_TBIT(qtd.next) != 0) {
2066 break;
2067 }
2068 qtdaddr = qtd.next;
2069 get_dwords(q->ehci, NLPTR_GET(qtdaddr),
2070 (uint32_t *) &qtd, sizeof(EHCIqtd) >> 2);
2071 ehci_trace_qtd(q, NLPTR_GET(qtdaddr), &qtd);
2072 if (!(qtd.token & QTD_TOKEN_ACTIVE)) {
2073 break;
2074 }
2075 p = ehci_alloc_packet(q);
2076 p->qtdaddr = qtdaddr;
2077 p->qtd = qtd;
2078 p->usb_status = ehci_execute(p, "queue");
2079 assert(p->usb_status == USB_RET_ASYNC);
2080 p->async = EHCI_ASYNC_INFLIGHT;
2081 }
2082 }
2083
2084 static int ehci_state_execute(EHCIQueue *q)
2085 {
2086 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
2087 int again = 0;
2088
2089 assert(p != NULL);
2090 assert(p->qtdaddr == q->qtdaddr);
2091
2092 if (ehci_qh_do_overlay(q) != 0) {
2093 return -1;
2094 }
2095
2096 // TODO verify enough time remains in the uframe as in 4.4.1.1
2097 // TODO write back ptr to async list when done or out of time
2098 // TODO Windows does not seem to ever set the MULT field
2099
2100 if (!q->async) {
2101 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
2102 if (!transactCtr) {
2103 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2104 again = 1;
2105 goto out;
2106 }
2107 }
2108
2109 if (q->async) {
2110 ehci_set_usbsts(q->ehci, USBSTS_REC);
2111 }
2112
2113 p->usb_status = ehci_execute(p, "process");
2114 if (p->usb_status == USB_RET_PROCERR) {
2115 again = -1;
2116 goto out;
2117 }
2118 if (p->usb_status == USB_RET_ASYNC) {
2119 ehci_flush_qh(q);
2120 trace_usb_ehci_packet_action(p->queue, p, "async");
2121 p->async = EHCI_ASYNC_INFLIGHT;
2122 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2123 again = 1;
2124 ehci_fill_queue(p);
2125 goto out;
2126 }
2127
2128 ehci_set_state(q->ehci, q->async, EST_EXECUTING);
2129 again = 1;
2130
2131 out:
2132 return again;
2133 }
2134
2135 static int ehci_state_executing(EHCIQueue *q)
2136 {
2137 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
2138
2139 assert(p != NULL);
2140 assert(p->qtdaddr == q->qtdaddr);
2141
2142 ehci_execute_complete(q);
2143
2144 // 4.10.3
2145 if (!q->async) {
2146 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
2147 transactCtr--;
2148 set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT);
2149 // 4.10.3, bottom of page 82, should exit this state when transaction
2150 // counter decrements to 0
2151 }
2152
2153 /* 4.10.5 */
2154 if (p->usb_status == USB_RET_NAK) {
2155 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2156 } else {
2157 ehci_set_state(q->ehci, q->async, EST_WRITEBACK);
2158 }
2159
2160 ehci_flush_qh(q);
2161 return 1;
2162 }
2163
2164
2165 static int ehci_state_writeback(EHCIQueue *q)
2166 {
2167 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
2168 uint32_t *qtd, addr;
2169 int again = 0;
2170
2171 /* Write back the QTD from the QH area */
2172 assert(p != NULL);
2173 assert(p->qtdaddr == q->qtdaddr);
2174
2175 ehci_trace_qtd(q, NLPTR_GET(p->qtdaddr), (EHCIqtd *) &q->qh.next_qtd);
2176 qtd = (uint32_t *) &q->qh.next_qtd;
2177 addr = NLPTR_GET(p->qtdaddr);
2178 put_dwords(q->ehci, addr + 2 * sizeof(uint32_t), qtd + 2, 2);
2179 ehci_free_packet(p);
2180
2181 /*
2182 * EHCI specs say go horizontal here.
2183 *
2184 * We can also advance the queue here for performance reasons. We
2185 * need to take care to only take that shortcut in case we've
2186 * processed the qtd just written back without errors, i.e. halt
2187 * bit is clear.
2188 */
2189 if (q->qh.token & QTD_TOKEN_HALT) {
2190 /*
2191 * We should not do any further processing on a halted queue!
2192 * This is esp. important for bulk endpoints with pipelining enabled
2193 * (redirection to a real USB device), where we must cancel all the
2194 * transfers after this one so that:
2195 * 1) If they've completed already, they are not processed further
2196 * causing more stalls, originating from the same failed transfer
2197 * 2) If still in flight, they are cancelled before the guest does
2198 * a clear stall, otherwise the guest and device can loose sync!
2199 */
2200 while ((p = QTAILQ_FIRST(&q->packets)) != NULL) {
2201 ehci_free_packet(p);
2202 }
2203 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2204 again = 1;
2205 } else {
2206 ehci_set_state(q->ehci, q->async, EST_ADVANCEQUEUE);
2207 again = 1;
2208 }
2209 return again;
2210 }
2211
2212 /*
2213 * This is the state machine that is common to both async and periodic
2214 */
2215
2216 static void ehci_advance_state(EHCIState *ehci, int async)
2217 {
2218 EHCIQueue *q = NULL;
2219 int again;
2220
2221 do {
2222 switch(ehci_get_state(ehci, async)) {
2223 case EST_WAITLISTHEAD:
2224 again = ehci_state_waitlisthead(ehci, async);
2225 break;
2226
2227 case EST_FETCHENTRY:
2228 again = ehci_state_fetchentry(ehci, async);
2229 break;
2230
2231 case EST_FETCHQH:
2232 q = ehci_state_fetchqh(ehci, async);
2233 if (q != NULL) {
2234 assert(q->async == async);
2235 again = 1;
2236 } else {
2237 again = 0;
2238 }
2239 break;
2240
2241 case EST_FETCHITD:
2242 again = ehci_state_fetchitd(ehci, async);
2243 break;
2244
2245 case EST_FETCHSITD:
2246 again = ehci_state_fetchsitd(ehci, async);
2247 break;
2248
2249 case EST_ADVANCEQUEUE:
2250 again = ehci_state_advqueue(q);
2251 break;
2252
2253 case EST_FETCHQTD:
2254 again = ehci_state_fetchqtd(q);
2255 break;
2256
2257 case EST_HORIZONTALQH:
2258 again = ehci_state_horizqh(q);
2259 break;
2260
2261 case EST_EXECUTE:
2262 again = ehci_state_execute(q);
2263 if (async) {
2264 ehci->async_stepdown = 0;
2265 }
2266 break;
2267
2268 case EST_EXECUTING:
2269 assert(q != NULL);
2270 if (async) {
2271 ehci->async_stepdown = 0;
2272 }
2273 again = ehci_state_executing(q);
2274 break;
2275
2276 case EST_WRITEBACK:
2277 assert(q != NULL);
2278 again = ehci_state_writeback(q);
2279 break;
2280
2281 default:
2282 fprintf(stderr, "Bad state!\n");
2283 again = -1;
2284 assert(0);
2285 break;
2286 }
2287
2288 if (again < 0) {
2289 fprintf(stderr, "processing error - resetting ehci HC\n");
2290 ehci_reset(ehci);
2291 again = 0;
2292 }
2293 }
2294 while (again);
2295 }
2296
2297 static void ehci_advance_async_state(EHCIState *ehci)
2298 {
2299 const int async = 1;
2300
2301 switch(ehci_get_state(ehci, async)) {
2302 case EST_INACTIVE:
2303 if (!ehci_async_enabled(ehci)) {
2304 break;
2305 }
2306 ehci_set_state(ehci, async, EST_ACTIVE);
2307 // No break, fall through to ACTIVE
2308
2309 case EST_ACTIVE:
2310 if (!ehci_async_enabled(ehci)) {
2311 ehci_queues_rip_all(ehci, async);
2312 ehci_set_state(ehci, async, EST_INACTIVE);
2313 break;
2314 }
2315
2316 /* make sure guest has acknowledged the doorbell interrupt */
2317 /* TO-DO: is this really needed? */
2318 if (ehci->usbsts & USBSTS_IAA) {
2319 DPRINTF("IAA status bit still set.\n");
2320 break;
2321 }
2322
2323 /* check that address register has been set */
2324 if (ehci->asynclistaddr == 0) {
2325 break;
2326 }
2327
2328 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
2329 ehci_advance_state(ehci, async);
2330
2331 /* If the doorbell is set, the guest wants to make a change to the
2332 * schedule. The host controller needs to release cached data.
2333 * (section 4.8.2)
2334 */
2335 if (ehci->usbcmd & USBCMD_IAAD) {
2336 /* Remove all unseen qhs from the async qhs queue */
2337 ehci_queues_rip_unused(ehci, async, 1);
2338 DPRINTF("ASYNC: doorbell request acknowledged\n");
2339 ehci->usbcmd &= ~USBCMD_IAAD;
2340 ehci_raise_irq(ehci, USBSTS_IAA);
2341 }
2342 break;
2343
2344 default:
2345 /* this should only be due to a developer mistake */
2346 fprintf(stderr, "ehci: Bad asynchronous state %d. "
2347 "Resetting to active\n", ehci->astate);
2348 assert(0);
2349 }
2350 }
2351
2352 static void ehci_advance_periodic_state(EHCIState *ehci)
2353 {
2354 uint32_t entry;
2355 uint32_t list;
2356 const int async = 0;
2357
2358 // 4.6
2359
2360 switch(ehci_get_state(ehci, async)) {
2361 case EST_INACTIVE:
2362 if (!(ehci->frindex & 7) && ehci_periodic_enabled(ehci)) {
2363 ehci_set_state(ehci, async, EST_ACTIVE);
2364 // No break, fall through to ACTIVE
2365 } else
2366 break;
2367
2368 case EST_ACTIVE:
2369 if (!(ehci->frindex & 7) && !ehci_periodic_enabled(ehci)) {
2370 ehci_queues_rip_all(ehci, async);
2371 ehci_set_state(ehci, async, EST_INACTIVE);
2372 break;
2373 }
2374
2375 list = ehci->periodiclistbase & 0xfffff000;
2376 /* check that register has been set */
2377 if (list == 0) {
2378 break;
2379 }
2380 list |= ((ehci->frindex & 0x1ff8) >> 1);
2381
2382 pci_dma_read(&ehci->dev, list, &entry, sizeof entry);
2383 entry = le32_to_cpu(entry);
2384
2385 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2386 ehci->frindex / 8, list, entry);
2387 ehci_set_fetch_addr(ehci, async,entry);
2388 ehci_set_state(ehci, async, EST_FETCHENTRY);
2389 ehci_advance_state(ehci, async);
2390 ehci_queues_rip_unused(ehci, async, 0);
2391 break;
2392
2393 default:
2394 /* this should only be due to a developer mistake */
2395 fprintf(stderr, "ehci: Bad periodic state %d. "
2396 "Resetting to active\n", ehci->pstate);
2397 assert(0);
2398 }
2399 }
2400
2401 static void ehci_update_frindex(EHCIState *ehci, int frames)
2402 {
2403 int i;
2404
2405 if (!ehci_enabled(ehci)) {
2406 return;
2407 }
2408
2409 for (i = 0; i < frames; i++) {
2410 ehci->frindex += 8;
2411
2412 if (ehci->frindex == 0x00002000) {
2413 ehci_raise_irq(ehci, USBSTS_FLR);
2414 }
2415
2416 if (ehci->frindex == 0x00004000) {
2417 ehci_raise_irq(ehci, USBSTS_FLR);
2418 ehci->frindex = 0;
2419 if (ehci->usbsts_frindex > 0x00004000) {
2420 ehci->usbsts_frindex -= 0x00004000;
2421 } else {
2422 ehci->usbsts_frindex = 0;
2423 }
2424 }
2425 }
2426 }
2427
2428 static void ehci_frame_timer(void *opaque)
2429 {
2430 EHCIState *ehci = opaque;
2431 int need_timer = 0;
2432 int64_t expire_time, t_now;
2433 uint64_t ns_elapsed;
2434 int frames, skipped_frames;
2435 int i;
2436
2437 t_now = qemu_get_clock_ns(vm_clock);
2438 ns_elapsed = t_now - ehci->last_run_ns;
2439 frames = ns_elapsed / FRAME_TIMER_NS;
2440
2441 if (ehci_periodic_enabled(ehci) || ehci->pstate != EST_INACTIVE) {
2442 need_timer++;
2443 ehci->async_stepdown = 0;
2444
2445 if (frames > ehci->maxframes) {
2446 skipped_frames = frames - ehci->maxframes;
2447 ehci_update_frindex(ehci, skipped_frames);
2448 ehci->last_run_ns += FRAME_TIMER_NS * skipped_frames;
2449 frames -= skipped_frames;
2450 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
2451 }
2452
2453 for (i = 0; i < frames; i++) {
2454 ehci_update_frindex(ehci, 1);
2455 ehci_advance_periodic_state(ehci);
2456 ehci->last_run_ns += FRAME_TIMER_NS;
2457 }
2458 } else {
2459 if (ehci->async_stepdown < ehci->maxframes / 2) {
2460 ehci->async_stepdown++;
2461 }
2462 ehci_update_frindex(ehci, frames);
2463 ehci->last_run_ns += FRAME_TIMER_NS * frames;
2464 }
2465
2466 /* Async is not inside loop since it executes everything it can once
2467 * called
2468 */
2469 if (ehci_async_enabled(ehci) || ehci->astate != EST_INACTIVE) {
2470 need_timer++;
2471 ehci_advance_async_state(ehci);
2472 }
2473
2474 ehci_commit_irq(ehci);
2475 if (ehci->usbsts_pending) {
2476 need_timer++;
2477 ehci->async_stepdown = 0;
2478 }
2479
2480 if (need_timer) {
2481 expire_time = t_now + (get_ticks_per_sec()
2482 * (ehci->async_stepdown+1) / FRAME_TIMER_FREQ);
2483 qemu_mod_timer(ehci->frame_timer, expire_time);
2484 }
2485 }
2486
2487 static void ehci_async_bh(void *opaque)
2488 {
2489 EHCIState *ehci = opaque;
2490 ehci_advance_async_state(ehci);
2491 }
2492
2493 static const MemoryRegionOps ehci_mem_ops = {
2494 .old_mmio = {
2495 .read = { ehci_mem_readb, ehci_mem_readw, ehci_mem_readl },
2496 .write = { ehci_mem_writeb, ehci_mem_writew, ehci_mem_writel },
2497 },
2498 .endianness = DEVICE_LITTLE_ENDIAN,
2499 };
2500
2501 static int usb_ehci_initfn(PCIDevice *dev);
2502
2503 static USBPortOps ehci_port_ops = {
2504 .attach = ehci_attach,
2505 .detach = ehci_detach,
2506 .child_detach = ehci_child_detach,
2507 .wakeup = ehci_wakeup,
2508 .complete = ehci_async_complete_packet,
2509 };
2510
2511 static USBBusOps ehci_bus_ops = {
2512 .register_companion = ehci_register_companion,
2513 };
2514
2515 static int usb_ehci_post_load(void *opaque, int version_id)
2516 {
2517 EHCIState *s = opaque;
2518 int i;
2519
2520 for (i = 0; i < NB_PORTS; i++) {
2521 USBPort *companion = s->companion_ports[i];
2522 if (companion == NULL) {
2523 continue;
2524 }
2525 if (s->portsc[i] & PORTSC_POWNER) {
2526 companion->dev = s->ports[i].dev;
2527 } else {
2528 companion->dev = NULL;
2529 }
2530 }
2531
2532 return 0;
2533 }
2534
2535 static const VMStateDescription vmstate_ehci = {
2536 .name = "ehci",
2537 .version_id = 2,
2538 .minimum_version_id = 1,
2539 .post_load = usb_ehci_post_load,
2540 .fields = (VMStateField[]) {
2541 VMSTATE_PCI_DEVICE(dev, EHCIState),
2542 /* mmio registers */
2543 VMSTATE_UINT32(usbcmd, EHCIState),
2544 VMSTATE_UINT32(usbsts, EHCIState),
2545 VMSTATE_UINT32_V(usbsts_pending, EHCIState, 2),
2546 VMSTATE_UINT32_V(usbsts_frindex, EHCIState, 2),
2547 VMSTATE_UINT32(usbintr, EHCIState),
2548 VMSTATE_UINT32(frindex, EHCIState),
2549 VMSTATE_UINT32(ctrldssegment, EHCIState),
2550 VMSTATE_UINT32(periodiclistbase, EHCIState),
2551 VMSTATE_UINT32(asynclistaddr, EHCIState),
2552 VMSTATE_UINT32(configflag, EHCIState),
2553 VMSTATE_UINT32(portsc[0], EHCIState),
2554 VMSTATE_UINT32(portsc[1], EHCIState),
2555 VMSTATE_UINT32(portsc[2], EHCIState),
2556 VMSTATE_UINT32(portsc[3], EHCIState),
2557 VMSTATE_UINT32(portsc[4], EHCIState),
2558 VMSTATE_UINT32(portsc[5], EHCIState),
2559 /* frame timer */
2560 VMSTATE_TIMER(frame_timer, EHCIState),
2561 VMSTATE_UINT64(last_run_ns, EHCIState),
2562 VMSTATE_UINT32(async_stepdown, EHCIState),
2563 /* schedule state */
2564 VMSTATE_UINT32(astate, EHCIState),
2565 VMSTATE_UINT32(pstate, EHCIState),
2566 VMSTATE_UINT32(a_fetch_addr, EHCIState),
2567 VMSTATE_UINT32(p_fetch_addr, EHCIState),
2568 VMSTATE_END_OF_LIST()
2569 }
2570 };
2571
2572 static Property ehci_properties[] = {
2573 DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128),
2574 DEFINE_PROP_END_OF_LIST(),
2575 };
2576
2577 static void ehci_class_init(ObjectClass *klass, void *data)
2578 {
2579 DeviceClass *dc = DEVICE_CLASS(klass);
2580 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2581
2582 k->init = usb_ehci_initfn;
2583 k->vendor_id = PCI_VENDOR_ID_INTEL;
2584 k->device_id = PCI_DEVICE_ID_INTEL_82801D; /* ich4 */
2585 k->revision = 0x10;
2586 k->class_id = PCI_CLASS_SERIAL_USB;
2587 dc->vmsd = &vmstate_ehci;
2588 dc->props = ehci_properties;
2589 }
2590
2591 static TypeInfo ehci_info = {
2592 .name = "usb-ehci",
2593 .parent = TYPE_PCI_DEVICE,
2594 .instance_size = sizeof(EHCIState),
2595 .class_init = ehci_class_init,
2596 };
2597
2598 static void ich9_ehci_class_init(ObjectClass *klass, void *data)
2599 {
2600 DeviceClass *dc = DEVICE_CLASS(klass);
2601 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2602
2603 k->init = usb_ehci_initfn;
2604 k->vendor_id = PCI_VENDOR_ID_INTEL;
2605 k->device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1;
2606 k->revision = 0x03;
2607 k->class_id = PCI_CLASS_SERIAL_USB;
2608 dc->vmsd = &vmstate_ehci;
2609 dc->props = ehci_properties;
2610 }
2611
2612 static TypeInfo ich9_ehci_info = {
2613 .name = "ich9-usb-ehci1",
2614 .parent = TYPE_PCI_DEVICE,
2615 .instance_size = sizeof(EHCIState),
2616 .class_init = ich9_ehci_class_init,
2617 };
2618
2619 static int usb_ehci_initfn(PCIDevice *dev)
2620 {
2621 EHCIState *s = DO_UPCAST(EHCIState, dev, dev);
2622 uint8_t *pci_conf = s->dev.config;
2623 int i;
2624
2625 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
2626
2627 /* capabilities pointer */
2628 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
2629 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2630
2631 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */
2632 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
2633 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
2634
2635 // pci_conf[0x50] = 0x01; // power management caps
2636
2637 pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4)
2638 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5)
2639 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6)
2640
2641 pci_conf[0x64] = 0x00;
2642 pci_conf[0x65] = 0x00;
2643 pci_conf[0x66] = 0x00;
2644 pci_conf[0x67] = 0x00;
2645 pci_conf[0x68] = 0x01;
2646 pci_conf[0x69] = 0x00;
2647 pci_conf[0x6a] = 0x00;
2648 pci_conf[0x6b] = 0x00; // USBLEGSUP
2649 pci_conf[0x6c] = 0x00;
2650 pci_conf[0x6d] = 0x00;
2651 pci_conf[0x6e] = 0x00;
2652 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS
2653
2654 // 2.2 host controller interface version
2655 s->mmio[0x00] = (uint8_t) OPREGBASE;
2656 s->mmio[0x01] = 0x00;
2657 s->mmio[0x02] = 0x00;
2658 s->mmio[0x03] = 0x01; // HC version
2659 s->mmio[0x04] = NB_PORTS; // Number of downstream ports
2660 s->mmio[0x05] = 0x00; // No companion ports at present
2661 s->mmio[0x06] = 0x00;
2662 s->mmio[0x07] = 0x00;
2663 s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2664 s->mmio[0x09] = 0x68; // EECP
2665 s->mmio[0x0a] = 0x00;
2666 s->mmio[0x0b] = 0x00;
2667
2668 s->irq = s->dev.irq[3];
2669
2670 usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev);
2671 for(i = 0; i < NB_PORTS; i++) {
2672 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2673 USB_SPEED_MASK_HIGH);
2674 s->ports[i].dev = 0;
2675 }
2676
2677 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2678 s->async_bh = qemu_bh_new(ehci_async_bh, s);
2679 QTAILQ_INIT(&s->aqueues);
2680 QTAILQ_INIT(&s->pqueues);
2681 usb_packet_init(&s->ipacket);
2682
2683 qemu_register_reset(ehci_reset, s);
2684
2685 memory_region_init_io(&s->mem, &ehci_mem_ops, s, "ehci", MMIO_SIZE);
2686 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
2687
2688 return 0;
2689 }
2690
2691 static void ehci_register_types(void)
2692 {
2693 type_register_static(&ehci_info);
2694 type_register_static(&ich9_ehci_info);
2695 }
2696
2697 type_init(ehci_register_types)
2698
2699 /*
2700 * vim: expandtab ts=4
2701 */
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