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Revert "ehci: don't flush cache on doorbell rings."
[mirror_qemu.git] / hw / usb / hcd-ehci.c
1 /*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 *
6 * EHCI project was started by Mark Burkley, with contributions by
7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
8 * Jan Kiszka and Vincent Palatin contributed bugfixes.
9 *
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or(at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #include "hw/hw.h"
26 #include "qemu-timer.h"
27 #include "hw/usb.h"
28 #include "hw/pci.h"
29 #include "monitor.h"
30 #include "trace.h"
31 #include "dma.h"
32
33 #define EHCI_DEBUG 0
34
35 #if EHCI_DEBUG
36 #define DPRINTF printf
37 #else
38 #define DPRINTF(...)
39 #endif
40
41 /* internal processing - reset HC to try and recover */
42 #define USB_RET_PROCERR (-99)
43
44 #define MMIO_SIZE 0x1000
45
46 /* Capability Registers Base Address - section 2.2 */
47 #define CAPREGBASE 0x0000
48 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
49 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
50 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
51 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
52 #define EECP HCCPARAMS + 1
53 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
54 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
55
56 #define OPREGBASE 0x0020 // Operational Registers Base Address
57
58 #define USBCMD OPREGBASE + 0x0000
59 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
60 #define USBCMD_HCRESET (1 << 1) // HC Reset
61 #define USBCMD_FLS (3 << 2) // Frame List Size
62 #define USBCMD_FLS_SH 2 // Frame List Size Shift
63 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
64 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
65 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
66 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
67 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
68 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
69 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
70 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
71
72 #define USBSTS OPREGBASE + 0x0004
73 #define USBSTS_RO_MASK 0x0000003f
74 #define USBSTS_INT (1 << 0) // USB Interrupt
75 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
76 #define USBSTS_PCD (1 << 2) // Port Change Detect
77 #define USBSTS_FLR (1 << 3) // Frame List Rollover
78 #define USBSTS_HSE (1 << 4) // Host System Error
79 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
80 #define USBSTS_HALT (1 << 12) // HC Halted
81 #define USBSTS_REC (1 << 13) // Reclamation
82 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
83 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
84
85 /*
86 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
87 * so no need to redefine here.
88 */
89 #define USBINTR OPREGBASE + 0x0008
90 #define USBINTR_MASK 0x0000003f
91
92 #define FRINDEX OPREGBASE + 0x000c
93 #define CTRLDSSEGMENT OPREGBASE + 0x0010
94 #define PERIODICLISTBASE OPREGBASE + 0x0014
95 #define ASYNCLISTADDR OPREGBASE + 0x0018
96 #define ASYNCLISTADDR_MASK 0xffffffe0
97
98 #define CONFIGFLAG OPREGBASE + 0x0040
99
100 #define PORTSC (OPREGBASE + 0x0044)
101 #define PORTSC_BEGIN PORTSC
102 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
103 /*
104 * Bits that are reserved or are read-only are masked out of values
105 * written to us by software
106 */
107 #define PORTSC_RO_MASK 0x007001c0
108 #define PORTSC_RWC_MASK 0x0000002a
109 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
110 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
111 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
112 #define PORTSC_PTC (15 << 16) // Port Test Control
113 #define PORTSC_PTC_SH 16 // Port Test Control shift
114 #define PORTSC_PIC (3 << 14) // Port Indicator Control
115 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
116 #define PORTSC_POWNER (1 << 13) // Port Owner
117 #define PORTSC_PPOWER (1 << 12) // Port Power
118 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
119 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
120 #define PORTSC_PRESET (1 << 8) // Port Reset
121 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
122 #define PORTSC_FPRES (1 << 6) // Force Port Resume
123 #define PORTSC_OCC (1 << 5) // Over Current Change
124 #define PORTSC_OCA (1 << 4) // Over Current Active
125 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
126 #define PORTSC_PED (1 << 2) // Port Enable/Disable
127 #define PORTSC_CSC (1 << 1) // Connect Status Change
128 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
129
130 #define FRAME_TIMER_FREQ 1000
131 #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ)
132
133 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
134 #define NB_PORTS 6 // Number of downstream ports
135 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
136 #define MAX_QH 100 // Max allowable queue heads in a chain
137
138 /* Internal periodic / asynchronous schedule state machine states
139 */
140 typedef enum {
141 EST_INACTIVE = 1000,
142 EST_ACTIVE,
143 EST_EXECUTING,
144 EST_SLEEPING,
145 /* The following states are internal to the state machine function
146 */
147 EST_WAITLISTHEAD,
148 EST_FETCHENTRY,
149 EST_FETCHQH,
150 EST_FETCHITD,
151 EST_FETCHSITD,
152 EST_ADVANCEQUEUE,
153 EST_FETCHQTD,
154 EST_EXECUTE,
155 EST_WRITEBACK,
156 EST_HORIZONTALQH
157 } EHCI_STATES;
158
159 /* macros for accessing fields within next link pointer entry */
160 #define NLPTR_GET(x) ((x) & 0xffffffe0)
161 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
162 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
163
164 /* link pointer types */
165 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
166 #define NLPTR_TYPE_QH 1 // queue head
167 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
168 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
169
170
171 /* EHCI spec version 1.0 Section 3.3
172 */
173 typedef struct EHCIitd {
174 uint32_t next;
175
176 uint32_t transact[8];
177 #define ITD_XACT_ACTIVE (1 << 31)
178 #define ITD_XACT_DBERROR (1 << 30)
179 #define ITD_XACT_BABBLE (1 << 29)
180 #define ITD_XACT_XACTERR (1 << 28)
181 #define ITD_XACT_LENGTH_MASK 0x0fff0000
182 #define ITD_XACT_LENGTH_SH 16
183 #define ITD_XACT_IOC (1 << 15)
184 #define ITD_XACT_PGSEL_MASK 0x00007000
185 #define ITD_XACT_PGSEL_SH 12
186 #define ITD_XACT_OFFSET_MASK 0x00000fff
187
188 uint32_t bufptr[7];
189 #define ITD_BUFPTR_MASK 0xfffff000
190 #define ITD_BUFPTR_SH 12
191 #define ITD_BUFPTR_EP_MASK 0x00000f00
192 #define ITD_BUFPTR_EP_SH 8
193 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
194 #define ITD_BUFPTR_DEVADDR_SH 0
195 #define ITD_BUFPTR_DIRECTION (1 << 11)
196 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
197 #define ITD_BUFPTR_MAXPKT_SH 0
198 #define ITD_BUFPTR_MULT_MASK 0x00000003
199 #define ITD_BUFPTR_MULT_SH 0
200 } EHCIitd;
201
202 /* EHCI spec version 1.0 Section 3.4
203 */
204 typedef struct EHCIsitd {
205 uint32_t next; // Standard next link pointer
206 uint32_t epchar;
207 #define SITD_EPCHAR_IO (1 << 31)
208 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
209 #define SITD_EPCHAR_PORTNUM_SH 24
210 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
211 #define SITD_EPCHAR_HUBADDR_SH 16
212 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
213 #define SITD_EPCHAR_EPNUM_SH 8
214 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
215
216 uint32_t uframe;
217 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
218 #define SITD_UFRAME_CMASK_SH 8
219 #define SITD_UFRAME_SMASK_MASK 0x000000ff
220
221 uint32_t results;
222 #define SITD_RESULTS_IOC (1 << 31)
223 #define SITD_RESULTS_PGSEL (1 << 30)
224 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
225 #define SITD_RESULTS_TYBYTES_SH 16
226 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
227 #define SITD_RESULTS_CPROGMASK_SH 8
228 #define SITD_RESULTS_ACTIVE (1 << 7)
229 #define SITD_RESULTS_ERR (1 << 6)
230 #define SITD_RESULTS_DBERR (1 << 5)
231 #define SITD_RESULTS_BABBLE (1 << 4)
232 #define SITD_RESULTS_XACTERR (1 << 3)
233 #define SITD_RESULTS_MISSEDUF (1 << 2)
234 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
235
236 uint32_t bufptr[2];
237 #define SITD_BUFPTR_MASK 0xfffff000
238 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
239 #define SITD_BUFPTR_TPOS_MASK 0x00000018
240 #define SITD_BUFPTR_TPOS_SH 3
241 #define SITD_BUFPTR_TCNT_MASK 0x00000007
242
243 uint32_t backptr; // Standard next link pointer
244 } EHCIsitd;
245
246 /* EHCI spec version 1.0 Section 3.5
247 */
248 typedef struct EHCIqtd {
249 uint32_t next; // Standard next link pointer
250 uint32_t altnext; // Standard next link pointer
251 uint32_t token;
252 #define QTD_TOKEN_DTOGGLE (1 << 31)
253 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
254 #define QTD_TOKEN_TBYTES_SH 16
255 #define QTD_TOKEN_IOC (1 << 15)
256 #define QTD_TOKEN_CPAGE_MASK 0x00007000
257 #define QTD_TOKEN_CPAGE_SH 12
258 #define QTD_TOKEN_CERR_MASK 0x00000c00
259 #define QTD_TOKEN_CERR_SH 10
260 #define QTD_TOKEN_PID_MASK 0x00000300
261 #define QTD_TOKEN_PID_SH 8
262 #define QTD_TOKEN_ACTIVE (1 << 7)
263 #define QTD_TOKEN_HALT (1 << 6)
264 #define QTD_TOKEN_DBERR (1 << 5)
265 #define QTD_TOKEN_BABBLE (1 << 4)
266 #define QTD_TOKEN_XACTERR (1 << 3)
267 #define QTD_TOKEN_MISSEDUF (1 << 2)
268 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
269 #define QTD_TOKEN_PING (1 << 0)
270
271 uint32_t bufptr[5]; // Standard buffer pointer
272 #define QTD_BUFPTR_MASK 0xfffff000
273 #define QTD_BUFPTR_SH 12
274 } EHCIqtd;
275
276 /* EHCI spec version 1.0 Section 3.6
277 */
278 typedef struct EHCIqh {
279 uint32_t next; // Standard next link pointer
280
281 /* endpoint characteristics */
282 uint32_t epchar;
283 #define QH_EPCHAR_RL_MASK 0xf0000000
284 #define QH_EPCHAR_RL_SH 28
285 #define QH_EPCHAR_C (1 << 27)
286 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
287 #define QH_EPCHAR_MPLEN_SH 16
288 #define QH_EPCHAR_H (1 << 15)
289 #define QH_EPCHAR_DTC (1 << 14)
290 #define QH_EPCHAR_EPS_MASK 0x00003000
291 #define QH_EPCHAR_EPS_SH 12
292 #define EHCI_QH_EPS_FULL 0
293 #define EHCI_QH_EPS_LOW 1
294 #define EHCI_QH_EPS_HIGH 2
295 #define EHCI_QH_EPS_RESERVED 3
296
297 #define QH_EPCHAR_EP_MASK 0x00000f00
298 #define QH_EPCHAR_EP_SH 8
299 #define QH_EPCHAR_I (1 << 7)
300 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
301 #define QH_EPCHAR_DEVADDR_SH 0
302
303 /* endpoint capabilities */
304 uint32_t epcap;
305 #define QH_EPCAP_MULT_MASK 0xc0000000
306 #define QH_EPCAP_MULT_SH 30
307 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
308 #define QH_EPCAP_PORTNUM_SH 23
309 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
310 #define QH_EPCAP_HUBADDR_SH 16
311 #define QH_EPCAP_CMASK_MASK 0x0000ff00
312 #define QH_EPCAP_CMASK_SH 8
313 #define QH_EPCAP_SMASK_MASK 0x000000ff
314 #define QH_EPCAP_SMASK_SH 0
315
316 uint32_t current_qtd; // Standard next link pointer
317 uint32_t next_qtd; // Standard next link pointer
318 uint32_t altnext_qtd;
319 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
320 #define QH_ALTNEXT_NAKCNT_SH 1
321
322 uint32_t token; // Same as QTD token
323 uint32_t bufptr[5]; // Standard buffer pointer
324 #define BUFPTR_CPROGMASK_MASK 0x000000ff
325 #define BUFPTR_FRAMETAG_MASK 0x0000001f
326 #define BUFPTR_SBYTES_MASK 0x00000fe0
327 #define BUFPTR_SBYTES_SH 5
328 } EHCIqh;
329
330 /* EHCI spec version 1.0 Section 3.7
331 */
332 typedef struct EHCIfstn {
333 uint32_t next; // Standard next link pointer
334 uint32_t backptr; // Standard next link pointer
335 } EHCIfstn;
336
337 typedef struct EHCIPacket EHCIPacket;
338 typedef struct EHCIQueue EHCIQueue;
339 typedef struct EHCIState EHCIState;
340
341 enum async_state {
342 EHCI_ASYNC_NONE = 0,
343 EHCI_ASYNC_INFLIGHT,
344 EHCI_ASYNC_FINISHED,
345 };
346
347 struct EHCIPacket {
348 EHCIQueue *queue;
349 QTAILQ_ENTRY(EHCIPacket) next;
350
351 EHCIqtd qtd; /* copy of current QTD (being worked on) */
352 uint32_t qtdaddr; /* address QTD read from */
353
354 USBPacket packet;
355 QEMUSGList sgl;
356 int pid;
357 uint32_t tbytes;
358 enum async_state async;
359 int usb_status;
360 };
361
362 struct EHCIQueue {
363 EHCIState *ehci;
364 QTAILQ_ENTRY(EHCIQueue) next;
365 uint32_t seen;
366 uint64_t ts;
367 int async;
368
369 /* cached data from guest - needs to be flushed
370 * when guest removes an entry (doorbell, handshake sequence)
371 */
372 EHCIqh qh; /* copy of current QH (being worked on) */
373 uint32_t qhaddr; /* address QH read from */
374 uint32_t qtdaddr; /* address QTD read from */
375 USBDevice *dev;
376 QTAILQ_HEAD(, EHCIPacket) packets;
377 };
378
379 typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead;
380
381 struct EHCIState {
382 PCIDevice dev;
383 USBBus bus;
384 qemu_irq irq;
385 MemoryRegion mem;
386 int companion_count;
387
388 /* properties */
389 uint32_t maxframes;
390
391 /*
392 * EHCI spec version 1.0 Section 2.3
393 * Host Controller Operational Registers
394 */
395 union {
396 uint8_t mmio[MMIO_SIZE];
397 struct {
398 uint8_t cap[OPREGBASE];
399 uint32_t usbcmd;
400 uint32_t usbsts;
401 uint32_t usbintr;
402 uint32_t frindex;
403 uint32_t ctrldssegment;
404 uint32_t periodiclistbase;
405 uint32_t asynclistaddr;
406 uint32_t notused[9];
407 uint32_t configflag;
408 uint32_t portsc[NB_PORTS];
409 };
410 };
411
412 /*
413 * Internal states, shadow registers, etc
414 */
415 QEMUTimer *frame_timer;
416 QEMUBH *async_bh;
417 uint32_t astate; /* Current state in asynchronous schedule */
418 uint32_t pstate; /* Current state in periodic schedule */
419 USBPort ports[NB_PORTS];
420 USBPort *companion_ports[NB_PORTS];
421 uint32_t usbsts_pending;
422 uint32_t usbsts_frindex;
423 EHCIQueueHead aqueues;
424 EHCIQueueHead pqueues;
425
426 /* which address to look at next */
427 uint32_t a_fetch_addr;
428 uint32_t p_fetch_addr;
429
430 USBPacket ipacket;
431 QEMUSGList isgl;
432
433 uint64_t last_run_ns;
434 uint32_t async_stepdown;
435 };
436
437 #define SET_LAST_RUN_CLOCK(s) \
438 (s)->last_run_ns = qemu_get_clock_ns(vm_clock);
439
440 /* nifty macros from Arnon's EHCI version */
441 #define get_field(data, field) \
442 (((data) & field##_MASK) >> field##_SH)
443
444 #define set_field(data, newval, field) do { \
445 uint32_t val = *data; \
446 val &= ~ field##_MASK; \
447 val |= ((newval) << field##_SH) & field##_MASK; \
448 *data = val; \
449 } while(0)
450
451 static const char *ehci_state_names[] = {
452 [EST_INACTIVE] = "INACTIVE",
453 [EST_ACTIVE] = "ACTIVE",
454 [EST_EXECUTING] = "EXECUTING",
455 [EST_SLEEPING] = "SLEEPING",
456 [EST_WAITLISTHEAD] = "WAITLISTHEAD",
457 [EST_FETCHENTRY] = "FETCH ENTRY",
458 [EST_FETCHQH] = "FETCH QH",
459 [EST_FETCHITD] = "FETCH ITD",
460 [EST_ADVANCEQUEUE] = "ADVANCEQUEUE",
461 [EST_FETCHQTD] = "FETCH QTD",
462 [EST_EXECUTE] = "EXECUTE",
463 [EST_WRITEBACK] = "WRITEBACK",
464 [EST_HORIZONTALQH] = "HORIZONTALQH",
465 };
466
467 static const char *ehci_mmio_names[] = {
468 [CAPLENGTH] = "CAPLENGTH",
469 [HCIVERSION] = "HCIVERSION",
470 [HCSPARAMS] = "HCSPARAMS",
471 [HCCPARAMS] = "HCCPARAMS",
472 [USBCMD] = "USBCMD",
473 [USBSTS] = "USBSTS",
474 [USBINTR] = "USBINTR",
475 [FRINDEX] = "FRINDEX",
476 [PERIODICLISTBASE] = "P-LIST BASE",
477 [ASYNCLISTADDR] = "A-LIST ADDR",
478 [PORTSC_BEGIN] = "PORTSC #0",
479 [PORTSC_BEGIN + 4] = "PORTSC #1",
480 [PORTSC_BEGIN + 8] = "PORTSC #2",
481 [PORTSC_BEGIN + 12] = "PORTSC #3",
482 [PORTSC_BEGIN + 16] = "PORTSC #4",
483 [PORTSC_BEGIN + 20] = "PORTSC #5",
484 [CONFIGFLAG] = "CONFIGFLAG",
485 };
486
487 static const char *nr2str(const char **n, size_t len, uint32_t nr)
488 {
489 if (nr < len && n[nr] != NULL) {
490 return n[nr];
491 } else {
492 return "unknown";
493 }
494 }
495
496 static const char *state2str(uint32_t state)
497 {
498 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
499 }
500
501 static const char *addr2str(target_phys_addr_t addr)
502 {
503 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
504 }
505
506 static void ehci_trace_usbsts(uint32_t mask, int state)
507 {
508 /* interrupts */
509 if (mask & USBSTS_INT) {
510 trace_usb_ehci_usbsts("INT", state);
511 }
512 if (mask & USBSTS_ERRINT) {
513 trace_usb_ehci_usbsts("ERRINT", state);
514 }
515 if (mask & USBSTS_PCD) {
516 trace_usb_ehci_usbsts("PCD", state);
517 }
518 if (mask & USBSTS_FLR) {
519 trace_usb_ehci_usbsts("FLR", state);
520 }
521 if (mask & USBSTS_HSE) {
522 trace_usb_ehci_usbsts("HSE", state);
523 }
524 if (mask & USBSTS_IAA) {
525 trace_usb_ehci_usbsts("IAA", state);
526 }
527
528 /* status */
529 if (mask & USBSTS_HALT) {
530 trace_usb_ehci_usbsts("HALT", state);
531 }
532 if (mask & USBSTS_REC) {
533 trace_usb_ehci_usbsts("REC", state);
534 }
535 if (mask & USBSTS_PSS) {
536 trace_usb_ehci_usbsts("PSS", state);
537 }
538 if (mask & USBSTS_ASS) {
539 trace_usb_ehci_usbsts("ASS", state);
540 }
541 }
542
543 static inline void ehci_set_usbsts(EHCIState *s, int mask)
544 {
545 if ((s->usbsts & mask) == mask) {
546 return;
547 }
548 ehci_trace_usbsts(mask, 1);
549 s->usbsts |= mask;
550 }
551
552 static inline void ehci_clear_usbsts(EHCIState *s, int mask)
553 {
554 if ((s->usbsts & mask) == 0) {
555 return;
556 }
557 ehci_trace_usbsts(mask, 0);
558 s->usbsts &= ~mask;
559 }
560
561 /* update irq line */
562 static inline void ehci_update_irq(EHCIState *s)
563 {
564 int level = 0;
565
566 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
567 level = 1;
568 }
569
570 trace_usb_ehci_irq(level, s->frindex, s->usbsts, s->usbintr);
571 qemu_set_irq(s->irq, level);
572 }
573
574 /* flag interrupt condition */
575 static inline void ehci_raise_irq(EHCIState *s, int intr)
576 {
577 if (intr & (USBSTS_PCD | USBSTS_FLR | USBSTS_HSE)) {
578 s->usbsts |= intr;
579 ehci_update_irq(s);
580 } else {
581 s->usbsts_pending |= intr;
582 }
583 }
584
585 /*
586 * Commit pending interrupts (added via ehci_raise_irq),
587 * at the rate allowed by "Interrupt Threshold Control".
588 */
589 static inline void ehci_commit_irq(EHCIState *s)
590 {
591 uint32_t itc;
592
593 if (!s->usbsts_pending) {
594 return;
595 }
596 if (s->usbsts_frindex > s->frindex) {
597 return;
598 }
599
600 itc = (s->usbcmd >> 16) & 0xff;
601 s->usbsts |= s->usbsts_pending;
602 s->usbsts_pending = 0;
603 s->usbsts_frindex = s->frindex + itc;
604 ehci_update_irq(s);
605 }
606
607 static void ehci_update_halt(EHCIState *s)
608 {
609 if (s->usbcmd & USBCMD_RUNSTOP) {
610 ehci_clear_usbsts(s, USBSTS_HALT);
611 } else {
612 if (s->astate == EST_INACTIVE && s->pstate == EST_INACTIVE) {
613 ehci_set_usbsts(s, USBSTS_HALT);
614 }
615 }
616 }
617
618 static void ehci_set_state(EHCIState *s, int async, int state)
619 {
620 if (async) {
621 trace_usb_ehci_state("async", state2str(state));
622 s->astate = state;
623 if (s->astate == EST_INACTIVE) {
624 ehci_clear_usbsts(s, USBSTS_ASS);
625 ehci_update_halt(s);
626 } else {
627 ehci_set_usbsts(s, USBSTS_ASS);
628 }
629 } else {
630 trace_usb_ehci_state("periodic", state2str(state));
631 s->pstate = state;
632 if (s->pstate == EST_INACTIVE) {
633 ehci_clear_usbsts(s, USBSTS_PSS);
634 ehci_update_halt(s);
635 } else {
636 ehci_set_usbsts(s, USBSTS_PSS);
637 }
638 }
639 }
640
641 static int ehci_get_state(EHCIState *s, int async)
642 {
643 return async ? s->astate : s->pstate;
644 }
645
646 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr)
647 {
648 if (async) {
649 s->a_fetch_addr = addr;
650 } else {
651 s->p_fetch_addr = addr;
652 }
653 }
654
655 static int ehci_get_fetch_addr(EHCIState *s, int async)
656 {
657 return async ? s->a_fetch_addr : s->p_fetch_addr;
658 }
659
660 static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh)
661 {
662 /* need three here due to argument count limits */
663 trace_usb_ehci_qh_ptrs(q, addr, qh->next,
664 qh->current_qtd, qh->next_qtd, qh->altnext_qtd);
665 trace_usb_ehci_qh_fields(addr,
666 get_field(qh->epchar, QH_EPCHAR_RL),
667 get_field(qh->epchar, QH_EPCHAR_MPLEN),
668 get_field(qh->epchar, QH_EPCHAR_EPS),
669 get_field(qh->epchar, QH_EPCHAR_EP),
670 get_field(qh->epchar, QH_EPCHAR_DEVADDR));
671 trace_usb_ehci_qh_bits(addr,
672 (bool)(qh->epchar & QH_EPCHAR_C),
673 (bool)(qh->epchar & QH_EPCHAR_H),
674 (bool)(qh->epchar & QH_EPCHAR_DTC),
675 (bool)(qh->epchar & QH_EPCHAR_I));
676 }
677
678 static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd)
679 {
680 /* need three here due to argument count limits */
681 trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext);
682 trace_usb_ehci_qtd_fields(addr,
683 get_field(qtd->token, QTD_TOKEN_TBYTES),
684 get_field(qtd->token, QTD_TOKEN_CPAGE),
685 get_field(qtd->token, QTD_TOKEN_CERR),
686 get_field(qtd->token, QTD_TOKEN_PID));
687 trace_usb_ehci_qtd_bits(addr,
688 (bool)(qtd->token & QTD_TOKEN_IOC),
689 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
690 (bool)(qtd->token & QTD_TOKEN_HALT),
691 (bool)(qtd->token & QTD_TOKEN_BABBLE),
692 (bool)(qtd->token & QTD_TOKEN_XACTERR));
693 }
694
695 static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
696 {
697 trace_usb_ehci_itd(addr, itd->next,
698 get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
699 get_field(itd->bufptr[2], ITD_BUFPTR_MULT),
700 get_field(itd->bufptr[0], ITD_BUFPTR_EP),
701 get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
702 }
703
704 static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr,
705 EHCIsitd *sitd)
706 {
707 trace_usb_ehci_sitd(addr, sitd->next,
708 (bool)(sitd->results & SITD_RESULTS_ACTIVE));
709 }
710
711 static inline bool ehci_enabled(EHCIState *s)
712 {
713 return s->usbcmd & USBCMD_RUNSTOP;
714 }
715
716 static inline bool ehci_async_enabled(EHCIState *s)
717 {
718 return ehci_enabled(s) && (s->usbcmd & USBCMD_ASE);
719 }
720
721 static inline bool ehci_periodic_enabled(EHCIState *s)
722 {
723 return ehci_enabled(s) && (s->usbcmd & USBCMD_PSE);
724 }
725
726 /* packet management */
727
728 static EHCIPacket *ehci_alloc_packet(EHCIQueue *q)
729 {
730 EHCIPacket *p;
731
732 p = g_new0(EHCIPacket, 1);
733 p->queue = q;
734 usb_packet_init(&p->packet);
735 QTAILQ_INSERT_TAIL(&q->packets, p, next);
736 trace_usb_ehci_packet_action(p->queue, p, "alloc");
737 return p;
738 }
739
740 static void ehci_free_packet(EHCIPacket *p)
741 {
742 trace_usb_ehci_packet_action(p->queue, p, "free");
743 if (p->async == EHCI_ASYNC_INFLIGHT) {
744 usb_cancel_packet(&p->packet);
745 }
746 QTAILQ_REMOVE(&p->queue->packets, p, next);
747 usb_packet_cleanup(&p->packet);
748 g_free(p);
749 }
750
751 /* queue management */
752
753 static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint32_t addr, int async)
754 {
755 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
756 EHCIQueue *q;
757
758 q = g_malloc0(sizeof(*q));
759 q->ehci = ehci;
760 q->qhaddr = addr;
761 q->async = async;
762 QTAILQ_INIT(&q->packets);
763 QTAILQ_INSERT_HEAD(head, q, next);
764 trace_usb_ehci_queue_action(q, "alloc");
765 return q;
766 }
767
768 static void ehci_cancel_queue(EHCIQueue *q)
769 {
770 EHCIPacket *p;
771
772 p = QTAILQ_FIRST(&q->packets);
773 if (p == NULL) {
774 return;
775 }
776
777 trace_usb_ehci_queue_action(q, "cancel");
778 do {
779 ehci_free_packet(p);
780 } while ((p = QTAILQ_FIRST(&q->packets)) != NULL);
781 }
782
783 static void ehci_free_queue(EHCIQueue *q)
784 {
785 EHCIQueueHead *head = q->async ? &q->ehci->aqueues : &q->ehci->pqueues;
786
787 trace_usb_ehci_queue_action(q, "free");
788 ehci_cancel_queue(q);
789 QTAILQ_REMOVE(head, q, next);
790 g_free(q);
791 }
792
793 static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr,
794 int async)
795 {
796 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
797 EHCIQueue *q;
798
799 QTAILQ_FOREACH(q, head, next) {
800 if (addr == q->qhaddr) {
801 return q;
802 }
803 }
804 return NULL;
805 }
806
807 static void ehci_queues_rip_unused(EHCIState *ehci, int async, int flush)
808 {
809 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
810 uint64_t maxage = FRAME_TIMER_NS * ehci->maxframes * 4;
811 EHCIQueue *q, *tmp;
812
813 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
814 if (q->seen) {
815 q->seen = 0;
816 q->ts = ehci->last_run_ns;
817 continue;
818 }
819 if (!flush && ehci->last_run_ns < q->ts + maxage) {
820 continue;
821 }
822 ehci_free_queue(q);
823 }
824 }
825
826 static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async)
827 {
828 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
829 EHCIQueue *q, *tmp;
830
831 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
832 if (q->dev != dev) {
833 continue;
834 }
835 ehci_free_queue(q);
836 }
837 }
838
839 static void ehci_queues_rip_all(EHCIState *ehci, int async)
840 {
841 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
842 EHCIQueue *q, *tmp;
843
844 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
845 ehci_free_queue(q);
846 }
847 }
848
849 /* Attach or detach a device on root hub */
850
851 static void ehci_attach(USBPort *port)
852 {
853 EHCIState *s = port->opaque;
854 uint32_t *portsc = &s->portsc[port->index];
855 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci";
856
857 trace_usb_ehci_port_attach(port->index, owner, port->dev->product_desc);
858
859 if (*portsc & PORTSC_POWNER) {
860 USBPort *companion = s->companion_ports[port->index];
861 companion->dev = port->dev;
862 companion->ops->attach(companion);
863 return;
864 }
865
866 *portsc |= PORTSC_CONNECT;
867 *portsc |= PORTSC_CSC;
868
869 ehci_raise_irq(s, USBSTS_PCD);
870 ehci_commit_irq(s);
871 }
872
873 static void ehci_detach(USBPort *port)
874 {
875 EHCIState *s = port->opaque;
876 uint32_t *portsc = &s->portsc[port->index];
877 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci";
878
879 trace_usb_ehci_port_detach(port->index, owner);
880
881 if (*portsc & PORTSC_POWNER) {
882 USBPort *companion = s->companion_ports[port->index];
883 companion->ops->detach(companion);
884 companion->dev = NULL;
885 /*
886 * EHCI spec 4.2.2: "When a disconnect occurs... On the event,
887 * the port ownership is returned immediately to the EHCI controller."
888 */
889 *portsc &= ~PORTSC_POWNER;
890 return;
891 }
892
893 ehci_queues_rip_device(s, port->dev, 0);
894 ehci_queues_rip_device(s, port->dev, 1);
895
896 *portsc &= ~(PORTSC_CONNECT|PORTSC_PED);
897 *portsc |= PORTSC_CSC;
898
899 ehci_raise_irq(s, USBSTS_PCD);
900 ehci_commit_irq(s);
901 }
902
903 static void ehci_child_detach(USBPort *port, USBDevice *child)
904 {
905 EHCIState *s = port->opaque;
906 uint32_t portsc = s->portsc[port->index];
907
908 if (portsc & PORTSC_POWNER) {
909 USBPort *companion = s->companion_ports[port->index];
910 companion->ops->child_detach(companion, child);
911 return;
912 }
913
914 ehci_queues_rip_device(s, child, 0);
915 ehci_queues_rip_device(s, child, 1);
916 }
917
918 static void ehci_wakeup(USBPort *port)
919 {
920 EHCIState *s = port->opaque;
921 uint32_t portsc = s->portsc[port->index];
922
923 if (portsc & PORTSC_POWNER) {
924 USBPort *companion = s->companion_ports[port->index];
925 if (companion->ops->wakeup) {
926 companion->ops->wakeup(companion);
927 }
928 return;
929 }
930
931 qemu_bh_schedule(s->async_bh);
932 }
933
934 static int ehci_register_companion(USBBus *bus, USBPort *ports[],
935 uint32_t portcount, uint32_t firstport)
936 {
937 EHCIState *s = container_of(bus, EHCIState, bus);
938 uint32_t i;
939
940 if (firstport + portcount > NB_PORTS) {
941 qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport",
942 "firstport on masterbus");
943 error_printf_unless_qmp(
944 "firstport value of %u makes companion take ports %u - %u, which "
945 "is outside of the valid range of 0 - %u\n", firstport, firstport,
946 firstport + portcount - 1, NB_PORTS - 1);
947 return -1;
948 }
949
950 for (i = 0; i < portcount; i++) {
951 if (s->companion_ports[firstport + i]) {
952 qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus",
953 "an USB masterbus");
954 error_printf_unless_qmp(
955 "port %u on masterbus %s already has a companion assigned\n",
956 firstport + i, bus->qbus.name);
957 return -1;
958 }
959 }
960
961 for (i = 0; i < portcount; i++) {
962 s->companion_ports[firstport + i] = ports[i];
963 s->ports[firstport + i].speedmask |=
964 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL;
965 /* Ensure devs attached before the initial reset go to the companion */
966 s->portsc[firstport + i] = PORTSC_POWNER;
967 }
968
969 s->companion_count++;
970 s->mmio[0x05] = (s->companion_count << 4) | portcount;
971
972 return 0;
973 }
974
975 static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr)
976 {
977 USBDevice *dev;
978 USBPort *port;
979 int i;
980
981 for (i = 0; i < NB_PORTS; i++) {
982 port = &ehci->ports[i];
983 if (!(ehci->portsc[i] & PORTSC_PED)) {
984 DPRINTF("Port %d not enabled\n", i);
985 continue;
986 }
987 dev = usb_find_device(port, addr);
988 if (dev != NULL) {
989 return dev;
990 }
991 }
992 return NULL;
993 }
994
995 /* 4.1 host controller initialization */
996 static void ehci_reset(void *opaque)
997 {
998 EHCIState *s = opaque;
999 int i;
1000 USBDevice *devs[NB_PORTS];
1001
1002 trace_usb_ehci_reset();
1003
1004 /*
1005 * Do the detach before touching portsc, so that it correctly gets send to
1006 * us or to our companion based on PORTSC_POWNER before the reset.
1007 */
1008 for(i = 0; i < NB_PORTS; i++) {
1009 devs[i] = s->ports[i].dev;
1010 if (devs[i] && devs[i]->attached) {
1011 usb_detach(&s->ports[i]);
1012 }
1013 }
1014
1015 memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
1016
1017 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
1018 s->usbsts = USBSTS_HALT;
1019 s->usbsts_pending = 0;
1020 s->usbsts_frindex = 0;
1021
1022 s->astate = EST_INACTIVE;
1023 s->pstate = EST_INACTIVE;
1024
1025 for(i = 0; i < NB_PORTS; i++) {
1026 if (s->companion_ports[i]) {
1027 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
1028 } else {
1029 s->portsc[i] = PORTSC_PPOWER;
1030 }
1031 if (devs[i] && devs[i]->attached) {
1032 usb_attach(&s->ports[i]);
1033 usb_device_reset(devs[i]);
1034 }
1035 }
1036 ehci_queues_rip_all(s, 0);
1037 ehci_queues_rip_all(s, 1);
1038 qemu_del_timer(s->frame_timer);
1039 qemu_bh_cancel(s->async_bh);
1040 }
1041
1042 static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
1043 {
1044 EHCIState *s = ptr;
1045 uint32_t val;
1046
1047 val = s->mmio[addr];
1048
1049 return val;
1050 }
1051
1052 static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
1053 {
1054 EHCIState *s = ptr;
1055 uint32_t val;
1056
1057 val = s->mmio[addr] | (s->mmio[addr+1] << 8);
1058
1059 return val;
1060 }
1061
1062 static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
1063 {
1064 EHCIState *s = ptr;
1065 uint32_t val;
1066
1067 val = s->mmio[addr] | (s->mmio[addr+1] << 8) |
1068 (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);
1069
1070 trace_usb_ehci_mmio_readl(addr, addr2str(addr), val);
1071 return val;
1072 }
1073
1074 static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
1075 {
1076 fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
1077 exit(1);
1078 }
1079
1080 static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
1081 {
1082 fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
1083 exit(1);
1084 }
1085
1086 static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner)
1087 {
1088 USBDevice *dev = s->ports[port].dev;
1089 uint32_t *portsc = &s->portsc[port];
1090 uint32_t orig;
1091
1092 if (s->companion_ports[port] == NULL)
1093 return;
1094
1095 owner = owner & PORTSC_POWNER;
1096 orig = *portsc & PORTSC_POWNER;
1097
1098 if (!(owner ^ orig)) {
1099 return;
1100 }
1101
1102 if (dev && dev->attached) {
1103 usb_detach(&s->ports[port]);
1104 }
1105
1106 *portsc &= ~PORTSC_POWNER;
1107 *portsc |= owner;
1108
1109 if (dev && dev->attached) {
1110 usb_attach(&s->ports[port]);
1111 }
1112 }
1113
1114 static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
1115 {
1116 uint32_t *portsc = &s->portsc[port];
1117 USBDevice *dev = s->ports[port].dev;
1118
1119 /* Clear rwc bits */
1120 *portsc &= ~(val & PORTSC_RWC_MASK);
1121 /* The guest may clear, but not set the PED bit */
1122 *portsc &= val | ~PORTSC_PED;
1123 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */
1124 handle_port_owner_write(s, port, val);
1125 /* And finally apply RO_MASK */
1126 val &= PORTSC_RO_MASK;
1127
1128 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
1129 trace_usb_ehci_port_reset(port, 1);
1130 }
1131
1132 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
1133 trace_usb_ehci_port_reset(port, 0);
1134 if (dev && dev->attached) {
1135 usb_port_reset(&s->ports[port]);
1136 *portsc &= ~PORTSC_CSC;
1137 }
1138
1139 /*
1140 * Table 2.16 Set the enable bit(and enable bit change) to indicate
1141 * to SW that this port has a high speed device attached
1142 */
1143 if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) {
1144 val |= PORTSC_PED;
1145 }
1146 }
1147
1148 *portsc &= ~PORTSC_RO_MASK;
1149 *portsc |= val;
1150 }
1151
1152 static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
1153 {
1154 EHCIState *s = ptr;
1155 uint32_t *mmio = (uint32_t *)(&s->mmio[addr]);
1156 uint32_t old = *mmio;
1157 int i;
1158
1159 trace_usb_ehci_mmio_writel(addr, addr2str(addr), val);
1160
1161 /* Only aligned reads are allowed on OHCI */
1162 if (addr & 3) {
1163 fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
1164 TARGET_FMT_plx "\n", addr);
1165 return;
1166 }
1167
1168 if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
1169 handle_port_status_write(s, (addr-PORTSC)/4, val);
1170 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1171 return;
1172 }
1173
1174 if (addr < OPREGBASE) {
1175 fprintf(stderr, "usb-ehci: write attempt to read-only register"
1176 TARGET_FMT_plx "\n", addr);
1177 return;
1178 }
1179
1180
1181 /* Do any register specific pre-write processing here. */
1182 switch(addr) {
1183 case USBCMD:
1184 if (val & USBCMD_HCRESET) {
1185 ehci_reset(s);
1186 val = s->usbcmd;
1187 break;
1188 }
1189
1190 /* not supporting dynamic frame list size at the moment */
1191 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
1192 fprintf(stderr, "attempt to set frame list size -- value %d\n",
1193 val & USBCMD_FLS);
1194 val &= ~USBCMD_FLS;
1195 }
1196
1197 if (val & USBCMD_IAAD) {
1198 /*
1199 * Process IAAD immediately, otherwise the Linux IAAD watchdog may
1200 * trigger and re-use a qh without us seeing the unlink.
1201 */
1202 s->async_stepdown = 0;
1203 qemu_bh_schedule(s->async_bh);
1204 }
1205
1206 if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & val) !=
1207 ((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) {
1208 if (s->pstate == EST_INACTIVE) {
1209 SET_LAST_RUN_CLOCK(s);
1210 }
1211 s->usbcmd = val; /* Set usbcmd for ehci_update_halt() */
1212 ehci_update_halt(s);
1213 s->async_stepdown = 0;
1214 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
1215 }
1216 break;
1217
1218 case USBSTS:
1219 val &= USBSTS_RO_MASK; // bits 6 through 31 are RO
1220 ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC
1221 val = s->usbsts;
1222 ehci_update_irq(s);
1223 break;
1224
1225 case USBINTR:
1226 val &= USBINTR_MASK;
1227 break;
1228
1229 case FRINDEX:
1230 val &= 0x00003ff8; /* frindex is 14bits and always a multiple of 8 */
1231 break;
1232
1233 case CONFIGFLAG:
1234 val &= 0x1;
1235 if (val) {
1236 for(i = 0; i < NB_PORTS; i++)
1237 handle_port_owner_write(s, i, 0);
1238 }
1239 break;
1240
1241 case PERIODICLISTBASE:
1242 if (ehci_periodic_enabled(s)) {
1243 fprintf(stderr,
1244 "ehci: PERIODIC list base register set while periodic schedule\n"
1245 " is enabled and HC is enabled\n");
1246 }
1247 break;
1248
1249 case ASYNCLISTADDR:
1250 if (ehci_async_enabled(s)) {
1251 fprintf(stderr,
1252 "ehci: ASYNC list address register set while async schedule\n"
1253 " is enabled and HC is enabled\n");
1254 }
1255 break;
1256 }
1257
1258 *mmio = val;
1259 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1260 }
1261
1262
1263 // TODO : Put in common header file, duplication from usb-ohci.c
1264
1265 /* Get an array of dwords from main memory */
1266 static inline int get_dwords(EHCIState *ehci, uint32_t addr,
1267 uint32_t *buf, int num)
1268 {
1269 int i;
1270
1271 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1272 pci_dma_read(&ehci->dev, addr, buf, sizeof(*buf));
1273 *buf = le32_to_cpu(*buf);
1274 }
1275
1276 return 1;
1277 }
1278
1279 /* Put an array of dwords in to main memory */
1280 static inline int put_dwords(EHCIState *ehci, uint32_t addr,
1281 uint32_t *buf, int num)
1282 {
1283 int i;
1284
1285 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1286 uint32_t tmp = cpu_to_le32(*buf);
1287 pci_dma_write(&ehci->dev, addr, &tmp, sizeof(tmp));
1288 }
1289
1290 return 1;
1291 }
1292
1293 /*
1294 * Write the qh back to guest physical memory. This step isn't
1295 * in the EHCI spec but we need to do it since we don't share
1296 * physical memory with our guest VM.
1297 *
1298 * The first three dwords are read-only for the EHCI, so skip them
1299 * when writing back the qh.
1300 */
1301 static void ehci_flush_qh(EHCIQueue *q)
1302 {
1303 uint32_t *qh = (uint32_t *) &q->qh;
1304 uint32_t dwords = sizeof(EHCIqh) >> 2;
1305 uint32_t addr = NLPTR_GET(q->qhaddr);
1306
1307 put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3);
1308 }
1309
1310 // 4.10.2
1311
1312 static int ehci_qh_do_overlay(EHCIQueue *q)
1313 {
1314 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1315 int i;
1316 int dtoggle;
1317 int ping;
1318 int eps;
1319 int reload;
1320
1321 assert(p != NULL);
1322 assert(p->qtdaddr == q->qtdaddr);
1323
1324 // remember values in fields to preserve in qh after overlay
1325
1326 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE;
1327 ping = q->qh.token & QTD_TOKEN_PING;
1328
1329 q->qh.current_qtd = p->qtdaddr;
1330 q->qh.next_qtd = p->qtd.next;
1331 q->qh.altnext_qtd = p->qtd.altnext;
1332 q->qh.token = p->qtd.token;
1333
1334
1335 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS);
1336 if (eps == EHCI_QH_EPS_HIGH) {
1337 q->qh.token &= ~QTD_TOKEN_PING;
1338 q->qh.token |= ping;
1339 }
1340
1341 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1342 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1343
1344 for (i = 0; i < 5; i++) {
1345 q->qh.bufptr[i] = p->qtd.bufptr[i];
1346 }
1347
1348 if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
1349 // preserve QH DT bit
1350 q->qh.token &= ~QTD_TOKEN_DTOGGLE;
1351 q->qh.token |= dtoggle;
1352 }
1353
1354 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
1355 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
1356
1357 ehci_flush_qh(q);
1358
1359 return 0;
1360 }
1361
1362 static int ehci_init_transfer(EHCIPacket *p)
1363 {
1364 uint32_t cpage, offset, bytes, plen;
1365 dma_addr_t page;
1366
1367 cpage = get_field(p->qtd.token, QTD_TOKEN_CPAGE);
1368 bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES);
1369 offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK;
1370 pci_dma_sglist_init(&p->sgl, &p->queue->ehci->dev, 5);
1371
1372 while (bytes > 0) {
1373 if (cpage > 4) {
1374 fprintf(stderr, "cpage out of range (%d)\n", cpage);
1375 return USB_RET_PROCERR;
1376 }
1377
1378 page = p->qtd.bufptr[cpage] & QTD_BUFPTR_MASK;
1379 page += offset;
1380 plen = bytes;
1381 if (plen > 4096 - offset) {
1382 plen = 4096 - offset;
1383 offset = 0;
1384 cpage++;
1385 }
1386
1387 qemu_sglist_add(&p->sgl, page, plen);
1388 bytes -= plen;
1389 }
1390 return 0;
1391 }
1392
1393 static void ehci_finish_transfer(EHCIQueue *q, int status)
1394 {
1395 uint32_t cpage, offset;
1396
1397 if (status > 0) {
1398 /* update cpage & offset */
1399 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1400 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1401
1402 offset += status;
1403 cpage += offset >> QTD_BUFPTR_SH;
1404 offset &= ~QTD_BUFPTR_MASK;
1405
1406 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE);
1407 q->qh.bufptr[0] &= QTD_BUFPTR_MASK;
1408 q->qh.bufptr[0] |= offset;
1409 }
1410 }
1411
1412 static void ehci_async_complete_packet(USBPort *port, USBPacket *packet)
1413 {
1414 EHCIPacket *p;
1415 EHCIState *s = port->opaque;
1416 uint32_t portsc = s->portsc[port->index];
1417
1418 if (portsc & PORTSC_POWNER) {
1419 USBPort *companion = s->companion_ports[port->index];
1420 companion->ops->complete(companion, packet);
1421 return;
1422 }
1423
1424 p = container_of(packet, EHCIPacket, packet);
1425 trace_usb_ehci_packet_action(p->queue, p, "wakeup");
1426 assert(p->async == EHCI_ASYNC_INFLIGHT);
1427 p->async = EHCI_ASYNC_FINISHED;
1428 p->usb_status = packet->result;
1429
1430 if (p->queue->async) {
1431 qemu_bh_schedule(p->queue->ehci->async_bh);
1432 }
1433 }
1434
1435 static void ehci_execute_complete(EHCIQueue *q)
1436 {
1437 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1438
1439 assert(p != NULL);
1440 assert(p->qtdaddr == q->qtdaddr);
1441 assert(p->async != EHCI_ASYNC_INFLIGHT);
1442 p->async = EHCI_ASYNC_NONE;
1443
1444 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1445 q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status);
1446
1447 if (p->usb_status < 0) {
1448 switch (p->usb_status) {
1449 case USB_RET_IOERROR:
1450 case USB_RET_NODEV:
1451 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR);
1452 set_field(&q->qh.token, 0, QTD_TOKEN_CERR);
1453 ehci_raise_irq(q->ehci, USBSTS_ERRINT);
1454 break;
1455 case USB_RET_STALL:
1456 q->qh.token |= QTD_TOKEN_HALT;
1457 ehci_raise_irq(q->ehci, USBSTS_ERRINT);
1458 break;
1459 case USB_RET_NAK:
1460 set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT);
1461 return; /* We're not done yet with this transaction */
1462 case USB_RET_BABBLE:
1463 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1464 ehci_raise_irq(q->ehci, USBSTS_ERRINT);
1465 break;
1466 default:
1467 /* should not be triggerable */
1468 fprintf(stderr, "USB invalid response %d\n", p->usb_status);
1469 assert(0);
1470 break;
1471 }
1472 } else {
1473 // TODO check 4.12 for splits
1474
1475 if (p->tbytes && p->pid == USB_TOKEN_IN) {
1476 p->tbytes -= p->usb_status;
1477 } else {
1478 p->tbytes = 0;
1479 }
1480
1481 DPRINTF("updating tbytes to %d\n", p->tbytes);
1482 set_field(&q->qh.token, p->tbytes, QTD_TOKEN_TBYTES);
1483 }
1484 ehci_finish_transfer(q, p->usb_status);
1485 usb_packet_unmap(&p->packet, &p->sgl);
1486 qemu_sglist_destroy(&p->sgl);
1487
1488 q->qh.token ^= QTD_TOKEN_DTOGGLE;
1489 q->qh.token &= ~QTD_TOKEN_ACTIVE;
1490
1491 if (q->qh.token & QTD_TOKEN_IOC) {
1492 ehci_raise_irq(q->ehci, USBSTS_INT);
1493 }
1494 }
1495
1496 // 4.10.3
1497
1498 static int ehci_execute(EHCIPacket *p, const char *action)
1499 {
1500 USBEndpoint *ep;
1501 int ret;
1502 int endp;
1503
1504 if (!(p->qtd.token & QTD_TOKEN_ACTIVE)) {
1505 fprintf(stderr, "Attempting to execute inactive qtd\n");
1506 return USB_RET_PROCERR;
1507 }
1508
1509 p->tbytes = (p->qtd.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH;
1510 if (p->tbytes > BUFF_SIZE) {
1511 fprintf(stderr, "Request for more bytes than allowed\n");
1512 return USB_RET_PROCERR;
1513 }
1514
1515 p->pid = (p->qtd.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
1516 switch (p->pid) {
1517 case 0:
1518 p->pid = USB_TOKEN_OUT;
1519 break;
1520 case 1:
1521 p->pid = USB_TOKEN_IN;
1522 break;
1523 case 2:
1524 p->pid = USB_TOKEN_SETUP;
1525 break;
1526 default:
1527 fprintf(stderr, "bad token\n");
1528 break;
1529 }
1530
1531 if (ehci_init_transfer(p) != 0) {
1532 return USB_RET_PROCERR;
1533 }
1534
1535 endp = get_field(p->queue->qh.epchar, QH_EPCHAR_EP);
1536 ep = usb_ep_get(p->queue->dev, p->pid, endp);
1537
1538 usb_packet_setup(&p->packet, p->pid, ep, p->qtdaddr);
1539 usb_packet_map(&p->packet, &p->sgl);
1540
1541 trace_usb_ehci_packet_action(p->queue, p, action);
1542 ret = usb_handle_packet(p->queue->dev, &p->packet);
1543 DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd "
1544 "(total %d) endp %x ret %d\n",
1545 q->qhaddr, q->qh.next, q->qtdaddr, q->pid,
1546 q->packet.iov.size, q->tbytes, endp, ret);
1547
1548 if (ret > BUFF_SIZE) {
1549 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1550 return USB_RET_PROCERR;
1551 }
1552
1553 return ret;
1554 }
1555
1556 /* 4.7.2
1557 */
1558
1559 static int ehci_process_itd(EHCIState *ehci,
1560 EHCIitd *itd,
1561 uint32_t addr)
1562 {
1563 USBDevice *dev;
1564 USBEndpoint *ep;
1565 int ret;
1566 uint32_t i, len, pid, dir, devaddr, endp;
1567 uint32_t pg, off, ptr1, ptr2, max, mult;
1568
1569 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1570 devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1571 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1572 max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1573 mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);
1574
1575 for(i = 0; i < 8; i++) {
1576 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1577 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1578 off = itd->transact[i] & ITD_XACT_OFFSET_MASK;
1579 ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK);
1580 ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK);
1581 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1582
1583 if (len > max * mult) {
1584 len = max * mult;
1585 }
1586
1587 if (len > BUFF_SIZE) {
1588 return USB_RET_PROCERR;
1589 }
1590
1591 pci_dma_sglist_init(&ehci->isgl, &ehci->dev, 2);
1592 if (off + len > 4096) {
1593 /* transfer crosses page border */
1594 uint32_t len2 = off + len - 4096;
1595 uint32_t len1 = len - len2;
1596 qemu_sglist_add(&ehci->isgl, ptr1 + off, len1);
1597 qemu_sglist_add(&ehci->isgl, ptr2, len2);
1598 } else {
1599 qemu_sglist_add(&ehci->isgl, ptr1 + off, len);
1600 }
1601
1602 pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT;
1603
1604 dev = ehci_find_device(ehci, devaddr);
1605 ep = usb_ep_get(dev, pid, endp);
1606 if (ep && ep->type == USB_ENDPOINT_XFER_ISOC) {
1607 usb_packet_setup(&ehci->ipacket, pid, ep, addr);
1608 usb_packet_map(&ehci->ipacket, &ehci->isgl);
1609 ret = usb_handle_packet(dev, &ehci->ipacket);
1610 assert(ret != USB_RET_ASYNC);
1611 usb_packet_unmap(&ehci->ipacket, &ehci->isgl);
1612 } else {
1613 DPRINTF("ISOCH: attempt to addess non-iso endpoint\n");
1614 ret = USB_RET_NAK;
1615 }
1616 qemu_sglist_destroy(&ehci->isgl);
1617
1618 if (ret < 0) {
1619 switch (ret) {
1620 default:
1621 fprintf(stderr, "Unexpected iso usb result: %d\n", ret);
1622 /* Fall through */
1623 case USB_RET_IOERROR:
1624 case USB_RET_NODEV:
1625 /* 3.3.2: XACTERR is only allowed on IN transactions */
1626 if (dir) {
1627 itd->transact[i] |= ITD_XACT_XACTERR;
1628 ehci_raise_irq(ehci, USBSTS_ERRINT);
1629 }
1630 break;
1631 case USB_RET_BABBLE:
1632 itd->transact[i] |= ITD_XACT_BABBLE;
1633 ehci_raise_irq(ehci, USBSTS_ERRINT);
1634 break;
1635 case USB_RET_NAK:
1636 /* no data for us, so do a zero-length transfer */
1637 ret = 0;
1638 break;
1639 }
1640 }
1641 if (ret >= 0) {
1642 if (!dir) {
1643 /* OUT */
1644 set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH);
1645 } else {
1646 /* IN */
1647 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH);
1648 }
1649 }
1650 if (itd->transact[i] & ITD_XACT_IOC) {
1651 ehci_raise_irq(ehci, USBSTS_INT);
1652 }
1653 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1654 }
1655 }
1656 return 0;
1657 }
1658
1659
1660 /* This state is the entry point for asynchronous schedule
1661 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1662 */
1663 static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1664 {
1665 EHCIqh qh;
1666 int i = 0;
1667 int again = 0;
1668 uint32_t entry = ehci->asynclistaddr;
1669
1670 /* set reclamation flag at start event (4.8.6) */
1671 if (async) {
1672 ehci_set_usbsts(ehci, USBSTS_REC);
1673 }
1674
1675 ehci_queues_rip_unused(ehci, async, 0);
1676
1677 /* Find the head of the list (4.9.1.1) */
1678 for(i = 0; i < MAX_QH; i++) {
1679 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh,
1680 sizeof(EHCIqh) >> 2);
1681 ehci_trace_qh(NULL, NLPTR_GET(entry), &qh);
1682
1683 if (qh.epchar & QH_EPCHAR_H) {
1684 if (async) {
1685 entry |= (NLPTR_TYPE_QH << 1);
1686 }
1687
1688 ehci_set_fetch_addr(ehci, async, entry);
1689 ehci_set_state(ehci, async, EST_FETCHENTRY);
1690 again = 1;
1691 goto out;
1692 }
1693
1694 entry = qh.next;
1695 if (entry == ehci->asynclistaddr) {
1696 break;
1697 }
1698 }
1699
1700 /* no head found for list. */
1701
1702 ehci_set_state(ehci, async, EST_ACTIVE);
1703
1704 out:
1705 return again;
1706 }
1707
1708
1709 /* This state is the entry point for periodic schedule processing as
1710 * well as being a continuation state for async processing.
1711 */
1712 static int ehci_state_fetchentry(EHCIState *ehci, int async)
1713 {
1714 int again = 0;
1715 uint32_t entry = ehci_get_fetch_addr(ehci, async);
1716
1717 if (NLPTR_TBIT(entry)) {
1718 ehci_set_state(ehci, async, EST_ACTIVE);
1719 goto out;
1720 }
1721
1722 /* section 4.8, only QH in async schedule */
1723 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1724 fprintf(stderr, "non queue head request in async schedule\n");
1725 return -1;
1726 }
1727
1728 switch (NLPTR_TYPE_GET(entry)) {
1729 case NLPTR_TYPE_QH:
1730 ehci_set_state(ehci, async, EST_FETCHQH);
1731 again = 1;
1732 break;
1733
1734 case NLPTR_TYPE_ITD:
1735 ehci_set_state(ehci, async, EST_FETCHITD);
1736 again = 1;
1737 break;
1738
1739 case NLPTR_TYPE_STITD:
1740 ehci_set_state(ehci, async, EST_FETCHSITD);
1741 again = 1;
1742 break;
1743
1744 default:
1745 /* TODO: handle FSTN type */
1746 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1747 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1748 return -1;
1749 }
1750
1751 out:
1752 return again;
1753 }
1754
1755 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)
1756 {
1757 EHCIPacket *p;
1758 uint32_t entry, devaddr;
1759 EHCIQueue *q;
1760
1761 entry = ehci_get_fetch_addr(ehci, async);
1762 q = ehci_find_queue_by_qh(ehci, entry, async);
1763 if (NULL == q) {
1764 q = ehci_alloc_queue(ehci, entry, async);
1765 }
1766 p = QTAILQ_FIRST(&q->packets);
1767
1768 q->seen++;
1769 if (q->seen > 1) {
1770 /* we are going in circles -- stop processing */
1771 ehci_set_state(ehci, async, EST_ACTIVE);
1772 q = NULL;
1773 goto out;
1774 }
1775
1776 get_dwords(ehci, NLPTR_GET(q->qhaddr),
1777 (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2);
1778 ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh);
1779
1780 devaddr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR);
1781 if (q->dev != NULL && q->dev->addr != devaddr) {
1782 if (!QTAILQ_EMPTY(&q->packets)) {
1783 /* should not happen (guest bug) */
1784 ehci_cancel_queue(q);
1785 }
1786 q->dev = NULL;
1787 }
1788 if (q->dev == NULL) {
1789 q->dev = ehci_find_device(q->ehci, devaddr);
1790 }
1791
1792 if (p && p->async == EHCI_ASYNC_FINISHED) {
1793 /* I/O finished -- continue processing queue */
1794 trace_usb_ehci_packet_action(p->queue, p, "complete");
1795 ehci_set_state(ehci, async, EST_EXECUTING);
1796 goto out;
1797 }
1798
1799 if (async && (q->qh.epchar & QH_EPCHAR_H)) {
1800
1801 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1802 if (ehci->usbsts & USBSTS_REC) {
1803 ehci_clear_usbsts(ehci, USBSTS_REC);
1804 } else {
1805 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1806 " - done processing\n", q->qhaddr);
1807 ehci_set_state(ehci, async, EST_ACTIVE);
1808 q = NULL;
1809 goto out;
1810 }
1811 }
1812
1813 #if EHCI_DEBUG
1814 if (q->qhaddr != q->qh.next) {
1815 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1816 q->qhaddr,
1817 q->qh.epchar & QH_EPCHAR_H,
1818 q->qh.token & QTD_TOKEN_HALT,
1819 q->qh.token & QTD_TOKEN_ACTIVE,
1820 q->qh.next);
1821 }
1822 #endif
1823
1824 if (q->qh.token & QTD_TOKEN_HALT) {
1825 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1826
1827 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) &&
1828 (NLPTR_TBIT(q->qh.current_qtd) == 0)) {
1829 q->qtdaddr = q->qh.current_qtd;
1830 ehci_set_state(ehci, async, EST_FETCHQTD);
1831
1832 } else {
1833 /* EHCI spec version 1.0 Section 4.10.2 */
1834 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1835 }
1836
1837 out:
1838 return q;
1839 }
1840
1841 static int ehci_state_fetchitd(EHCIState *ehci, int async)
1842 {
1843 uint32_t entry;
1844 EHCIitd itd;
1845
1846 assert(!async);
1847 entry = ehci_get_fetch_addr(ehci, async);
1848
1849 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1850 sizeof(EHCIitd) >> 2);
1851 ehci_trace_itd(ehci, entry, &itd);
1852
1853 if (ehci_process_itd(ehci, &itd, entry) != 0) {
1854 return -1;
1855 }
1856
1857 put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1858 sizeof(EHCIitd) >> 2);
1859 ehci_set_fetch_addr(ehci, async, itd.next);
1860 ehci_set_state(ehci, async, EST_FETCHENTRY);
1861
1862 return 1;
1863 }
1864
1865 static int ehci_state_fetchsitd(EHCIState *ehci, int async)
1866 {
1867 uint32_t entry;
1868 EHCIsitd sitd;
1869
1870 assert(!async);
1871 entry = ehci_get_fetch_addr(ehci, async);
1872
1873 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd,
1874 sizeof(EHCIsitd) >> 2);
1875 ehci_trace_sitd(ehci, entry, &sitd);
1876
1877 if (!(sitd.results & SITD_RESULTS_ACTIVE)) {
1878 /* siTD is not active, nothing to do */;
1879 } else {
1880 /* TODO: split transfers are not implemented */
1881 fprintf(stderr, "WARNING: Skipping active siTD\n");
1882 }
1883
1884 ehci_set_fetch_addr(ehci, async, sitd.next);
1885 ehci_set_state(ehci, async, EST_FETCHENTRY);
1886 return 1;
1887 }
1888
1889 /* Section 4.10.2 - paragraph 3 */
1890 static int ehci_state_advqueue(EHCIQueue *q)
1891 {
1892 #if 0
1893 /* TO-DO: 4.10.2 - paragraph 2
1894 * if I-bit is set to 1 and QH is not active
1895 * go to horizontal QH
1896 */
1897 if (I-bit set) {
1898 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1899 goto out;
1900 }
1901 #endif
1902
1903 /*
1904 * want data and alt-next qTD is valid
1905 */
1906 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1907 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
1908 q->qtdaddr = q->qh.altnext_qtd;
1909 ehci_set_state(q->ehci, q->async, EST_FETCHQTD);
1910
1911 /*
1912 * next qTD is valid
1913 */
1914 } else if (NLPTR_TBIT(q->qh.next_qtd) == 0) {
1915 q->qtdaddr = q->qh.next_qtd;
1916 ehci_set_state(q->ehci, q->async, EST_FETCHQTD);
1917
1918 /*
1919 * no valid qTD, try next QH
1920 */
1921 } else {
1922 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1923 }
1924
1925 return 1;
1926 }
1927
1928 /* Section 4.10.2 - paragraph 4 */
1929 static int ehci_state_fetchqtd(EHCIQueue *q)
1930 {
1931 EHCIqtd qtd;
1932 EHCIPacket *p;
1933 int again = 0;
1934
1935 get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &qtd,
1936 sizeof(EHCIqtd) >> 2);
1937 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &qtd);
1938
1939 p = QTAILQ_FIRST(&q->packets);
1940 if (p != NULL) {
1941 if (p->qtdaddr != q->qtdaddr ||
1942 (!NLPTR_TBIT(p->qtd.next) && (p->qtd.next != qtd.next)) ||
1943 (!NLPTR_TBIT(p->qtd.altnext) && (p->qtd.altnext != qtd.altnext)) ||
1944 p->qtd.bufptr[0] != qtd.bufptr[0]) {
1945 /* guest bug: guest updated active QH or qTD underneath us */
1946 ehci_cancel_queue(q);
1947 p = NULL;
1948 } else {
1949 p->qtd = qtd;
1950 ehci_qh_do_overlay(q);
1951 }
1952 }
1953
1954 if (!(qtd.token & QTD_TOKEN_ACTIVE)) {
1955 if (p != NULL) {
1956 /* transfer canceled by guest (clear active) */
1957 ehci_cancel_queue(q);
1958 p = NULL;
1959 }
1960 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1961 again = 1;
1962 } else if (p != NULL) {
1963 switch (p->async) {
1964 case EHCI_ASYNC_NONE:
1965 /* Previously nacked packet (likely interrupt ep) */
1966 ehci_set_state(q->ehci, q->async, EST_EXECUTE);
1967 break;
1968 case EHCI_ASYNC_INFLIGHT:
1969 /* Unfinyshed async handled packet, go horizontal */
1970 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1971 break;
1972 case EHCI_ASYNC_FINISHED:
1973 /* Should never happen, as this case is caught by fetchqh */
1974 ehci_set_state(q->ehci, q->async, EST_EXECUTING);
1975 break;
1976 }
1977 again = 1;
1978 } else {
1979 p = ehci_alloc_packet(q);
1980 p->qtdaddr = q->qtdaddr;
1981 p->qtd = qtd;
1982 ehci_set_state(q->ehci, q->async, EST_EXECUTE);
1983 again = 1;
1984 }
1985
1986 return again;
1987 }
1988
1989 static int ehci_state_horizqh(EHCIQueue *q)
1990 {
1991 int again = 0;
1992
1993 if (ehci_get_fetch_addr(q->ehci, q->async) != q->qh.next) {
1994 ehci_set_fetch_addr(q->ehci, q->async, q->qh.next);
1995 ehci_set_state(q->ehci, q->async, EST_FETCHENTRY);
1996 again = 1;
1997 } else {
1998 ehci_set_state(q->ehci, q->async, EST_ACTIVE);
1999 }
2000
2001 return again;
2002 }
2003
2004 static void ehci_fill_queue(EHCIPacket *p)
2005 {
2006 EHCIQueue *q = p->queue;
2007 EHCIqtd qtd = p->qtd;
2008 uint32_t qtdaddr;
2009
2010 for (;;) {
2011 if (NLPTR_TBIT(qtd.altnext) == 0) {
2012 break;
2013 }
2014 if (NLPTR_TBIT(qtd.next) != 0) {
2015 break;
2016 }
2017 qtdaddr = qtd.next;
2018 get_dwords(q->ehci, NLPTR_GET(qtdaddr),
2019 (uint32_t *) &qtd, sizeof(EHCIqtd) >> 2);
2020 ehci_trace_qtd(q, NLPTR_GET(qtdaddr), &qtd);
2021 if (!(qtd.token & QTD_TOKEN_ACTIVE)) {
2022 break;
2023 }
2024 p = ehci_alloc_packet(q);
2025 p->qtdaddr = qtdaddr;
2026 p->qtd = qtd;
2027 p->usb_status = ehci_execute(p, "queue");
2028 assert(p->usb_status == USB_RET_ASYNC);
2029 p->async = EHCI_ASYNC_INFLIGHT;
2030 }
2031 }
2032
2033 static int ehci_state_execute(EHCIQueue *q)
2034 {
2035 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
2036 int again = 0;
2037
2038 assert(p != NULL);
2039 assert(p->qtdaddr == q->qtdaddr);
2040
2041 if (ehci_qh_do_overlay(q) != 0) {
2042 return -1;
2043 }
2044
2045 // TODO verify enough time remains in the uframe as in 4.4.1.1
2046 // TODO write back ptr to async list when done or out of time
2047 // TODO Windows does not seem to ever set the MULT field
2048
2049 if (!q->async) {
2050 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
2051 if (!transactCtr) {
2052 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2053 again = 1;
2054 goto out;
2055 }
2056 }
2057
2058 if (q->async) {
2059 ehci_set_usbsts(q->ehci, USBSTS_REC);
2060 }
2061
2062 p->usb_status = ehci_execute(p, "process");
2063 if (p->usb_status == USB_RET_PROCERR) {
2064 again = -1;
2065 goto out;
2066 }
2067 if (p->usb_status == USB_RET_ASYNC) {
2068 ehci_flush_qh(q);
2069 trace_usb_ehci_packet_action(p->queue, p, "async");
2070 p->async = EHCI_ASYNC_INFLIGHT;
2071 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2072 again = 1;
2073 ehci_fill_queue(p);
2074 goto out;
2075 }
2076
2077 ehci_set_state(q->ehci, q->async, EST_EXECUTING);
2078 again = 1;
2079
2080 out:
2081 return again;
2082 }
2083
2084 static int ehci_state_executing(EHCIQueue *q)
2085 {
2086 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
2087
2088 assert(p != NULL);
2089 assert(p->qtdaddr == q->qtdaddr);
2090
2091 ehci_execute_complete(q);
2092
2093 // 4.10.3
2094 if (!q->async) {
2095 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
2096 transactCtr--;
2097 set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT);
2098 // 4.10.3, bottom of page 82, should exit this state when transaction
2099 // counter decrements to 0
2100 }
2101
2102 /* 4.10.5 */
2103 if (p->usb_status == USB_RET_NAK) {
2104 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2105 } else {
2106 ehci_set_state(q->ehci, q->async, EST_WRITEBACK);
2107 }
2108
2109 ehci_flush_qh(q);
2110 return 1;
2111 }
2112
2113
2114 static int ehci_state_writeback(EHCIQueue *q)
2115 {
2116 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
2117 uint32_t *qtd, addr;
2118 int again = 0;
2119
2120 /* Write back the QTD from the QH area */
2121 assert(p != NULL);
2122 assert(p->qtdaddr == q->qtdaddr);
2123
2124 ehci_trace_qtd(q, NLPTR_GET(p->qtdaddr), (EHCIqtd *) &q->qh.next_qtd);
2125 qtd = (uint32_t *) &q->qh.next_qtd;
2126 addr = NLPTR_GET(p->qtdaddr);
2127 put_dwords(q->ehci, addr + 2 * sizeof(uint32_t), qtd + 2, 2);
2128 ehci_free_packet(p);
2129
2130 /*
2131 * EHCI specs say go horizontal here.
2132 *
2133 * We can also advance the queue here for performance reasons. We
2134 * need to take care to only take that shortcut in case we've
2135 * processed the qtd just written back without errors, i.e. halt
2136 * bit is clear.
2137 */
2138 if (q->qh.token & QTD_TOKEN_HALT) {
2139 /*
2140 * We should not do any further processing on a halted queue!
2141 * This is esp. important for bulk endpoints with pipelining enabled
2142 * (redirection to a real USB device), where we must cancel all the
2143 * transfers after this one so that:
2144 * 1) If they've completed already, they are not processed further
2145 * causing more stalls, originating from the same failed transfer
2146 * 2) If still in flight, they are cancelled before the guest does
2147 * a clear stall, otherwise the guest and device can loose sync!
2148 */
2149 while ((p = QTAILQ_FIRST(&q->packets)) != NULL) {
2150 ehci_free_packet(p);
2151 }
2152 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
2153 again = 1;
2154 } else {
2155 ehci_set_state(q->ehci, q->async, EST_ADVANCEQUEUE);
2156 again = 1;
2157 }
2158 return again;
2159 }
2160
2161 /*
2162 * This is the state machine that is common to both async and periodic
2163 */
2164
2165 static void ehci_advance_state(EHCIState *ehci, int async)
2166 {
2167 EHCIQueue *q = NULL;
2168 int again;
2169
2170 do {
2171 switch(ehci_get_state(ehci, async)) {
2172 case EST_WAITLISTHEAD:
2173 again = ehci_state_waitlisthead(ehci, async);
2174 break;
2175
2176 case EST_FETCHENTRY:
2177 again = ehci_state_fetchentry(ehci, async);
2178 break;
2179
2180 case EST_FETCHQH:
2181 q = ehci_state_fetchqh(ehci, async);
2182 if (q != NULL) {
2183 assert(q->async == async);
2184 again = 1;
2185 } else {
2186 again = 0;
2187 }
2188 break;
2189
2190 case EST_FETCHITD:
2191 again = ehci_state_fetchitd(ehci, async);
2192 break;
2193
2194 case EST_FETCHSITD:
2195 again = ehci_state_fetchsitd(ehci, async);
2196 break;
2197
2198 case EST_ADVANCEQUEUE:
2199 again = ehci_state_advqueue(q);
2200 break;
2201
2202 case EST_FETCHQTD:
2203 again = ehci_state_fetchqtd(q);
2204 break;
2205
2206 case EST_HORIZONTALQH:
2207 again = ehci_state_horizqh(q);
2208 break;
2209
2210 case EST_EXECUTE:
2211 again = ehci_state_execute(q);
2212 if (async) {
2213 ehci->async_stepdown = 0;
2214 }
2215 break;
2216
2217 case EST_EXECUTING:
2218 assert(q != NULL);
2219 if (async) {
2220 ehci->async_stepdown = 0;
2221 }
2222 again = ehci_state_executing(q);
2223 break;
2224
2225 case EST_WRITEBACK:
2226 assert(q != NULL);
2227 again = ehci_state_writeback(q);
2228 break;
2229
2230 default:
2231 fprintf(stderr, "Bad state!\n");
2232 again = -1;
2233 assert(0);
2234 break;
2235 }
2236
2237 if (again < 0) {
2238 fprintf(stderr, "processing error - resetting ehci HC\n");
2239 ehci_reset(ehci);
2240 again = 0;
2241 }
2242 }
2243 while (again);
2244 }
2245
2246 static void ehci_advance_async_state(EHCIState *ehci)
2247 {
2248 const int async = 1;
2249
2250 switch(ehci_get_state(ehci, async)) {
2251 case EST_INACTIVE:
2252 if (!ehci_async_enabled(ehci)) {
2253 break;
2254 }
2255 ehci_set_state(ehci, async, EST_ACTIVE);
2256 // No break, fall through to ACTIVE
2257
2258 case EST_ACTIVE:
2259 if (!ehci_async_enabled(ehci)) {
2260 ehci_queues_rip_all(ehci, async);
2261 ehci_set_state(ehci, async, EST_INACTIVE);
2262 break;
2263 }
2264
2265 /* make sure guest has acknowledged the doorbell interrupt */
2266 /* TO-DO: is this really needed? */
2267 if (ehci->usbsts & USBSTS_IAA) {
2268 DPRINTF("IAA status bit still set.\n");
2269 break;
2270 }
2271
2272 /* check that address register has been set */
2273 if (ehci->asynclistaddr == 0) {
2274 break;
2275 }
2276
2277 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
2278 ehci_advance_state(ehci, async);
2279
2280 /* If the doorbell is set, the guest wants to make a change to the
2281 * schedule. The host controller needs to release cached data.
2282 * (section 4.8.2)
2283 */
2284 if (ehci->usbcmd & USBCMD_IAAD) {
2285 /* Remove all unseen qhs from the async qhs queue */
2286 ehci_queues_rip_unused(ehci, async, 1);
2287 DPRINTF("ASYNC: doorbell request acknowledged\n");
2288 ehci->usbcmd &= ~USBCMD_IAAD;
2289 ehci_raise_irq(ehci, USBSTS_IAA);
2290 }
2291 break;
2292
2293 default:
2294 /* this should only be due to a developer mistake */
2295 fprintf(stderr, "ehci: Bad asynchronous state %d. "
2296 "Resetting to active\n", ehci->astate);
2297 assert(0);
2298 }
2299 }
2300
2301 static void ehci_advance_periodic_state(EHCIState *ehci)
2302 {
2303 uint32_t entry;
2304 uint32_t list;
2305 const int async = 0;
2306
2307 // 4.6
2308
2309 switch(ehci_get_state(ehci, async)) {
2310 case EST_INACTIVE:
2311 if (!(ehci->frindex & 7) && ehci_periodic_enabled(ehci)) {
2312 ehci_set_state(ehci, async, EST_ACTIVE);
2313 // No break, fall through to ACTIVE
2314 } else
2315 break;
2316
2317 case EST_ACTIVE:
2318 if (!(ehci->frindex & 7) && !ehci_periodic_enabled(ehci)) {
2319 ehci_queues_rip_all(ehci, async);
2320 ehci_set_state(ehci, async, EST_INACTIVE);
2321 break;
2322 }
2323
2324 list = ehci->periodiclistbase & 0xfffff000;
2325 /* check that register has been set */
2326 if (list == 0) {
2327 break;
2328 }
2329 list |= ((ehci->frindex & 0x1ff8) >> 1);
2330
2331 pci_dma_read(&ehci->dev, list, &entry, sizeof entry);
2332 entry = le32_to_cpu(entry);
2333
2334 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2335 ehci->frindex / 8, list, entry);
2336 ehci_set_fetch_addr(ehci, async,entry);
2337 ehci_set_state(ehci, async, EST_FETCHENTRY);
2338 ehci_advance_state(ehci, async);
2339 ehci_queues_rip_unused(ehci, async, 0);
2340 break;
2341
2342 default:
2343 /* this should only be due to a developer mistake */
2344 fprintf(stderr, "ehci: Bad periodic state %d. "
2345 "Resetting to active\n", ehci->pstate);
2346 assert(0);
2347 }
2348 }
2349
2350 static void ehci_update_frindex(EHCIState *ehci, int frames)
2351 {
2352 int i;
2353
2354 if (!ehci_enabled(ehci)) {
2355 return;
2356 }
2357
2358 for (i = 0; i < frames; i++) {
2359 ehci->frindex += 8;
2360
2361 if (ehci->frindex == 0x00002000) {
2362 ehci_raise_irq(ehci, USBSTS_FLR);
2363 }
2364
2365 if (ehci->frindex == 0x00004000) {
2366 ehci_raise_irq(ehci, USBSTS_FLR);
2367 ehci->frindex = 0;
2368 if (ehci->usbsts_frindex > 0x00004000) {
2369 ehci->usbsts_frindex -= 0x00004000;
2370 } else {
2371 ehci->usbsts_frindex = 0;
2372 }
2373 }
2374 }
2375 }
2376
2377 static void ehci_frame_timer(void *opaque)
2378 {
2379 EHCIState *ehci = opaque;
2380 int need_timer = 0;
2381 int64_t expire_time, t_now;
2382 uint64_t ns_elapsed;
2383 int frames, skipped_frames;
2384 int i;
2385
2386 t_now = qemu_get_clock_ns(vm_clock);
2387 ns_elapsed = t_now - ehci->last_run_ns;
2388 frames = ns_elapsed / FRAME_TIMER_NS;
2389
2390 if (ehci_periodic_enabled(ehci) || ehci->pstate != EST_INACTIVE) {
2391 need_timer++;
2392 ehci->async_stepdown = 0;
2393
2394 if (frames > ehci->maxframes) {
2395 skipped_frames = frames - ehci->maxframes;
2396 ehci_update_frindex(ehci, skipped_frames);
2397 ehci->last_run_ns += FRAME_TIMER_NS * skipped_frames;
2398 frames -= skipped_frames;
2399 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
2400 }
2401
2402 for (i = 0; i < frames; i++) {
2403 ehci_update_frindex(ehci, 1);
2404 ehci_advance_periodic_state(ehci);
2405 ehci->last_run_ns += FRAME_TIMER_NS;
2406 }
2407 } else {
2408 if (ehci->async_stepdown < ehci->maxframes / 2) {
2409 ehci->async_stepdown++;
2410 }
2411 ehci_update_frindex(ehci, frames);
2412 ehci->last_run_ns += FRAME_TIMER_NS * frames;
2413 }
2414
2415 /* Async is not inside loop since it executes everything it can once
2416 * called
2417 */
2418 if (ehci_async_enabled(ehci) || ehci->astate != EST_INACTIVE) {
2419 need_timer++;
2420 ehci_advance_async_state(ehci);
2421 }
2422
2423 ehci_commit_irq(ehci);
2424 if (ehci->usbsts_pending) {
2425 need_timer++;
2426 ehci->async_stepdown = 0;
2427 }
2428
2429 if (need_timer) {
2430 expire_time = t_now + (get_ticks_per_sec()
2431 * (ehci->async_stepdown+1) / FRAME_TIMER_FREQ);
2432 qemu_mod_timer(ehci->frame_timer, expire_time);
2433 }
2434 }
2435
2436 static void ehci_async_bh(void *opaque)
2437 {
2438 EHCIState *ehci = opaque;
2439 ehci_advance_async_state(ehci);
2440 }
2441
2442 static const MemoryRegionOps ehci_mem_ops = {
2443 .old_mmio = {
2444 .read = { ehci_mem_readb, ehci_mem_readw, ehci_mem_readl },
2445 .write = { ehci_mem_writeb, ehci_mem_writew, ehci_mem_writel },
2446 },
2447 .endianness = DEVICE_LITTLE_ENDIAN,
2448 };
2449
2450 static int usb_ehci_initfn(PCIDevice *dev);
2451
2452 static USBPortOps ehci_port_ops = {
2453 .attach = ehci_attach,
2454 .detach = ehci_detach,
2455 .child_detach = ehci_child_detach,
2456 .wakeup = ehci_wakeup,
2457 .complete = ehci_async_complete_packet,
2458 };
2459
2460 static USBBusOps ehci_bus_ops = {
2461 .register_companion = ehci_register_companion,
2462 };
2463
2464 static int usb_ehci_post_load(void *opaque, int version_id)
2465 {
2466 EHCIState *s = opaque;
2467 int i;
2468
2469 for (i = 0; i < NB_PORTS; i++) {
2470 USBPort *companion = s->companion_ports[i];
2471 if (companion == NULL) {
2472 continue;
2473 }
2474 if (s->portsc[i] & PORTSC_POWNER) {
2475 companion->dev = s->ports[i].dev;
2476 } else {
2477 companion->dev = NULL;
2478 }
2479 }
2480
2481 return 0;
2482 }
2483
2484 static const VMStateDescription vmstate_ehci = {
2485 .name = "ehci",
2486 .version_id = 2,
2487 .minimum_version_id = 1,
2488 .post_load = usb_ehci_post_load,
2489 .fields = (VMStateField[]) {
2490 VMSTATE_PCI_DEVICE(dev, EHCIState),
2491 /* mmio registers */
2492 VMSTATE_UINT32(usbcmd, EHCIState),
2493 VMSTATE_UINT32(usbsts, EHCIState),
2494 VMSTATE_UINT32_V(usbsts_pending, EHCIState, 2),
2495 VMSTATE_UINT32_V(usbsts_frindex, EHCIState, 2),
2496 VMSTATE_UINT32(usbintr, EHCIState),
2497 VMSTATE_UINT32(frindex, EHCIState),
2498 VMSTATE_UINT32(ctrldssegment, EHCIState),
2499 VMSTATE_UINT32(periodiclistbase, EHCIState),
2500 VMSTATE_UINT32(asynclistaddr, EHCIState),
2501 VMSTATE_UINT32(configflag, EHCIState),
2502 VMSTATE_UINT32(portsc[0], EHCIState),
2503 VMSTATE_UINT32(portsc[1], EHCIState),
2504 VMSTATE_UINT32(portsc[2], EHCIState),
2505 VMSTATE_UINT32(portsc[3], EHCIState),
2506 VMSTATE_UINT32(portsc[4], EHCIState),
2507 VMSTATE_UINT32(portsc[5], EHCIState),
2508 /* frame timer */
2509 VMSTATE_TIMER(frame_timer, EHCIState),
2510 VMSTATE_UINT64(last_run_ns, EHCIState),
2511 VMSTATE_UINT32(async_stepdown, EHCIState),
2512 /* schedule state */
2513 VMSTATE_UINT32(astate, EHCIState),
2514 VMSTATE_UINT32(pstate, EHCIState),
2515 VMSTATE_UINT32(a_fetch_addr, EHCIState),
2516 VMSTATE_UINT32(p_fetch_addr, EHCIState),
2517 VMSTATE_END_OF_LIST()
2518 }
2519 };
2520
2521 static Property ehci_properties[] = {
2522 DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128),
2523 DEFINE_PROP_END_OF_LIST(),
2524 };
2525
2526 static void ehci_class_init(ObjectClass *klass, void *data)
2527 {
2528 DeviceClass *dc = DEVICE_CLASS(klass);
2529 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2530
2531 k->init = usb_ehci_initfn;
2532 k->vendor_id = PCI_VENDOR_ID_INTEL;
2533 k->device_id = PCI_DEVICE_ID_INTEL_82801D; /* ich4 */
2534 k->revision = 0x10;
2535 k->class_id = PCI_CLASS_SERIAL_USB;
2536 dc->vmsd = &vmstate_ehci;
2537 dc->props = ehci_properties;
2538 }
2539
2540 static TypeInfo ehci_info = {
2541 .name = "usb-ehci",
2542 .parent = TYPE_PCI_DEVICE,
2543 .instance_size = sizeof(EHCIState),
2544 .class_init = ehci_class_init,
2545 };
2546
2547 static void ich9_ehci_class_init(ObjectClass *klass, void *data)
2548 {
2549 DeviceClass *dc = DEVICE_CLASS(klass);
2550 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2551
2552 k->init = usb_ehci_initfn;
2553 k->vendor_id = PCI_VENDOR_ID_INTEL;
2554 k->device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1;
2555 k->revision = 0x03;
2556 k->class_id = PCI_CLASS_SERIAL_USB;
2557 dc->vmsd = &vmstate_ehci;
2558 dc->props = ehci_properties;
2559 }
2560
2561 static TypeInfo ich9_ehci_info = {
2562 .name = "ich9-usb-ehci1",
2563 .parent = TYPE_PCI_DEVICE,
2564 .instance_size = sizeof(EHCIState),
2565 .class_init = ich9_ehci_class_init,
2566 };
2567
2568 static int usb_ehci_initfn(PCIDevice *dev)
2569 {
2570 EHCIState *s = DO_UPCAST(EHCIState, dev, dev);
2571 uint8_t *pci_conf = s->dev.config;
2572 int i;
2573
2574 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
2575
2576 /* capabilities pointer */
2577 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
2578 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2579
2580 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */
2581 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
2582 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
2583
2584 // pci_conf[0x50] = 0x01; // power management caps
2585
2586 pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4)
2587 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5)
2588 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6)
2589
2590 pci_conf[0x64] = 0x00;
2591 pci_conf[0x65] = 0x00;
2592 pci_conf[0x66] = 0x00;
2593 pci_conf[0x67] = 0x00;
2594 pci_conf[0x68] = 0x01;
2595 pci_conf[0x69] = 0x00;
2596 pci_conf[0x6a] = 0x00;
2597 pci_conf[0x6b] = 0x00; // USBLEGSUP
2598 pci_conf[0x6c] = 0x00;
2599 pci_conf[0x6d] = 0x00;
2600 pci_conf[0x6e] = 0x00;
2601 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS
2602
2603 // 2.2 host controller interface version
2604 s->mmio[0x00] = (uint8_t) OPREGBASE;
2605 s->mmio[0x01] = 0x00;
2606 s->mmio[0x02] = 0x00;
2607 s->mmio[0x03] = 0x01; // HC version
2608 s->mmio[0x04] = NB_PORTS; // Number of downstream ports
2609 s->mmio[0x05] = 0x00; // No companion ports at present
2610 s->mmio[0x06] = 0x00;
2611 s->mmio[0x07] = 0x00;
2612 s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2613 s->mmio[0x09] = 0x68; // EECP
2614 s->mmio[0x0a] = 0x00;
2615 s->mmio[0x0b] = 0x00;
2616
2617 s->irq = s->dev.irq[3];
2618
2619 usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev);
2620 for(i = 0; i < NB_PORTS; i++) {
2621 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2622 USB_SPEED_MASK_HIGH);
2623 s->ports[i].dev = 0;
2624 }
2625
2626 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2627 s->async_bh = qemu_bh_new(ehci_async_bh, s);
2628 QTAILQ_INIT(&s->aqueues);
2629 QTAILQ_INIT(&s->pqueues);
2630 usb_packet_init(&s->ipacket);
2631
2632 qemu_register_reset(ehci_reset, s);
2633
2634 memory_region_init_io(&s->mem, &ehci_mem_ops, s, "ehci", MMIO_SIZE);
2635 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
2636
2637 return 0;
2638 }
2639
2640 static void ehci_register_types(void)
2641 {
2642 type_register_static(&ehci_info);
2643 type_register_static(&ich9_ehci_info);
2644 }
2645
2646 type_init(ehci_register_types)
2647
2648 /*
2649 * vim: expandtab ts=4
2650 */
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