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ehci: Fixup q->qtdaddr after cancelling an already completed packet
[mirror_qemu.git] / hw / usb / hcd-ehci.c
1 /*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 * Copyright(c) 2011-2012 Red Hat, Inc.
6 *
7 * Red Hat Authors:
8 * Gerd Hoffmann <kraxel@redhat.com>
9 * Hans de Goede <hdegoede@redhat.com>
10 *
11 * EHCI project was started by Mark Burkley, with contributions by
12 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
13 * Jan Kiszka and Vincent Palatin contributed bugfixes.
14 *
15 *
16 * This library is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU Lesser General Public
18 * License as published by the Free Software Foundation; either
19 * version 2 of the License, or(at your option) any later version.
20 *
21 * This library is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
24 * Lesser General Public License for more details.
25 *
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, see <http://www.gnu.org/licenses/>.
28 */
29
30 #include "hw/usb/hcd-ehci.h"
31
32 /* Capability Registers Base Address - section 2.2 */
33 #define CAPLENGTH 0x0000 /* 1-byte, 0x0001 reserved */
34 #define HCIVERSION 0x0002 /* 2-bytes, i/f version # */
35 #define HCSPARAMS 0x0004 /* 4-bytes, structural params */
36 #define HCCPARAMS 0x0008 /* 4-bytes, capability params */
37 #define EECP HCCPARAMS + 1
38 #define HCSPPORTROUTE1 0x000c
39 #define HCSPPORTROUTE2 0x0010
40
41 #define USBCMD 0x0000
42 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
43 #define USBCMD_HCRESET (1 << 1) // HC Reset
44 #define USBCMD_FLS (3 << 2) // Frame List Size
45 #define USBCMD_FLS_SH 2 // Frame List Size Shift
46 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
47 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
48 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
49 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
50 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
51 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
52 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
53 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
54
55 #define USBSTS 0x0004
56 #define USBSTS_RO_MASK 0x0000003f
57 #define USBSTS_INT (1 << 0) // USB Interrupt
58 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
59 #define USBSTS_PCD (1 << 2) // Port Change Detect
60 #define USBSTS_FLR (1 << 3) // Frame List Rollover
61 #define USBSTS_HSE (1 << 4) // Host System Error
62 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
63 #define USBSTS_HALT (1 << 12) // HC Halted
64 #define USBSTS_REC (1 << 13) // Reclamation
65 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
66 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
67
68 /*
69 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
70 * so no need to redefine here.
71 */
72 #define USBINTR 0x0008
73 #define USBINTR_MASK 0x0000003f
74
75 #define FRINDEX 0x000c
76 #define CTRLDSSEGMENT 0x0010
77 #define PERIODICLISTBASE 0x0014
78 #define ASYNCLISTADDR 0x0018
79 #define ASYNCLISTADDR_MASK 0xffffffe0
80
81 #define CONFIGFLAG 0x0040
82
83 /*
84 * Bits that are reserved or are read-only are masked out of values
85 * written to us by software
86 */
87 #define PORTSC_RO_MASK 0x007001c0
88 #define PORTSC_RWC_MASK 0x0000002a
89 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
90 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
91 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
92 #define PORTSC_PTC (15 << 16) // Port Test Control
93 #define PORTSC_PTC_SH 16 // Port Test Control shift
94 #define PORTSC_PIC (3 << 14) // Port Indicator Control
95 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
96 #define PORTSC_POWNER (1 << 13) // Port Owner
97 #define PORTSC_PPOWER (1 << 12) // Port Power
98 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
99 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
100 #define PORTSC_PRESET (1 << 8) // Port Reset
101 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
102 #define PORTSC_FPRES (1 << 6) // Force Port Resume
103 #define PORTSC_OCC (1 << 5) // Over Current Change
104 #define PORTSC_OCA (1 << 4) // Over Current Active
105 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
106 #define PORTSC_PED (1 << 2) // Port Enable/Disable
107 #define PORTSC_CSC (1 << 1) // Connect Status Change
108 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
109
110 #define FRAME_TIMER_FREQ 1000
111 #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ)
112
113 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
114 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
115 #define MAX_QH 100 // Max allowable queue heads in a chain
116 #define MIN_FR_PER_TICK 3 // Min frames to process when catching up
117
118 /* Internal periodic / asynchronous schedule state machine states
119 */
120 typedef enum {
121 EST_INACTIVE = 1000,
122 EST_ACTIVE,
123 EST_EXECUTING,
124 EST_SLEEPING,
125 /* The following states are internal to the state machine function
126 */
127 EST_WAITLISTHEAD,
128 EST_FETCHENTRY,
129 EST_FETCHQH,
130 EST_FETCHITD,
131 EST_FETCHSITD,
132 EST_ADVANCEQUEUE,
133 EST_FETCHQTD,
134 EST_EXECUTE,
135 EST_WRITEBACK,
136 EST_HORIZONTALQH
137 } EHCI_STATES;
138
139 /* macros for accessing fields within next link pointer entry */
140 #define NLPTR_GET(x) ((x) & 0xffffffe0)
141 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
142 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
143
144 /* link pointer types */
145 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
146 #define NLPTR_TYPE_QH 1 // queue head
147 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
148 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
149
150 #define SET_LAST_RUN_CLOCK(s) \
151 (s)->last_run_ns = qemu_get_clock_ns(vm_clock);
152
153 /* nifty macros from Arnon's EHCI version */
154 #define get_field(data, field) \
155 (((data) & field##_MASK) >> field##_SH)
156
157 #define set_field(data, newval, field) do { \
158 uint32_t val = *data; \
159 val &= ~ field##_MASK; \
160 val |= ((newval) << field##_SH) & field##_MASK; \
161 *data = val; \
162 } while(0)
163
164 static const char *ehci_state_names[] = {
165 [EST_INACTIVE] = "INACTIVE",
166 [EST_ACTIVE] = "ACTIVE",
167 [EST_EXECUTING] = "EXECUTING",
168 [EST_SLEEPING] = "SLEEPING",
169 [EST_WAITLISTHEAD] = "WAITLISTHEAD",
170 [EST_FETCHENTRY] = "FETCH ENTRY",
171 [EST_FETCHQH] = "FETCH QH",
172 [EST_FETCHITD] = "FETCH ITD",
173 [EST_ADVANCEQUEUE] = "ADVANCEQUEUE",
174 [EST_FETCHQTD] = "FETCH QTD",
175 [EST_EXECUTE] = "EXECUTE",
176 [EST_WRITEBACK] = "WRITEBACK",
177 [EST_HORIZONTALQH] = "HORIZONTALQH",
178 };
179
180 static const char *ehci_mmio_names[] = {
181 [USBCMD] = "USBCMD",
182 [USBSTS] = "USBSTS",
183 [USBINTR] = "USBINTR",
184 [FRINDEX] = "FRINDEX",
185 [PERIODICLISTBASE] = "P-LIST BASE",
186 [ASYNCLISTADDR] = "A-LIST ADDR",
187 [CONFIGFLAG] = "CONFIGFLAG",
188 };
189
190 static int ehci_state_executing(EHCIQueue *q);
191 static int ehci_state_writeback(EHCIQueue *q);
192 static int ehci_state_advqueue(EHCIQueue *q);
193 static int ehci_fill_queue(EHCIPacket *p);
194
195 static const char *nr2str(const char **n, size_t len, uint32_t nr)
196 {
197 if (nr < len && n[nr] != NULL) {
198 return n[nr];
199 } else {
200 return "unknown";
201 }
202 }
203
204 static const char *state2str(uint32_t state)
205 {
206 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
207 }
208
209 static const char *addr2str(hwaddr addr)
210 {
211 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
212 }
213
214 static void ehci_trace_usbsts(uint32_t mask, int state)
215 {
216 /* interrupts */
217 if (mask & USBSTS_INT) {
218 trace_usb_ehci_usbsts("INT", state);
219 }
220 if (mask & USBSTS_ERRINT) {
221 trace_usb_ehci_usbsts("ERRINT", state);
222 }
223 if (mask & USBSTS_PCD) {
224 trace_usb_ehci_usbsts("PCD", state);
225 }
226 if (mask & USBSTS_FLR) {
227 trace_usb_ehci_usbsts("FLR", state);
228 }
229 if (mask & USBSTS_HSE) {
230 trace_usb_ehci_usbsts("HSE", state);
231 }
232 if (mask & USBSTS_IAA) {
233 trace_usb_ehci_usbsts("IAA", state);
234 }
235
236 /* status */
237 if (mask & USBSTS_HALT) {
238 trace_usb_ehci_usbsts("HALT", state);
239 }
240 if (mask & USBSTS_REC) {
241 trace_usb_ehci_usbsts("REC", state);
242 }
243 if (mask & USBSTS_PSS) {
244 trace_usb_ehci_usbsts("PSS", state);
245 }
246 if (mask & USBSTS_ASS) {
247 trace_usb_ehci_usbsts("ASS", state);
248 }
249 }
250
251 static inline void ehci_set_usbsts(EHCIState *s, int mask)
252 {
253 if ((s->usbsts & mask) == mask) {
254 return;
255 }
256 ehci_trace_usbsts(mask, 1);
257 s->usbsts |= mask;
258 }
259
260 static inline void ehci_clear_usbsts(EHCIState *s, int mask)
261 {
262 if ((s->usbsts & mask) == 0) {
263 return;
264 }
265 ehci_trace_usbsts(mask, 0);
266 s->usbsts &= ~mask;
267 }
268
269 /* update irq line */
270 static inline void ehci_update_irq(EHCIState *s)
271 {
272 int level = 0;
273
274 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
275 level = 1;
276 }
277
278 trace_usb_ehci_irq(level, s->frindex, s->usbsts, s->usbintr);
279 qemu_set_irq(s->irq, level);
280 }
281
282 /* flag interrupt condition */
283 static inline void ehci_raise_irq(EHCIState *s, int intr)
284 {
285 if (intr & (USBSTS_PCD | USBSTS_FLR | USBSTS_HSE)) {
286 s->usbsts |= intr;
287 ehci_update_irq(s);
288 } else {
289 s->usbsts_pending |= intr;
290 }
291 }
292
293 /*
294 * Commit pending interrupts (added via ehci_raise_irq),
295 * at the rate allowed by "Interrupt Threshold Control".
296 */
297 static inline void ehci_commit_irq(EHCIState *s)
298 {
299 uint32_t itc;
300
301 if (!s->usbsts_pending) {
302 return;
303 }
304 if (s->usbsts_frindex > s->frindex) {
305 return;
306 }
307
308 itc = (s->usbcmd >> 16) & 0xff;
309 s->usbsts |= s->usbsts_pending;
310 s->usbsts_pending = 0;
311 s->usbsts_frindex = s->frindex + itc;
312 ehci_update_irq(s);
313 }
314
315 static void ehci_update_halt(EHCIState *s)
316 {
317 if (s->usbcmd & USBCMD_RUNSTOP) {
318 ehci_clear_usbsts(s, USBSTS_HALT);
319 } else {
320 if (s->astate == EST_INACTIVE && s->pstate == EST_INACTIVE) {
321 ehci_set_usbsts(s, USBSTS_HALT);
322 }
323 }
324 }
325
326 static void ehci_set_state(EHCIState *s, int async, int state)
327 {
328 if (async) {
329 trace_usb_ehci_state("async", state2str(state));
330 s->astate = state;
331 if (s->astate == EST_INACTIVE) {
332 ehci_clear_usbsts(s, USBSTS_ASS);
333 ehci_update_halt(s);
334 } else {
335 ehci_set_usbsts(s, USBSTS_ASS);
336 }
337 } else {
338 trace_usb_ehci_state("periodic", state2str(state));
339 s->pstate = state;
340 if (s->pstate == EST_INACTIVE) {
341 ehci_clear_usbsts(s, USBSTS_PSS);
342 ehci_update_halt(s);
343 } else {
344 ehci_set_usbsts(s, USBSTS_PSS);
345 }
346 }
347 }
348
349 static int ehci_get_state(EHCIState *s, int async)
350 {
351 return async ? s->astate : s->pstate;
352 }
353
354 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr)
355 {
356 if (async) {
357 s->a_fetch_addr = addr;
358 } else {
359 s->p_fetch_addr = addr;
360 }
361 }
362
363 static int ehci_get_fetch_addr(EHCIState *s, int async)
364 {
365 return async ? s->a_fetch_addr : s->p_fetch_addr;
366 }
367
368 static void ehci_trace_qh(EHCIQueue *q, hwaddr addr, EHCIqh *qh)
369 {
370 /* need three here due to argument count limits */
371 trace_usb_ehci_qh_ptrs(q, addr, qh->next,
372 qh->current_qtd, qh->next_qtd, qh->altnext_qtd);
373 trace_usb_ehci_qh_fields(addr,
374 get_field(qh->epchar, QH_EPCHAR_RL),
375 get_field(qh->epchar, QH_EPCHAR_MPLEN),
376 get_field(qh->epchar, QH_EPCHAR_EPS),
377 get_field(qh->epchar, QH_EPCHAR_EP),
378 get_field(qh->epchar, QH_EPCHAR_DEVADDR));
379 trace_usb_ehci_qh_bits(addr,
380 (bool)(qh->epchar & QH_EPCHAR_C),
381 (bool)(qh->epchar & QH_EPCHAR_H),
382 (bool)(qh->epchar & QH_EPCHAR_DTC),
383 (bool)(qh->epchar & QH_EPCHAR_I));
384 }
385
386 static void ehci_trace_qtd(EHCIQueue *q, hwaddr addr, EHCIqtd *qtd)
387 {
388 /* need three here due to argument count limits */
389 trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext);
390 trace_usb_ehci_qtd_fields(addr,
391 get_field(qtd->token, QTD_TOKEN_TBYTES),
392 get_field(qtd->token, QTD_TOKEN_CPAGE),
393 get_field(qtd->token, QTD_TOKEN_CERR),
394 get_field(qtd->token, QTD_TOKEN_PID));
395 trace_usb_ehci_qtd_bits(addr,
396 (bool)(qtd->token & QTD_TOKEN_IOC),
397 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
398 (bool)(qtd->token & QTD_TOKEN_HALT),
399 (bool)(qtd->token & QTD_TOKEN_BABBLE),
400 (bool)(qtd->token & QTD_TOKEN_XACTERR));
401 }
402
403 static void ehci_trace_itd(EHCIState *s, hwaddr addr, EHCIitd *itd)
404 {
405 trace_usb_ehci_itd(addr, itd->next,
406 get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
407 get_field(itd->bufptr[2], ITD_BUFPTR_MULT),
408 get_field(itd->bufptr[0], ITD_BUFPTR_EP),
409 get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
410 }
411
412 static void ehci_trace_sitd(EHCIState *s, hwaddr addr,
413 EHCIsitd *sitd)
414 {
415 trace_usb_ehci_sitd(addr, sitd->next,
416 (bool)(sitd->results & SITD_RESULTS_ACTIVE));
417 }
418
419 static void ehci_trace_guest_bug(EHCIState *s, const char *message)
420 {
421 trace_usb_ehci_guest_bug(message);
422 fprintf(stderr, "ehci warning: %s\n", message);
423 }
424
425 static inline bool ehci_enabled(EHCIState *s)
426 {
427 return s->usbcmd & USBCMD_RUNSTOP;
428 }
429
430 static inline bool ehci_async_enabled(EHCIState *s)
431 {
432 return ehci_enabled(s) && (s->usbcmd & USBCMD_ASE);
433 }
434
435 static inline bool ehci_periodic_enabled(EHCIState *s)
436 {
437 return ehci_enabled(s) && (s->usbcmd & USBCMD_PSE);
438 }
439
440 /* packet management */
441
442 static EHCIPacket *ehci_alloc_packet(EHCIQueue *q)
443 {
444 EHCIPacket *p;
445
446 p = g_new0(EHCIPacket, 1);
447 p->queue = q;
448 usb_packet_init(&p->packet);
449 QTAILQ_INSERT_TAIL(&q->packets, p, next);
450 trace_usb_ehci_packet_action(p->queue, p, "alloc");
451 return p;
452 }
453
454 static void ehci_free_packet(EHCIPacket *p)
455 {
456 if (p->async == EHCI_ASYNC_FINISHED) {
457 EHCIQueue *q = p->queue;
458 int state = ehci_get_state(q->ehci, q->async);
459 /* This is a normal, but rare condition (cancel racing completion) */
460 fprintf(stderr, "EHCI: Warning packet completed but not processed\n");
461 ehci_state_executing(q);
462 ehci_state_writeback(q);
463 if (!(q->qh.token & QTD_TOKEN_HALT)) {
464 ehci_state_advqueue(q);
465 }
466 ehci_set_state(q->ehci, q->async, state);
467 /* state_writeback recurses into us with async == EHCI_ASYNC_NONE!! */
468 return;
469 }
470 trace_usb_ehci_packet_action(p->queue, p, "free");
471 if (p->async == EHCI_ASYNC_INITIALIZED) {
472 usb_packet_unmap(&p->packet, &p->sgl);
473 qemu_sglist_destroy(&p->sgl);
474 }
475 if (p->async == EHCI_ASYNC_INFLIGHT) {
476 usb_cancel_packet(&p->packet);
477 usb_packet_unmap(&p->packet, &p->sgl);
478 qemu_sglist_destroy(&p->sgl);
479 }
480 QTAILQ_REMOVE(&p->queue->packets, p, next);
481 usb_packet_cleanup(&p->packet);
482 g_free(p);
483 }
484
485 /* queue management */
486
487 static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, uint32_t addr, int async)
488 {
489 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
490 EHCIQueue *q;
491
492 q = g_malloc0(sizeof(*q));
493 q->ehci = ehci;
494 q->qhaddr = addr;
495 q->async = async;
496 QTAILQ_INIT(&q->packets);
497 QTAILQ_INSERT_HEAD(head, q, next);
498 trace_usb_ehci_queue_action(q, "alloc");
499 return q;
500 }
501
502 static int ehci_cancel_queue(EHCIQueue *q)
503 {
504 EHCIPacket *p;
505 int packets = 0;
506
507 p = QTAILQ_FIRST(&q->packets);
508 if (p == NULL) {
509 return 0;
510 }
511
512 trace_usb_ehci_queue_action(q, "cancel");
513 do {
514 ehci_free_packet(p);
515 packets++;
516 } while ((p = QTAILQ_FIRST(&q->packets)) != NULL);
517 return packets;
518 }
519
520 static int ehci_reset_queue(EHCIQueue *q)
521 {
522 int packets;
523
524 trace_usb_ehci_queue_action(q, "reset");
525 packets = ehci_cancel_queue(q);
526 q->dev = NULL;
527 q->qtdaddr = 0;
528 return packets;
529 }
530
531 static void ehci_free_queue(EHCIQueue *q, const char *warn)
532 {
533 EHCIQueueHead *head = q->async ? &q->ehci->aqueues : &q->ehci->pqueues;
534 int cancelled;
535
536 trace_usb_ehci_queue_action(q, "free");
537 cancelled = ehci_cancel_queue(q);
538 if (warn && cancelled > 0) {
539 ehci_trace_guest_bug(q->ehci, warn);
540 }
541 QTAILQ_REMOVE(head, q, next);
542 g_free(q);
543 }
544
545 static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr,
546 int async)
547 {
548 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
549 EHCIQueue *q;
550
551 QTAILQ_FOREACH(q, head, next) {
552 if (addr == q->qhaddr) {
553 return q;
554 }
555 }
556 return NULL;
557 }
558
559 static void ehci_queues_rip_unused(EHCIState *ehci, int async)
560 {
561 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
562 const char *warn = async ? "guest unlinked busy QH" : NULL;
563 uint64_t maxage = FRAME_TIMER_NS * ehci->maxframes * 4;
564 EHCIQueue *q, *tmp;
565
566 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
567 if (q->seen) {
568 q->seen = 0;
569 q->ts = ehci->last_run_ns;
570 continue;
571 }
572 if (ehci->last_run_ns < q->ts + maxage) {
573 continue;
574 }
575 ehci_free_queue(q, warn);
576 }
577 }
578
579 static void ehci_queues_rip_unseen(EHCIState *ehci, int async)
580 {
581 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
582 EHCIQueue *q, *tmp;
583
584 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
585 if (!q->seen) {
586 ehci_free_queue(q, NULL);
587 }
588 }
589 }
590
591 static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async)
592 {
593 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
594 EHCIQueue *q, *tmp;
595
596 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
597 if (q->dev != dev) {
598 continue;
599 }
600 ehci_free_queue(q, NULL);
601 }
602 }
603
604 static void ehci_queues_rip_all(EHCIState *ehci, int async)
605 {
606 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
607 const char *warn = async ? "guest stopped busy async schedule" : NULL;
608 EHCIQueue *q, *tmp;
609
610 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
611 ehci_free_queue(q, warn);
612 }
613 }
614
615 /* Attach or detach a device on root hub */
616
617 static void ehci_attach(USBPort *port)
618 {
619 EHCIState *s = port->opaque;
620 uint32_t *portsc = &s->portsc[port->index];
621 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci";
622
623 trace_usb_ehci_port_attach(port->index, owner, port->dev->product_desc);
624
625 if (*portsc & PORTSC_POWNER) {
626 USBPort *companion = s->companion_ports[port->index];
627 companion->dev = port->dev;
628 companion->ops->attach(companion);
629 return;
630 }
631
632 *portsc |= PORTSC_CONNECT;
633 *portsc |= PORTSC_CSC;
634
635 ehci_raise_irq(s, USBSTS_PCD);
636 ehci_commit_irq(s);
637 }
638
639 static void ehci_detach(USBPort *port)
640 {
641 EHCIState *s = port->opaque;
642 uint32_t *portsc = &s->portsc[port->index];
643 const char *owner = (*portsc & PORTSC_POWNER) ? "comp" : "ehci";
644
645 trace_usb_ehci_port_detach(port->index, owner);
646
647 if (*portsc & PORTSC_POWNER) {
648 USBPort *companion = s->companion_ports[port->index];
649 companion->ops->detach(companion);
650 companion->dev = NULL;
651 /*
652 * EHCI spec 4.2.2: "When a disconnect occurs... On the event,
653 * the port ownership is returned immediately to the EHCI controller."
654 */
655 *portsc &= ~PORTSC_POWNER;
656 return;
657 }
658
659 ehci_queues_rip_device(s, port->dev, 0);
660 ehci_queues_rip_device(s, port->dev, 1);
661
662 *portsc &= ~(PORTSC_CONNECT|PORTSC_PED);
663 *portsc |= PORTSC_CSC;
664
665 ehci_raise_irq(s, USBSTS_PCD);
666 ehci_commit_irq(s);
667 }
668
669 static void ehci_child_detach(USBPort *port, USBDevice *child)
670 {
671 EHCIState *s = port->opaque;
672 uint32_t portsc = s->portsc[port->index];
673
674 if (portsc & PORTSC_POWNER) {
675 USBPort *companion = s->companion_ports[port->index];
676 companion->ops->child_detach(companion, child);
677 return;
678 }
679
680 ehci_queues_rip_device(s, child, 0);
681 ehci_queues_rip_device(s, child, 1);
682 }
683
684 static void ehci_wakeup(USBPort *port)
685 {
686 EHCIState *s = port->opaque;
687 uint32_t portsc = s->portsc[port->index];
688
689 if (portsc & PORTSC_POWNER) {
690 USBPort *companion = s->companion_ports[port->index];
691 if (companion->ops->wakeup) {
692 companion->ops->wakeup(companion);
693 }
694 return;
695 }
696
697 qemu_bh_schedule(s->async_bh);
698 }
699
700 static int ehci_register_companion(USBBus *bus, USBPort *ports[],
701 uint32_t portcount, uint32_t firstport)
702 {
703 EHCIState *s = container_of(bus, EHCIState, bus);
704 uint32_t i;
705
706 if (firstport + portcount > NB_PORTS) {
707 qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport",
708 "firstport on masterbus");
709 error_printf_unless_qmp(
710 "firstport value of %u makes companion take ports %u - %u, which "
711 "is outside of the valid range of 0 - %u\n", firstport, firstport,
712 firstport + portcount - 1, NB_PORTS - 1);
713 return -1;
714 }
715
716 for (i = 0; i < portcount; i++) {
717 if (s->companion_ports[firstport + i]) {
718 qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus",
719 "an USB masterbus");
720 error_printf_unless_qmp(
721 "port %u on masterbus %s already has a companion assigned\n",
722 firstport + i, bus->qbus.name);
723 return -1;
724 }
725 }
726
727 for (i = 0; i < portcount; i++) {
728 s->companion_ports[firstport + i] = ports[i];
729 s->ports[firstport + i].speedmask |=
730 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL;
731 /* Ensure devs attached before the initial reset go to the companion */
732 s->portsc[firstport + i] = PORTSC_POWNER;
733 }
734
735 s->companion_count++;
736 s->caps[0x05] = (s->companion_count << 4) | portcount;
737
738 return 0;
739 }
740
741 static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr)
742 {
743 USBDevice *dev;
744 USBPort *port;
745 int i;
746
747 for (i = 0; i < NB_PORTS; i++) {
748 port = &ehci->ports[i];
749 if (!(ehci->portsc[i] & PORTSC_PED)) {
750 DPRINTF("Port %d not enabled\n", i);
751 continue;
752 }
753 dev = usb_find_device(port, addr);
754 if (dev != NULL) {
755 return dev;
756 }
757 }
758 return NULL;
759 }
760
761 /* 4.1 host controller initialization */
762 static void ehci_reset(void *opaque)
763 {
764 EHCIState *s = opaque;
765 int i;
766 USBDevice *devs[NB_PORTS];
767
768 trace_usb_ehci_reset();
769
770 /*
771 * Do the detach before touching portsc, so that it correctly gets send to
772 * us or to our companion based on PORTSC_POWNER before the reset.
773 */
774 for(i = 0; i < NB_PORTS; i++) {
775 devs[i] = s->ports[i].dev;
776 if (devs[i] && devs[i]->attached) {
777 usb_detach(&s->ports[i]);
778 }
779 }
780
781 memset(&s->opreg, 0x00, sizeof(s->opreg));
782 memset(&s->portsc, 0x00, sizeof(s->portsc));
783
784 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
785 s->usbsts = USBSTS_HALT;
786 s->usbsts_pending = 0;
787 s->usbsts_frindex = 0;
788
789 s->astate = EST_INACTIVE;
790 s->pstate = EST_INACTIVE;
791
792 for(i = 0; i < NB_PORTS; i++) {
793 if (s->companion_ports[i]) {
794 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
795 } else {
796 s->portsc[i] = PORTSC_PPOWER;
797 }
798 if (devs[i] && devs[i]->attached) {
799 usb_attach(&s->ports[i]);
800 usb_device_reset(devs[i]);
801 }
802 }
803 ehci_queues_rip_all(s, 0);
804 ehci_queues_rip_all(s, 1);
805 qemu_del_timer(s->frame_timer);
806 qemu_bh_cancel(s->async_bh);
807 }
808
809 static uint64_t ehci_caps_read(void *ptr, hwaddr addr,
810 unsigned size)
811 {
812 EHCIState *s = ptr;
813 return s->caps[addr];
814 }
815
816 static uint64_t ehci_opreg_read(void *ptr, hwaddr addr,
817 unsigned size)
818 {
819 EHCIState *s = ptr;
820 uint32_t val;
821
822 val = s->opreg[addr >> 2];
823 trace_usb_ehci_opreg_read(addr + s->opregbase, addr2str(addr), val);
824 return val;
825 }
826
827 static uint64_t ehci_port_read(void *ptr, hwaddr addr,
828 unsigned size)
829 {
830 EHCIState *s = ptr;
831 uint32_t val;
832
833 val = s->portsc[addr >> 2];
834 trace_usb_ehci_portsc_read(addr + PORTSC_BEGIN, addr >> 2, val);
835 return val;
836 }
837
838 static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner)
839 {
840 USBDevice *dev = s->ports[port].dev;
841 uint32_t *portsc = &s->portsc[port];
842 uint32_t orig;
843
844 if (s->companion_ports[port] == NULL)
845 return;
846
847 owner = owner & PORTSC_POWNER;
848 orig = *portsc & PORTSC_POWNER;
849
850 if (!(owner ^ orig)) {
851 return;
852 }
853
854 if (dev && dev->attached) {
855 usb_detach(&s->ports[port]);
856 }
857
858 *portsc &= ~PORTSC_POWNER;
859 *portsc |= owner;
860
861 if (dev && dev->attached) {
862 usb_attach(&s->ports[port]);
863 }
864 }
865
866 static void ehci_port_write(void *ptr, hwaddr addr,
867 uint64_t val, unsigned size)
868 {
869 EHCIState *s = ptr;
870 int port = addr >> 2;
871 uint32_t *portsc = &s->portsc[port];
872 uint32_t old = *portsc;
873 USBDevice *dev = s->ports[port].dev;
874
875 trace_usb_ehci_portsc_write(addr + PORTSC_BEGIN, addr >> 2, val);
876
877 /* Clear rwc bits */
878 *portsc &= ~(val & PORTSC_RWC_MASK);
879 /* The guest may clear, but not set the PED bit */
880 *portsc &= val | ~PORTSC_PED;
881 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */
882 handle_port_owner_write(s, port, val);
883 /* And finally apply RO_MASK */
884 val &= PORTSC_RO_MASK;
885
886 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
887 trace_usb_ehci_port_reset(port, 1);
888 }
889
890 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
891 trace_usb_ehci_port_reset(port, 0);
892 if (dev && dev->attached) {
893 usb_port_reset(&s->ports[port]);
894 *portsc &= ~PORTSC_CSC;
895 }
896
897 /*
898 * Table 2.16 Set the enable bit(and enable bit change) to indicate
899 * to SW that this port has a high speed device attached
900 */
901 if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) {
902 val |= PORTSC_PED;
903 }
904 }
905
906 *portsc &= ~PORTSC_RO_MASK;
907 *portsc |= val;
908 trace_usb_ehci_portsc_change(addr + PORTSC_BEGIN, addr >> 2, *portsc, old);
909 }
910
911 static void ehci_opreg_write(void *ptr, hwaddr addr,
912 uint64_t val, unsigned size)
913 {
914 EHCIState *s = ptr;
915 uint32_t *mmio = s->opreg + (addr >> 2);
916 uint32_t old = *mmio;
917 int i;
918
919 trace_usb_ehci_opreg_write(addr + s->opregbase, addr2str(addr), val);
920
921 switch (addr) {
922 case USBCMD:
923 if (val & USBCMD_HCRESET) {
924 ehci_reset(s);
925 val = s->usbcmd;
926 break;
927 }
928
929 /* not supporting dynamic frame list size at the moment */
930 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
931 fprintf(stderr, "attempt to set frame list size -- value %d\n",
932 (int)val & USBCMD_FLS);
933 val &= ~USBCMD_FLS;
934 }
935
936 if (val & USBCMD_IAAD) {
937 /*
938 * Process IAAD immediately, otherwise the Linux IAAD watchdog may
939 * trigger and re-use a qh without us seeing the unlink.
940 */
941 s->async_stepdown = 0;
942 qemu_bh_schedule(s->async_bh);
943 trace_usb_ehci_doorbell_ring();
944 }
945
946 if (((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & val) !=
947 ((USBCMD_RUNSTOP | USBCMD_PSE | USBCMD_ASE) & s->usbcmd)) {
948 if (s->pstate == EST_INACTIVE) {
949 SET_LAST_RUN_CLOCK(s);
950 }
951 s->usbcmd = val; /* Set usbcmd for ehci_update_halt() */
952 ehci_update_halt(s);
953 s->async_stepdown = 0;
954 qemu_bh_schedule(s->async_bh);
955 }
956 break;
957
958 case USBSTS:
959 val &= USBSTS_RO_MASK; // bits 6 through 31 are RO
960 ehci_clear_usbsts(s, val); // bits 0 through 5 are R/WC
961 val = s->usbsts;
962 ehci_update_irq(s);
963 break;
964
965 case USBINTR:
966 val &= USBINTR_MASK;
967 break;
968
969 case FRINDEX:
970 val &= 0x00003ff8; /* frindex is 14bits and always a multiple of 8 */
971 break;
972
973 case CONFIGFLAG:
974 val &= 0x1;
975 if (val) {
976 for(i = 0; i < NB_PORTS; i++)
977 handle_port_owner_write(s, i, 0);
978 }
979 break;
980
981 case PERIODICLISTBASE:
982 if (ehci_periodic_enabled(s)) {
983 fprintf(stderr,
984 "ehci: PERIODIC list base register set while periodic schedule\n"
985 " is enabled and HC is enabled\n");
986 }
987 break;
988
989 case ASYNCLISTADDR:
990 if (ehci_async_enabled(s)) {
991 fprintf(stderr,
992 "ehci: ASYNC list address register set while async schedule\n"
993 " is enabled and HC is enabled\n");
994 }
995 break;
996 }
997
998 *mmio = val;
999 trace_usb_ehci_opreg_change(addr + s->opregbase, addr2str(addr),
1000 *mmio, old);
1001 }
1002
1003
1004 // TODO : Put in common header file, duplication from usb-ohci.c
1005
1006 /* Get an array of dwords from main memory */
1007 static inline int get_dwords(EHCIState *ehci, uint32_t addr,
1008 uint32_t *buf, int num)
1009 {
1010 int i;
1011
1012 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1013 dma_memory_read(ehci->dma, addr, buf, sizeof(*buf));
1014 *buf = le32_to_cpu(*buf);
1015 }
1016
1017 return 1;
1018 }
1019
1020 /* Put an array of dwords in to main memory */
1021 static inline int put_dwords(EHCIState *ehci, uint32_t addr,
1022 uint32_t *buf, int num)
1023 {
1024 int i;
1025
1026 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1027 uint32_t tmp = cpu_to_le32(*buf);
1028 dma_memory_write(ehci->dma, addr, &tmp, sizeof(tmp));
1029 }
1030
1031 return 1;
1032 }
1033
1034 /*
1035 * Write the qh back to guest physical memory. This step isn't
1036 * in the EHCI spec but we need to do it since we don't share
1037 * physical memory with our guest VM.
1038 *
1039 * The first three dwords are read-only for the EHCI, so skip them
1040 * when writing back the qh.
1041 */
1042 static void ehci_flush_qh(EHCIQueue *q)
1043 {
1044 uint32_t *qh = (uint32_t *) &q->qh;
1045 uint32_t dwords = sizeof(EHCIqh) >> 2;
1046 uint32_t addr = NLPTR_GET(q->qhaddr);
1047
1048 put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3);
1049 }
1050
1051 // 4.10.2
1052
1053 static int ehci_qh_do_overlay(EHCIQueue *q)
1054 {
1055 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1056 int i;
1057 int dtoggle;
1058 int ping;
1059 int eps;
1060 int reload;
1061
1062 assert(p != NULL);
1063 assert(p->qtdaddr == q->qtdaddr);
1064
1065 // remember values in fields to preserve in qh after overlay
1066
1067 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE;
1068 ping = q->qh.token & QTD_TOKEN_PING;
1069
1070 q->qh.current_qtd = p->qtdaddr;
1071 q->qh.next_qtd = p->qtd.next;
1072 q->qh.altnext_qtd = p->qtd.altnext;
1073 q->qh.token = p->qtd.token;
1074
1075
1076 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS);
1077 if (eps == EHCI_QH_EPS_HIGH) {
1078 q->qh.token &= ~QTD_TOKEN_PING;
1079 q->qh.token |= ping;
1080 }
1081
1082 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1083 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1084
1085 for (i = 0; i < 5; i++) {
1086 q->qh.bufptr[i] = p->qtd.bufptr[i];
1087 }
1088
1089 if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
1090 // preserve QH DT bit
1091 q->qh.token &= ~QTD_TOKEN_DTOGGLE;
1092 q->qh.token |= dtoggle;
1093 }
1094
1095 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
1096 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
1097
1098 ehci_flush_qh(q);
1099
1100 return 0;
1101 }
1102
1103 static int ehci_init_transfer(EHCIPacket *p)
1104 {
1105 uint32_t cpage, offset, bytes, plen;
1106 dma_addr_t page;
1107
1108 cpage = get_field(p->qtd.token, QTD_TOKEN_CPAGE);
1109 bytes = get_field(p->qtd.token, QTD_TOKEN_TBYTES);
1110 offset = p->qtd.bufptr[0] & ~QTD_BUFPTR_MASK;
1111 qemu_sglist_init(&p->sgl, 5, p->queue->ehci->dma);
1112
1113 while (bytes > 0) {
1114 if (cpage > 4) {
1115 fprintf(stderr, "cpage out of range (%d)\n", cpage);
1116 return -1;
1117 }
1118
1119 page = p->qtd.bufptr[cpage] & QTD_BUFPTR_MASK;
1120 page += offset;
1121 plen = bytes;
1122 if (plen > 4096 - offset) {
1123 plen = 4096 - offset;
1124 offset = 0;
1125 cpage++;
1126 }
1127
1128 qemu_sglist_add(&p->sgl, page, plen);
1129 bytes -= plen;
1130 }
1131 return 0;
1132 }
1133
1134 static void ehci_finish_transfer(EHCIQueue *q, int len)
1135 {
1136 uint32_t cpage, offset;
1137
1138 if (len > 0) {
1139 /* update cpage & offset */
1140 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1141 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1142
1143 offset += len;
1144 cpage += offset >> QTD_BUFPTR_SH;
1145 offset &= ~QTD_BUFPTR_MASK;
1146
1147 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE);
1148 q->qh.bufptr[0] &= QTD_BUFPTR_MASK;
1149 q->qh.bufptr[0] |= offset;
1150 }
1151 }
1152
1153 static void ehci_async_complete_packet(USBPort *port, USBPacket *packet)
1154 {
1155 EHCIPacket *p;
1156 EHCIState *s = port->opaque;
1157 uint32_t portsc = s->portsc[port->index];
1158
1159 if (portsc & PORTSC_POWNER) {
1160 USBPort *companion = s->companion_ports[port->index];
1161 companion->ops->complete(companion, packet);
1162 return;
1163 }
1164
1165 p = container_of(packet, EHCIPacket, packet);
1166 assert(p->async == EHCI_ASYNC_INFLIGHT);
1167
1168 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
1169 trace_usb_ehci_packet_action(p->queue, p, "remove");
1170 ehci_free_packet(p);
1171 return;
1172 }
1173
1174 trace_usb_ehci_packet_action(p->queue, p, "wakeup");
1175 p->async = EHCI_ASYNC_FINISHED;
1176
1177 if (p->queue->async) {
1178 qemu_bh_schedule(p->queue->ehci->async_bh);
1179 }
1180 }
1181
1182 static void ehci_execute_complete(EHCIQueue *q)
1183 {
1184 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1185 uint32_t tbytes;
1186
1187 assert(p != NULL);
1188 assert(p->qtdaddr == q->qtdaddr);
1189 assert(p->async == EHCI_ASYNC_INITIALIZED ||
1190 p->async == EHCI_ASYNC_FINISHED);
1191
1192 DPRINTF("execute_complete: qhaddr 0x%x, next 0x%x, qtdaddr 0x%x, "
1193 "status %d, actual_length %d\n",
1194 q->qhaddr, q->qh.next, q->qtdaddr,
1195 p->packet.status, p->packet.actual_length);
1196
1197 switch (p->packet.status) {
1198 case USB_RET_SUCCESS:
1199 break;
1200 case USB_RET_IOERROR:
1201 case USB_RET_NODEV:
1202 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR);
1203 set_field(&q->qh.token, 0, QTD_TOKEN_CERR);
1204 ehci_raise_irq(q->ehci, USBSTS_ERRINT);
1205 break;
1206 case USB_RET_STALL:
1207 q->qh.token |= QTD_TOKEN_HALT;
1208 ehci_raise_irq(q->ehci, USBSTS_ERRINT);
1209 break;
1210 case USB_RET_NAK:
1211 set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT);
1212 return; /* We're not done yet with this transaction */
1213 case USB_RET_BABBLE:
1214 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1215 ehci_raise_irq(q->ehci, USBSTS_ERRINT);
1216 break;
1217 default:
1218 /* should not be triggerable */
1219 fprintf(stderr, "USB invalid response %d\n", p->packet.status);
1220 assert(0);
1221 break;
1222 }
1223
1224 /* TODO check 4.12 for splits */
1225 tbytes = get_field(q->qh.token, QTD_TOKEN_TBYTES);
1226 if (tbytes && p->pid == USB_TOKEN_IN) {
1227 tbytes -= p->packet.actual_length;
1228 if (tbytes) {
1229 /* 4.15.1.2 must raise int on a short input packet */
1230 ehci_raise_irq(q->ehci, USBSTS_INT);
1231 }
1232 } else {
1233 tbytes = 0;
1234 }
1235 DPRINTF("updating tbytes to %d\n", tbytes);
1236 set_field(&q->qh.token, tbytes, QTD_TOKEN_TBYTES);
1237
1238 ehci_finish_transfer(q, p->packet.actual_length);
1239 usb_packet_unmap(&p->packet, &p->sgl);
1240 qemu_sglist_destroy(&p->sgl);
1241 p->async = EHCI_ASYNC_NONE;
1242
1243 q->qh.token ^= QTD_TOKEN_DTOGGLE;
1244 q->qh.token &= ~QTD_TOKEN_ACTIVE;
1245
1246 if (q->qh.token & QTD_TOKEN_IOC) {
1247 ehci_raise_irq(q->ehci, USBSTS_INT);
1248 if (q->async) {
1249 q->ehci->int_req_by_async = true;
1250 }
1251 }
1252 }
1253
1254 /* 4.10.3 returns "again" */
1255 static int ehci_execute(EHCIPacket *p, const char *action)
1256 {
1257 USBEndpoint *ep;
1258 int endp;
1259 bool spd;
1260
1261 assert(p->async == EHCI_ASYNC_NONE ||
1262 p->async == EHCI_ASYNC_INITIALIZED);
1263
1264 if (!(p->qtd.token & QTD_TOKEN_ACTIVE)) {
1265 fprintf(stderr, "Attempting to execute inactive qtd\n");
1266 return -1;
1267 }
1268
1269 if (get_field(p->qtd.token, QTD_TOKEN_TBYTES) > BUFF_SIZE) {
1270 ehci_trace_guest_bug(p->queue->ehci,
1271 "guest requested more bytes than allowed");
1272 return -1;
1273 }
1274
1275 p->pid = (p->qtd.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
1276 switch (p->pid) {
1277 case 0:
1278 p->pid = USB_TOKEN_OUT;
1279 break;
1280 case 1:
1281 p->pid = USB_TOKEN_IN;
1282 break;
1283 case 2:
1284 p->pid = USB_TOKEN_SETUP;
1285 break;
1286 default:
1287 fprintf(stderr, "bad token\n");
1288 break;
1289 }
1290
1291 endp = get_field(p->queue->qh.epchar, QH_EPCHAR_EP);
1292 ep = usb_ep_get(p->queue->dev, p->pid, endp);
1293
1294 if (p->async == EHCI_ASYNC_NONE) {
1295 if (ehci_init_transfer(p) != 0) {
1296 return -1;
1297 }
1298
1299 spd = (p->pid == USB_TOKEN_IN && NLPTR_TBIT(p->qtd.altnext) == 0);
1300 usb_packet_setup(&p->packet, p->pid, ep, p->qtdaddr, spd,
1301 (p->qtd.token & QTD_TOKEN_IOC) != 0);
1302 usb_packet_map(&p->packet, &p->sgl);
1303 p->async = EHCI_ASYNC_INITIALIZED;
1304 }
1305
1306 trace_usb_ehci_packet_action(p->queue, p, action);
1307 usb_handle_packet(p->queue->dev, &p->packet);
1308 DPRINTF("submit: qh 0x%x next 0x%x qtd 0x%x pid 0x%x len %zd endp 0x%x "
1309 "status %d actual_length %d\n", p->queue->qhaddr, p->qtd.next,
1310 p->qtdaddr, p->pid, p->packet.iov.size, endp, p->packet.status,
1311 p->packet.actual_length);
1312
1313 if (p->packet.actual_length > BUFF_SIZE) {
1314 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1315 return -1;
1316 }
1317
1318 return 1;
1319 }
1320
1321 /* 4.7.2
1322 */
1323
1324 static int ehci_process_itd(EHCIState *ehci,
1325 EHCIitd *itd,
1326 uint32_t addr)
1327 {
1328 USBDevice *dev;
1329 USBEndpoint *ep;
1330 uint32_t i, len, pid, dir, devaddr, endp;
1331 uint32_t pg, off, ptr1, ptr2, max, mult;
1332
1333 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1334 devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1335 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1336 max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1337 mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);
1338
1339 for(i = 0; i < 8; i++) {
1340 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1341 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1342 off = itd->transact[i] & ITD_XACT_OFFSET_MASK;
1343 ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK);
1344 ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK);
1345 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1346
1347 if (len > max * mult) {
1348 len = max * mult;
1349 }
1350
1351 if (len > BUFF_SIZE) {
1352 return -1;
1353 }
1354
1355 qemu_sglist_init(&ehci->isgl, 2, ehci->dma);
1356 if (off + len > 4096) {
1357 /* transfer crosses page border */
1358 uint32_t len2 = off + len - 4096;
1359 uint32_t len1 = len - len2;
1360 qemu_sglist_add(&ehci->isgl, ptr1 + off, len1);
1361 qemu_sglist_add(&ehci->isgl, ptr2, len2);
1362 } else {
1363 qemu_sglist_add(&ehci->isgl, ptr1 + off, len);
1364 }
1365
1366 pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT;
1367
1368 dev = ehci_find_device(ehci, devaddr);
1369 ep = usb_ep_get(dev, pid, endp);
1370 if (ep && ep->type == USB_ENDPOINT_XFER_ISOC) {
1371 usb_packet_setup(&ehci->ipacket, pid, ep, addr, false,
1372 (itd->transact[i] & ITD_XACT_IOC) != 0);
1373 usb_packet_map(&ehci->ipacket, &ehci->isgl);
1374 usb_handle_packet(dev, &ehci->ipacket);
1375 usb_packet_unmap(&ehci->ipacket, &ehci->isgl);
1376 } else {
1377 DPRINTF("ISOCH: attempt to addess non-iso endpoint\n");
1378 ehci->ipacket.status = USB_RET_NAK;
1379 ehci->ipacket.actual_length = 0;
1380 }
1381 qemu_sglist_destroy(&ehci->isgl);
1382
1383 switch (ehci->ipacket.status) {
1384 case USB_RET_SUCCESS:
1385 break;
1386 default:
1387 fprintf(stderr, "Unexpected iso usb result: %d\n",
1388 ehci->ipacket.status);
1389 /* Fall through */
1390 case USB_RET_IOERROR:
1391 case USB_RET_NODEV:
1392 /* 3.3.2: XACTERR is only allowed on IN transactions */
1393 if (dir) {
1394 itd->transact[i] |= ITD_XACT_XACTERR;
1395 ehci_raise_irq(ehci, USBSTS_ERRINT);
1396 }
1397 break;
1398 case USB_RET_BABBLE:
1399 itd->transact[i] |= ITD_XACT_BABBLE;
1400 ehci_raise_irq(ehci, USBSTS_ERRINT);
1401 break;
1402 case USB_RET_NAK:
1403 /* no data for us, so do a zero-length transfer */
1404 ehci->ipacket.actual_length = 0;
1405 break;
1406 }
1407 if (!dir) {
1408 set_field(&itd->transact[i], len - ehci->ipacket.actual_length,
1409 ITD_XACT_LENGTH); /* OUT */
1410 } else {
1411 set_field(&itd->transact[i], ehci->ipacket.actual_length,
1412 ITD_XACT_LENGTH); /* IN */
1413 }
1414 if (itd->transact[i] & ITD_XACT_IOC) {
1415 ehci_raise_irq(ehci, USBSTS_INT);
1416 }
1417 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1418 }
1419 }
1420 return 0;
1421 }
1422
1423
1424 /* This state is the entry point for asynchronous schedule
1425 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1426 */
1427 static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1428 {
1429 EHCIqh qh;
1430 int i = 0;
1431 int again = 0;
1432 uint32_t entry = ehci->asynclistaddr;
1433
1434 /* set reclamation flag at start event (4.8.6) */
1435 if (async) {
1436 ehci_set_usbsts(ehci, USBSTS_REC);
1437 }
1438
1439 ehci_queues_rip_unused(ehci, async);
1440
1441 /* Find the head of the list (4.9.1.1) */
1442 for(i = 0; i < MAX_QH; i++) {
1443 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh,
1444 sizeof(EHCIqh) >> 2);
1445 ehci_trace_qh(NULL, NLPTR_GET(entry), &qh);
1446
1447 if (qh.epchar & QH_EPCHAR_H) {
1448 if (async) {
1449 entry |= (NLPTR_TYPE_QH << 1);
1450 }
1451
1452 ehci_set_fetch_addr(ehci, async, entry);
1453 ehci_set_state(ehci, async, EST_FETCHENTRY);
1454 again = 1;
1455 goto out;
1456 }
1457
1458 entry = qh.next;
1459 if (entry == ehci->asynclistaddr) {
1460 break;
1461 }
1462 }
1463
1464 /* no head found for list. */
1465
1466 ehci_set_state(ehci, async, EST_ACTIVE);
1467
1468 out:
1469 return again;
1470 }
1471
1472
1473 /* This state is the entry point for periodic schedule processing as
1474 * well as being a continuation state for async processing.
1475 */
1476 static int ehci_state_fetchentry(EHCIState *ehci, int async)
1477 {
1478 int again = 0;
1479 uint32_t entry = ehci_get_fetch_addr(ehci, async);
1480
1481 if (NLPTR_TBIT(entry)) {
1482 ehci_set_state(ehci, async, EST_ACTIVE);
1483 goto out;
1484 }
1485
1486 /* section 4.8, only QH in async schedule */
1487 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1488 fprintf(stderr, "non queue head request in async schedule\n");
1489 return -1;
1490 }
1491
1492 switch (NLPTR_TYPE_GET(entry)) {
1493 case NLPTR_TYPE_QH:
1494 ehci_set_state(ehci, async, EST_FETCHQH);
1495 again = 1;
1496 break;
1497
1498 case NLPTR_TYPE_ITD:
1499 ehci_set_state(ehci, async, EST_FETCHITD);
1500 again = 1;
1501 break;
1502
1503 case NLPTR_TYPE_STITD:
1504 ehci_set_state(ehci, async, EST_FETCHSITD);
1505 again = 1;
1506 break;
1507
1508 default:
1509 /* TODO: handle FSTN type */
1510 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1511 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1512 return -1;
1513 }
1514
1515 out:
1516 return again;
1517 }
1518
1519 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)
1520 {
1521 EHCIPacket *p;
1522 uint32_t entry, devaddr, endp;
1523 EHCIQueue *q;
1524 EHCIqh qh;
1525
1526 entry = ehci_get_fetch_addr(ehci, async);
1527 q = ehci_find_queue_by_qh(ehci, entry, async);
1528 if (NULL == q) {
1529 q = ehci_alloc_queue(ehci, entry, async);
1530 }
1531 p = QTAILQ_FIRST(&q->packets);
1532
1533 q->seen++;
1534 if (q->seen > 1) {
1535 /* we are going in circles -- stop processing */
1536 ehci_set_state(ehci, async, EST_ACTIVE);
1537 q = NULL;
1538 goto out;
1539 }
1540
1541 get_dwords(ehci, NLPTR_GET(q->qhaddr),
1542 (uint32_t *) &qh, sizeof(EHCIqh) >> 2);
1543 ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &qh);
1544
1545 /*
1546 * The overlay area of the qh should never be changed by the guest,
1547 * except when idle, in which case the reset is a nop.
1548 */
1549 devaddr = get_field(qh.epchar, QH_EPCHAR_DEVADDR);
1550 endp = get_field(qh.epchar, QH_EPCHAR_EP);
1551 if ((devaddr != get_field(q->qh.epchar, QH_EPCHAR_DEVADDR)) ||
1552 (endp != get_field(q->qh.epchar, QH_EPCHAR_EP)) ||
1553 (memcmp(&qh.current_qtd, &q->qh.current_qtd,
1554 9 * sizeof(uint32_t)) != 0) ||
1555 (q->dev != NULL && q->dev->addr != devaddr)) {
1556 if (ehci_reset_queue(q) > 0) {
1557 ehci_trace_guest_bug(ehci, "guest updated active QH");
1558 }
1559 p = NULL;
1560 }
1561 q->qh = qh;
1562
1563 q->transact_ctr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1564 if (q->transact_ctr == 0) { /* Guest bug in some versions of windows */
1565 q->transact_ctr = 4;
1566 }
1567
1568 if (q->dev == NULL) {
1569 q->dev = ehci_find_device(q->ehci, devaddr);
1570 }
1571
1572 if (p && p->async == EHCI_ASYNC_FINISHED) {
1573 /* I/O finished -- continue processing queue */
1574 trace_usb_ehci_packet_action(p->queue, p, "complete");
1575 ehci_set_state(ehci, async, EST_EXECUTING);
1576 goto out;
1577 }
1578
1579 if (async && (q->qh.epchar & QH_EPCHAR_H)) {
1580
1581 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1582 if (ehci->usbsts & USBSTS_REC) {
1583 ehci_clear_usbsts(ehci, USBSTS_REC);
1584 } else {
1585 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1586 " - done processing\n", q->qhaddr);
1587 ehci_set_state(ehci, async, EST_ACTIVE);
1588 q = NULL;
1589 goto out;
1590 }
1591 }
1592
1593 #if EHCI_DEBUG
1594 if (q->qhaddr != q->qh.next) {
1595 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1596 q->qhaddr,
1597 q->qh.epchar & QH_EPCHAR_H,
1598 q->qh.token & QTD_TOKEN_HALT,
1599 q->qh.token & QTD_TOKEN_ACTIVE,
1600 q->qh.next);
1601 }
1602 #endif
1603
1604 if (q->qh.token & QTD_TOKEN_HALT) {
1605 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1606
1607 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) &&
1608 (NLPTR_TBIT(q->qh.current_qtd) == 0)) {
1609 q->qtdaddr = q->qh.current_qtd;
1610 ehci_set_state(ehci, async, EST_FETCHQTD);
1611
1612 } else {
1613 /* EHCI spec version 1.0 Section 4.10.2 */
1614 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1615 }
1616
1617 out:
1618 return q;
1619 }
1620
1621 static int ehci_state_fetchitd(EHCIState *ehci, int async)
1622 {
1623 uint32_t entry;
1624 EHCIitd itd;
1625
1626 assert(!async);
1627 entry = ehci_get_fetch_addr(ehci, async);
1628
1629 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1630 sizeof(EHCIitd) >> 2);
1631 ehci_trace_itd(ehci, entry, &itd);
1632
1633 if (ehci_process_itd(ehci, &itd, entry) != 0) {
1634 return -1;
1635 }
1636
1637 put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1638 sizeof(EHCIitd) >> 2);
1639 ehci_set_fetch_addr(ehci, async, itd.next);
1640 ehci_set_state(ehci, async, EST_FETCHENTRY);
1641
1642 return 1;
1643 }
1644
1645 static int ehci_state_fetchsitd(EHCIState *ehci, int async)
1646 {
1647 uint32_t entry;
1648 EHCIsitd sitd;
1649
1650 assert(!async);
1651 entry = ehci_get_fetch_addr(ehci, async);
1652
1653 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd,
1654 sizeof(EHCIsitd) >> 2);
1655 ehci_trace_sitd(ehci, entry, &sitd);
1656
1657 if (!(sitd.results & SITD_RESULTS_ACTIVE)) {
1658 /* siTD is not active, nothing to do */;
1659 } else {
1660 /* TODO: split transfers are not implemented */
1661 fprintf(stderr, "WARNING: Skipping active siTD\n");
1662 }
1663
1664 ehci_set_fetch_addr(ehci, async, sitd.next);
1665 ehci_set_state(ehci, async, EST_FETCHENTRY);
1666 return 1;
1667 }
1668
1669 /* Section 4.10.2 - paragraph 3 */
1670 static int ehci_state_advqueue(EHCIQueue *q)
1671 {
1672 #if 0
1673 /* TO-DO: 4.10.2 - paragraph 2
1674 * if I-bit is set to 1 and QH is not active
1675 * go to horizontal QH
1676 */
1677 if (I-bit set) {
1678 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1679 goto out;
1680 }
1681 #endif
1682
1683 /*
1684 * want data and alt-next qTD is valid
1685 */
1686 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1687 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
1688 q->qtdaddr = q->qh.altnext_qtd;
1689 ehci_set_state(q->ehci, q->async, EST_FETCHQTD);
1690
1691 /*
1692 * next qTD is valid
1693 */
1694 } else if (NLPTR_TBIT(q->qh.next_qtd) == 0) {
1695 q->qtdaddr = q->qh.next_qtd;
1696 ehci_set_state(q->ehci, q->async, EST_FETCHQTD);
1697
1698 /*
1699 * no valid qTD, try next QH
1700 */
1701 } else {
1702 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1703 }
1704
1705 return 1;
1706 }
1707
1708 /* Section 4.10.2 - paragraph 4 */
1709 static int ehci_state_fetchqtd(EHCIQueue *q)
1710 {
1711 EHCIqtd qtd;
1712 EHCIPacket *p;
1713 int again = 1;
1714
1715 get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &qtd,
1716 sizeof(EHCIqtd) >> 2);
1717 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &qtd);
1718
1719 p = QTAILQ_FIRST(&q->packets);
1720 if (p != NULL) {
1721 if (p->qtdaddr != q->qtdaddr ||
1722 (!NLPTR_TBIT(p->qtd.next) && (p->qtd.next != qtd.next)) ||
1723 (!NLPTR_TBIT(p->qtd.altnext) && (p->qtd.altnext != qtd.altnext)) ||
1724 p->qtd.bufptr[0] != qtd.bufptr[0]) {
1725 ehci_cancel_queue(q);
1726 ehci_trace_guest_bug(q->ehci, "guest updated active QH or qTD");
1727 p = NULL;
1728 } else {
1729 p->qtd = qtd;
1730 ehci_qh_do_overlay(q);
1731 }
1732 }
1733
1734 if (!(qtd.token & QTD_TOKEN_ACTIVE)) {
1735 if (p != NULL) {
1736 /* transfer canceled by guest (clear active) */
1737 ehci_cancel_queue(q);
1738 p = NULL;
1739 }
1740 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1741 } else if (p != NULL) {
1742 switch (p->async) {
1743 case EHCI_ASYNC_NONE:
1744 case EHCI_ASYNC_INITIALIZED:
1745 /* Not yet executed (MULT), or previously nacked (int) packet */
1746 ehci_set_state(q->ehci, q->async, EST_EXECUTE);
1747 break;
1748 case EHCI_ASYNC_INFLIGHT:
1749 /* Check if the guest has added new tds to the queue */
1750 again = ehci_fill_queue(QTAILQ_LAST(&q->packets, pkts_head));
1751 /* Unfinished async handled packet, go horizontal */
1752 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1753 break;
1754 case EHCI_ASYNC_FINISHED:
1755 /*
1756 * We get here when advqueue moves to a packet which is already
1757 * finished, which can happen with packets queued up by fill_queue
1758 */
1759 ehci_set_state(q->ehci, q->async, EST_EXECUTING);
1760 break;
1761 }
1762 } else {
1763 p = ehci_alloc_packet(q);
1764 p->qtdaddr = q->qtdaddr;
1765 p->qtd = qtd;
1766 ehci_set_state(q->ehci, q->async, EST_EXECUTE);
1767 }
1768
1769 return again;
1770 }
1771
1772 static int ehci_state_horizqh(EHCIQueue *q)
1773 {
1774 int again = 0;
1775
1776 if (ehci_get_fetch_addr(q->ehci, q->async) != q->qh.next) {
1777 ehci_set_fetch_addr(q->ehci, q->async, q->qh.next);
1778 ehci_set_state(q->ehci, q->async, EST_FETCHENTRY);
1779 again = 1;
1780 } else {
1781 ehci_set_state(q->ehci, q->async, EST_ACTIVE);
1782 }
1783
1784 return again;
1785 }
1786
1787 /* Returns "again" */
1788 static int ehci_fill_queue(EHCIPacket *p)
1789 {
1790 USBEndpoint *ep = p->packet.ep;
1791 EHCIQueue *q = p->queue;
1792 EHCIqtd qtd = p->qtd;
1793 uint32_t qtdaddr, start_addr = p->qtdaddr;
1794
1795 for (;;) {
1796 if (NLPTR_TBIT(qtd.next) != 0) {
1797 break;
1798 }
1799 qtdaddr = qtd.next;
1800 /*
1801 * Detect circular td lists, Windows creates these, counting on the
1802 * active bit going low after execution to make the queue stop.
1803 */
1804 if (qtdaddr == start_addr) {
1805 break;
1806 }
1807 get_dwords(q->ehci, NLPTR_GET(qtdaddr),
1808 (uint32_t *) &qtd, sizeof(EHCIqtd) >> 2);
1809 ehci_trace_qtd(q, NLPTR_GET(qtdaddr), &qtd);
1810 if (!(qtd.token & QTD_TOKEN_ACTIVE)) {
1811 break;
1812 }
1813 p = ehci_alloc_packet(q);
1814 p->qtdaddr = qtdaddr;
1815 p->qtd = qtd;
1816 if (ehci_execute(p, "queue") == -1) {
1817 return -1;
1818 }
1819 assert(p->packet.status == USB_RET_ASYNC);
1820 p->async = EHCI_ASYNC_INFLIGHT;
1821 }
1822 usb_device_flush_ep_queue(ep->dev, ep);
1823 return 1;
1824 }
1825
1826 static int ehci_state_execute(EHCIQueue *q)
1827 {
1828 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1829 int again = 0;
1830
1831 assert(p != NULL);
1832 assert(p->qtdaddr == q->qtdaddr);
1833
1834 if (ehci_qh_do_overlay(q) != 0) {
1835 return -1;
1836 }
1837
1838 // TODO verify enough time remains in the uframe as in 4.4.1.1
1839 // TODO write back ptr to async list when done or out of time
1840
1841 /* 4.10.3, bottom of page 82, go horizontal on transaction counter == 0 */
1842 if (!q->async && q->transact_ctr == 0) {
1843 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1844 again = 1;
1845 goto out;
1846 }
1847
1848 if (q->async) {
1849 ehci_set_usbsts(q->ehci, USBSTS_REC);
1850 }
1851
1852 again = ehci_execute(p, "process");
1853 if (again == -1) {
1854 goto out;
1855 }
1856 if (p->packet.status == USB_RET_ASYNC) {
1857 ehci_flush_qh(q);
1858 trace_usb_ehci_packet_action(p->queue, p, "async");
1859 p->async = EHCI_ASYNC_INFLIGHT;
1860 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1861 if (q->async) {
1862 again = ehci_fill_queue(p);
1863 } else {
1864 again = 1;
1865 }
1866 goto out;
1867 }
1868
1869 ehci_set_state(q->ehci, q->async, EST_EXECUTING);
1870 again = 1;
1871
1872 out:
1873 return again;
1874 }
1875
1876 static int ehci_state_executing(EHCIQueue *q)
1877 {
1878 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1879
1880 assert(p != NULL);
1881 assert(p->qtdaddr == q->qtdaddr);
1882
1883 ehci_execute_complete(q);
1884
1885 /* 4.10.3 */
1886 if (!q->async && q->transact_ctr > 0) {
1887 q->transact_ctr--;
1888 }
1889
1890 /* 4.10.5 */
1891 if (p->packet.status == USB_RET_NAK) {
1892 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1893 } else {
1894 ehci_set_state(q->ehci, q->async, EST_WRITEBACK);
1895 }
1896
1897 ehci_flush_qh(q);
1898 return 1;
1899 }
1900
1901
1902 static int ehci_state_writeback(EHCIQueue *q)
1903 {
1904 EHCIPacket *p = QTAILQ_FIRST(&q->packets);
1905 uint32_t *qtd, addr;
1906 int again = 0;
1907
1908 /* Write back the QTD from the QH area */
1909 assert(p != NULL);
1910 assert(p->qtdaddr == q->qtdaddr);
1911
1912 ehci_trace_qtd(q, NLPTR_GET(p->qtdaddr), (EHCIqtd *) &q->qh.next_qtd);
1913 qtd = (uint32_t *) &q->qh.next_qtd;
1914 addr = NLPTR_GET(p->qtdaddr);
1915 put_dwords(q->ehci, addr + 2 * sizeof(uint32_t), qtd + 2, 2);
1916 ehci_free_packet(p);
1917
1918 /*
1919 * EHCI specs say go horizontal here.
1920 *
1921 * We can also advance the queue here for performance reasons. We
1922 * need to take care to only take that shortcut in case we've
1923 * processed the qtd just written back without errors, i.e. halt
1924 * bit is clear.
1925 */
1926 if (q->qh.token & QTD_TOKEN_HALT) {
1927 ehci_set_state(q->ehci, q->async, EST_HORIZONTALQH);
1928 again = 1;
1929 } else {
1930 ehci_set_state(q->ehci, q->async, EST_ADVANCEQUEUE);
1931 again = 1;
1932 }
1933 return again;
1934 }
1935
1936 /*
1937 * This is the state machine that is common to both async and periodic
1938 */
1939
1940 static void ehci_advance_state(EHCIState *ehci, int async)
1941 {
1942 EHCIQueue *q = NULL;
1943 int again;
1944
1945 do {
1946 switch(ehci_get_state(ehci, async)) {
1947 case EST_WAITLISTHEAD:
1948 again = ehci_state_waitlisthead(ehci, async);
1949 break;
1950
1951 case EST_FETCHENTRY:
1952 again = ehci_state_fetchentry(ehci, async);
1953 break;
1954
1955 case EST_FETCHQH:
1956 q = ehci_state_fetchqh(ehci, async);
1957 if (q != NULL) {
1958 assert(q->async == async);
1959 again = 1;
1960 } else {
1961 again = 0;
1962 }
1963 break;
1964
1965 case EST_FETCHITD:
1966 again = ehci_state_fetchitd(ehci, async);
1967 break;
1968
1969 case EST_FETCHSITD:
1970 again = ehci_state_fetchsitd(ehci, async);
1971 break;
1972
1973 case EST_ADVANCEQUEUE:
1974 again = ehci_state_advqueue(q);
1975 break;
1976
1977 case EST_FETCHQTD:
1978 again = ehci_state_fetchqtd(q);
1979 break;
1980
1981 case EST_HORIZONTALQH:
1982 again = ehci_state_horizqh(q);
1983 break;
1984
1985 case EST_EXECUTE:
1986 again = ehci_state_execute(q);
1987 if (async) {
1988 ehci->async_stepdown = 0;
1989 }
1990 break;
1991
1992 case EST_EXECUTING:
1993 assert(q != NULL);
1994 if (async) {
1995 ehci->async_stepdown = 0;
1996 }
1997 again = ehci_state_executing(q);
1998 break;
1999
2000 case EST_WRITEBACK:
2001 assert(q != NULL);
2002 again = ehci_state_writeback(q);
2003 break;
2004
2005 default:
2006 fprintf(stderr, "Bad state!\n");
2007 again = -1;
2008 assert(0);
2009 break;
2010 }
2011
2012 if (again < 0) {
2013 fprintf(stderr, "processing error - resetting ehci HC\n");
2014 ehci_reset(ehci);
2015 again = 0;
2016 }
2017 }
2018 while (again);
2019 }
2020
2021 static void ehci_advance_async_state(EHCIState *ehci)
2022 {
2023 const int async = 1;
2024
2025 switch(ehci_get_state(ehci, async)) {
2026 case EST_INACTIVE:
2027 if (!ehci_async_enabled(ehci)) {
2028 break;
2029 }
2030 ehci_set_state(ehci, async, EST_ACTIVE);
2031 // No break, fall through to ACTIVE
2032
2033 case EST_ACTIVE:
2034 if (!ehci_async_enabled(ehci)) {
2035 ehci_queues_rip_all(ehci, async);
2036 ehci_set_state(ehci, async, EST_INACTIVE);
2037 break;
2038 }
2039
2040 /* make sure guest has acknowledged the doorbell interrupt */
2041 /* TO-DO: is this really needed? */
2042 if (ehci->usbsts & USBSTS_IAA) {
2043 DPRINTF("IAA status bit still set.\n");
2044 break;
2045 }
2046
2047 /* check that address register has been set */
2048 if (ehci->asynclistaddr == 0) {
2049 break;
2050 }
2051
2052 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
2053 ehci_advance_state(ehci, async);
2054
2055 /* If the doorbell is set, the guest wants to make a change to the
2056 * schedule. The host controller needs to release cached data.
2057 * (section 4.8.2)
2058 */
2059 if (ehci->usbcmd & USBCMD_IAAD) {
2060 /* Remove all unseen qhs from the async qhs queue */
2061 ehci_queues_rip_unseen(ehci, async);
2062 trace_usb_ehci_doorbell_ack();
2063 ehci->usbcmd &= ~USBCMD_IAAD;
2064 ehci_raise_irq(ehci, USBSTS_IAA);
2065 }
2066 break;
2067
2068 default:
2069 /* this should only be due to a developer mistake */
2070 fprintf(stderr, "ehci: Bad asynchronous state %d. "
2071 "Resetting to active\n", ehci->astate);
2072 assert(0);
2073 }
2074 }
2075
2076 static void ehci_advance_periodic_state(EHCIState *ehci)
2077 {
2078 uint32_t entry;
2079 uint32_t list;
2080 const int async = 0;
2081
2082 // 4.6
2083
2084 switch(ehci_get_state(ehci, async)) {
2085 case EST_INACTIVE:
2086 if (!(ehci->frindex & 7) && ehci_periodic_enabled(ehci)) {
2087 ehci_set_state(ehci, async, EST_ACTIVE);
2088 // No break, fall through to ACTIVE
2089 } else
2090 break;
2091
2092 case EST_ACTIVE:
2093 if (!(ehci->frindex & 7) && !ehci_periodic_enabled(ehci)) {
2094 ehci_queues_rip_all(ehci, async);
2095 ehci_set_state(ehci, async, EST_INACTIVE);
2096 break;
2097 }
2098
2099 list = ehci->periodiclistbase & 0xfffff000;
2100 /* check that register has been set */
2101 if (list == 0) {
2102 break;
2103 }
2104 list |= ((ehci->frindex & 0x1ff8) >> 1);
2105
2106 dma_memory_read(ehci->dma, list, &entry, sizeof entry);
2107 entry = le32_to_cpu(entry);
2108
2109 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2110 ehci->frindex / 8, list, entry);
2111 ehci_set_fetch_addr(ehci, async,entry);
2112 ehci_set_state(ehci, async, EST_FETCHENTRY);
2113 ehci_advance_state(ehci, async);
2114 ehci_queues_rip_unused(ehci, async);
2115 break;
2116
2117 default:
2118 /* this should only be due to a developer mistake */
2119 fprintf(stderr, "ehci: Bad periodic state %d. "
2120 "Resetting to active\n", ehci->pstate);
2121 assert(0);
2122 }
2123 }
2124
2125 static void ehci_update_frindex(EHCIState *ehci, int frames)
2126 {
2127 int i;
2128
2129 if (!ehci_enabled(ehci)) {
2130 return;
2131 }
2132
2133 for (i = 0; i < frames; i++) {
2134 ehci->frindex += 8;
2135
2136 if (ehci->frindex == 0x00002000) {
2137 ehci_raise_irq(ehci, USBSTS_FLR);
2138 }
2139
2140 if (ehci->frindex == 0x00004000) {
2141 ehci_raise_irq(ehci, USBSTS_FLR);
2142 ehci->frindex = 0;
2143 if (ehci->usbsts_frindex >= 0x00004000) {
2144 ehci->usbsts_frindex -= 0x00004000;
2145 } else {
2146 ehci->usbsts_frindex = 0;
2147 }
2148 }
2149 }
2150 }
2151
2152 static void ehci_frame_timer(void *opaque)
2153 {
2154 EHCIState *ehci = opaque;
2155 int need_timer = 0;
2156 int64_t expire_time, t_now;
2157 uint64_t ns_elapsed;
2158 int frames, skipped_frames;
2159 int i;
2160
2161 t_now = qemu_get_clock_ns(vm_clock);
2162 ns_elapsed = t_now - ehci->last_run_ns;
2163 frames = ns_elapsed / FRAME_TIMER_NS;
2164
2165 if (ehci_periodic_enabled(ehci) || ehci->pstate != EST_INACTIVE) {
2166 need_timer++;
2167 ehci->async_stepdown = 0;
2168
2169 if (frames > ehci->maxframes) {
2170 skipped_frames = frames - ehci->maxframes;
2171 ehci_update_frindex(ehci, skipped_frames);
2172 ehci->last_run_ns += FRAME_TIMER_NS * skipped_frames;
2173 frames -= skipped_frames;
2174 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
2175 }
2176
2177 for (i = 0; i < frames; i++) {
2178 /*
2179 * If we're running behind schedule, we should not catch up
2180 * too fast, as that will make some guests unhappy:
2181 * 1) We must process a minimum of MIN_FR_PER_TICK frames,
2182 * otherwise we will never catch up
2183 * 2) Process frames until the guest has requested an irq (IOC)
2184 */
2185 if (i >= MIN_FR_PER_TICK) {
2186 ehci_commit_irq(ehci);
2187 if ((ehci->usbsts & USBINTR_MASK) & ehci->usbintr) {
2188 break;
2189 }
2190 }
2191 ehci_update_frindex(ehci, 1);
2192 ehci_advance_periodic_state(ehci);
2193 ehci->last_run_ns += FRAME_TIMER_NS;
2194 }
2195 } else {
2196 if (ehci->async_stepdown < ehci->maxframes / 2) {
2197 ehci->async_stepdown++;
2198 }
2199 ehci_update_frindex(ehci, frames);
2200 ehci->last_run_ns += FRAME_TIMER_NS * frames;
2201 }
2202
2203 /* Async is not inside loop since it executes everything it can once
2204 * called
2205 */
2206 if (ehci_async_enabled(ehci) || ehci->astate != EST_INACTIVE) {
2207 need_timer++;
2208 ehci_advance_async_state(ehci);
2209 }
2210
2211 ehci_commit_irq(ehci);
2212 if (ehci->usbsts_pending) {
2213 need_timer++;
2214 ehci->async_stepdown = 0;
2215 }
2216
2217 if (need_timer) {
2218 /* If we've raised int, we speed up the timer, so that we quickly
2219 * notice any new packets queued up in response */
2220 if (ehci->int_req_by_async && (ehci->usbsts & USBSTS_INT)) {
2221 expire_time = t_now + get_ticks_per_sec() / (FRAME_TIMER_FREQ * 2);
2222 ehci->int_req_by_async = false;
2223 } else {
2224 expire_time = t_now + (get_ticks_per_sec()
2225 * (ehci->async_stepdown+1) / FRAME_TIMER_FREQ);
2226 }
2227 qemu_mod_timer(ehci->frame_timer, expire_time);
2228 }
2229 }
2230
2231 static const MemoryRegionOps ehci_mmio_caps_ops = {
2232 .read = ehci_caps_read,
2233 .valid.min_access_size = 1,
2234 .valid.max_access_size = 4,
2235 .impl.min_access_size = 1,
2236 .impl.max_access_size = 1,
2237 .endianness = DEVICE_LITTLE_ENDIAN,
2238 };
2239
2240 static const MemoryRegionOps ehci_mmio_opreg_ops = {
2241 .read = ehci_opreg_read,
2242 .write = ehci_opreg_write,
2243 .valid.min_access_size = 4,
2244 .valid.max_access_size = 4,
2245 .endianness = DEVICE_LITTLE_ENDIAN,
2246 };
2247
2248 static const MemoryRegionOps ehci_mmio_port_ops = {
2249 .read = ehci_port_read,
2250 .write = ehci_port_write,
2251 .valid.min_access_size = 4,
2252 .valid.max_access_size = 4,
2253 .endianness = DEVICE_LITTLE_ENDIAN,
2254 };
2255
2256 static USBPortOps ehci_port_ops = {
2257 .attach = ehci_attach,
2258 .detach = ehci_detach,
2259 .child_detach = ehci_child_detach,
2260 .wakeup = ehci_wakeup,
2261 .complete = ehci_async_complete_packet,
2262 };
2263
2264 static USBBusOps ehci_bus_ops = {
2265 .register_companion = ehci_register_companion,
2266 };
2267
2268 static int usb_ehci_post_load(void *opaque, int version_id)
2269 {
2270 EHCIState *s = opaque;
2271 int i;
2272
2273 for (i = 0; i < NB_PORTS; i++) {
2274 USBPort *companion = s->companion_ports[i];
2275 if (companion == NULL) {
2276 continue;
2277 }
2278 if (s->portsc[i] & PORTSC_POWNER) {
2279 companion->dev = s->ports[i].dev;
2280 } else {
2281 companion->dev = NULL;
2282 }
2283 }
2284
2285 return 0;
2286 }
2287
2288 static void usb_ehci_vm_state_change(void *opaque, int running, RunState state)
2289 {
2290 EHCIState *ehci = opaque;
2291
2292 /*
2293 * We don't migrate the EHCIQueue-s, instead we rebuild them for the
2294 * schedule in guest memory. We must do the rebuilt ASAP, so that
2295 * USB-devices which have async handled packages have a packet in the
2296 * ep queue to match the completion with.
2297 */
2298 if (state == RUN_STATE_RUNNING) {
2299 ehci_advance_async_state(ehci);
2300 }
2301
2302 /*
2303 * The schedule rebuilt from guest memory could cause the migration dest
2304 * to miss a QH unlink, and fail to cancel packets, since the unlinked QH
2305 * will never have existed on the destination. Therefor we must flush the
2306 * async schedule on savevm to catch any not yet noticed unlinks.
2307 */
2308 if (state == RUN_STATE_SAVE_VM) {
2309 ehci_advance_async_state(ehci);
2310 ehci_queues_rip_unseen(ehci, 1);
2311 }
2312 }
2313
2314 const VMStateDescription vmstate_ehci = {
2315 .name = "ehci-core",
2316 .version_id = 2,
2317 .minimum_version_id = 1,
2318 .post_load = usb_ehci_post_load,
2319 .fields = (VMStateField[]) {
2320 /* mmio registers */
2321 VMSTATE_UINT32(usbcmd, EHCIState),
2322 VMSTATE_UINT32(usbsts, EHCIState),
2323 VMSTATE_UINT32_V(usbsts_pending, EHCIState, 2),
2324 VMSTATE_UINT32_V(usbsts_frindex, EHCIState, 2),
2325 VMSTATE_UINT32(usbintr, EHCIState),
2326 VMSTATE_UINT32(frindex, EHCIState),
2327 VMSTATE_UINT32(ctrldssegment, EHCIState),
2328 VMSTATE_UINT32(periodiclistbase, EHCIState),
2329 VMSTATE_UINT32(asynclistaddr, EHCIState),
2330 VMSTATE_UINT32(configflag, EHCIState),
2331 VMSTATE_UINT32(portsc[0], EHCIState),
2332 VMSTATE_UINT32(portsc[1], EHCIState),
2333 VMSTATE_UINT32(portsc[2], EHCIState),
2334 VMSTATE_UINT32(portsc[3], EHCIState),
2335 VMSTATE_UINT32(portsc[4], EHCIState),
2336 VMSTATE_UINT32(portsc[5], EHCIState),
2337 /* frame timer */
2338 VMSTATE_TIMER(frame_timer, EHCIState),
2339 VMSTATE_UINT64(last_run_ns, EHCIState),
2340 VMSTATE_UINT32(async_stepdown, EHCIState),
2341 /* schedule state */
2342 VMSTATE_UINT32(astate, EHCIState),
2343 VMSTATE_UINT32(pstate, EHCIState),
2344 VMSTATE_UINT32(a_fetch_addr, EHCIState),
2345 VMSTATE_UINT32(p_fetch_addr, EHCIState),
2346 VMSTATE_END_OF_LIST()
2347 }
2348 };
2349
2350 void usb_ehci_initfn(EHCIState *s, DeviceState *dev)
2351 {
2352 int i;
2353
2354 /* 2.2 host controller interface version */
2355 s->caps[0x00] = (uint8_t)(s->opregbase - s->capsbase);
2356 s->caps[0x01] = 0x00;
2357 s->caps[0x02] = 0x00;
2358 s->caps[0x03] = 0x01; /* HC version */
2359 s->caps[0x04] = NB_PORTS; /* Number of downstream ports */
2360 s->caps[0x05] = 0x00; /* No companion ports at present */
2361 s->caps[0x06] = 0x00;
2362 s->caps[0x07] = 0x00;
2363 s->caps[0x08] = 0x80; /* We can cache whole frame, no 64-bit */
2364 s->caps[0x0a] = 0x00;
2365 s->caps[0x0b] = 0x00;
2366
2367 usb_bus_new(&s->bus, &ehci_bus_ops, dev);
2368 for(i = 0; i < NB_PORTS; i++) {
2369 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2370 USB_SPEED_MASK_HIGH);
2371 s->ports[i].dev = 0;
2372 }
2373
2374 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2375 s->async_bh = qemu_bh_new(ehci_frame_timer, s);
2376 QTAILQ_INIT(&s->aqueues);
2377 QTAILQ_INIT(&s->pqueues);
2378 usb_packet_init(&s->ipacket);
2379
2380 qemu_register_reset(ehci_reset, s);
2381 qemu_add_vm_change_state_handler(usb_ehci_vm_state_change, s);
2382
2383 memory_region_init(&s->mem, "ehci", MMIO_SIZE);
2384 memory_region_init_io(&s->mem_caps, &ehci_mmio_caps_ops, s,
2385 "capabilities", CAPA_SIZE);
2386 memory_region_init_io(&s->mem_opreg, &ehci_mmio_opreg_ops, s,
2387 "operational", PORTSC_BEGIN);
2388 memory_region_init_io(&s->mem_ports, &ehci_mmio_port_ops, s,
2389 "ports", PORTSC_END - PORTSC_BEGIN);
2390
2391 memory_region_add_subregion(&s->mem, s->capsbase, &s->mem_caps);
2392 memory_region_add_subregion(&s->mem, s->opregbase, &s->mem_opreg);
2393 memory_region_add_subregion(&s->mem, s->opregbase + PORTSC_BEGIN,
2394 &s->mem_ports);
2395 }
2396
2397 /*
2398 * vim: expandtab ts=4
2399 */
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