2 * USB UHCI controller emulation
4 * Copyright (c) 2005 Fabrice Bellard
6 * Copyright (c) 2008 Max Krasnyansky
7 * Magor rewrite of the UHCI data structures parser and frame processor
8 * Support for fully async operation and multiple outstanding transactions
10 * Permission is hereby granted, free of charge, to any person obtaining a copy
11 * of this software and associated documentation files (the "Software"), to deal
12 * in the Software without restriction, including without limitation the rights
13 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
14 * copies of the Software, and to permit persons to whom the Software is
15 * furnished to do so, subject to the following conditions:
17 * The above copyright notice and this permission notice shall be included in
18 * all copies or substantial portions of the Software.
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
24 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
25 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
31 #include "qemu-timer.h"
37 //#define DEBUG_DUMP_DATA
39 #define UHCI_CMD_FGR (1 << 4)
40 #define UHCI_CMD_EGSM (1 << 3)
41 #define UHCI_CMD_GRESET (1 << 2)
42 #define UHCI_CMD_HCRESET (1 << 1)
43 #define UHCI_CMD_RS (1 << 0)
45 #define UHCI_STS_HCHALTED (1 << 5)
46 #define UHCI_STS_HCPERR (1 << 4)
47 #define UHCI_STS_HSERR (1 << 3)
48 #define UHCI_STS_RD (1 << 2)
49 #define UHCI_STS_USBERR (1 << 1)
50 #define UHCI_STS_USBINT (1 << 0)
52 #define TD_CTRL_SPD (1 << 29)
53 #define TD_CTRL_ERROR_SHIFT 27
54 #define TD_CTRL_IOS (1 << 25)
55 #define TD_CTRL_IOC (1 << 24)
56 #define TD_CTRL_ACTIVE (1 << 23)
57 #define TD_CTRL_STALL (1 << 22)
58 #define TD_CTRL_BABBLE (1 << 20)
59 #define TD_CTRL_NAK (1 << 19)
60 #define TD_CTRL_TIMEOUT (1 << 18)
62 #define UHCI_PORT_SUSPEND (1 << 12)
63 #define UHCI_PORT_RESET (1 << 9)
64 #define UHCI_PORT_LSDA (1 << 8)
65 #define UHCI_PORT_RD (1 << 6)
66 #define UHCI_PORT_ENC (1 << 3)
67 #define UHCI_PORT_EN (1 << 2)
68 #define UHCI_PORT_CSC (1 << 1)
69 #define UHCI_PORT_CCS (1 << 0)
71 #define UHCI_PORT_READ_ONLY (0x1bb)
72 #define UHCI_PORT_WRITE_CLEAR (UHCI_PORT_CSC | UHCI_PORT_ENC)
74 #define FRAME_TIMER_FREQ 1000
76 #define FRAME_MAX_LOOPS 256
81 TD_RESULT_STOP_FRAME
= 10,
84 TD_RESULT_ASYNC_START
,
88 typedef struct UHCIState UHCIState
;
89 typedef struct UHCIAsync UHCIAsync
;
90 typedef struct UHCIQueue UHCIQueue
;
93 * Pending async transaction.
94 * 'packet' must be the first field because completion
95 * handler does "(UHCIAsync *) pkt" cast.
102 QTAILQ_ENTRY(UHCIAsync
) next
;
111 QTAILQ_ENTRY(UHCIQueue
) next
;
112 QTAILQ_HEAD(, UHCIAsync
) asyncs
;
116 typedef struct UHCIPort
{
124 USBBus bus
; /* Note unused when we're a companion controller */
125 uint16_t cmd
; /* cmd register */
127 uint16_t intr
; /* interrupt enable register */
128 uint16_t frnum
; /* frame number */
129 uint32_t fl_base_addr
; /* frame list base address */
131 uint8_t status2
; /* bit 0 and 1 are used to generate UHCI_STS_USBINT */
133 QEMUTimer
*frame_timer
;
135 uint32_t frame_bytes
;
136 uint32_t frame_bandwidth
;
137 UHCIPort ports
[NB_PORTS
];
139 /* Interrupts that should be raised at the end of the current frame. */
140 uint32_t pending_int_mask
;
144 QTAILQ_HEAD(, UHCIQueue
) queues
;
145 uint8_t num_ports_vmstate
;
152 typedef struct UHCI_TD
{
154 uint32_t ctrl
; /* see TD_CTRL_xxx */
159 typedef struct UHCI_QH
{
164 static inline int32_t uhci_queue_token(UHCI_TD
*td
)
166 /* covers ep, dev, pid -> identifies the endpoint */
167 return td
->token
& 0x7ffff;
170 static UHCIQueue
*uhci_queue_get(UHCIState
*s
, UHCI_TD
*td
)
172 uint32_t token
= uhci_queue_token(td
);
175 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
176 if (queue
->token
== token
) {
181 queue
= g_new0(UHCIQueue
, 1);
183 queue
->token
= token
;
184 QTAILQ_INIT(&queue
->asyncs
);
185 QTAILQ_INSERT_HEAD(&s
->queues
, queue
, next
);
186 trace_usb_uhci_queue_add(queue
->token
);
190 static void uhci_queue_free(UHCIQueue
*queue
)
192 UHCIState
*s
= queue
->uhci
;
194 trace_usb_uhci_queue_del(queue
->token
);
195 QTAILQ_REMOVE(&s
->queues
, queue
, next
);
199 static UHCIAsync
*uhci_async_alloc(UHCIQueue
*queue
, uint32_t addr
)
201 UHCIAsync
*async
= g_new0(UHCIAsync
, 1);
203 async
->queue
= queue
;
205 usb_packet_init(&async
->packet
);
206 pci_dma_sglist_init(&async
->sgl
, &queue
->uhci
->dev
, 1);
207 trace_usb_uhci_packet_add(async
->queue
->token
, async
->td
);
212 static void uhci_async_free(UHCIAsync
*async
)
214 trace_usb_uhci_packet_del(async
->queue
->token
, async
->td
);
215 usb_packet_cleanup(&async
->packet
);
216 qemu_sglist_destroy(&async
->sgl
);
220 static void uhci_async_link(UHCIAsync
*async
)
222 UHCIQueue
*queue
= async
->queue
;
223 QTAILQ_INSERT_TAIL(&queue
->asyncs
, async
, next
);
224 trace_usb_uhci_packet_link_async(async
->queue
->token
, async
->td
);
227 static void uhci_async_unlink(UHCIAsync
*async
)
229 UHCIQueue
*queue
= async
->queue
;
230 QTAILQ_REMOVE(&queue
->asyncs
, async
, next
);
231 trace_usb_uhci_packet_unlink_async(async
->queue
->token
, async
->td
);
234 static void uhci_async_cancel(UHCIAsync
*async
)
236 trace_usb_uhci_packet_cancel(async
->queue
->token
, async
->td
, async
->done
);
238 usb_cancel_packet(&async
->packet
);
239 uhci_async_free(async
);
243 * Mark all outstanding async packets as invalid.
244 * This is used for canceling them when TDs are removed by the HCD.
246 static void uhci_async_validate_begin(UHCIState
*s
)
250 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
256 * Cancel async packets that are no longer valid
258 static void uhci_async_validate_end(UHCIState
*s
)
260 UHCIQueue
*queue
, *n
;
263 QTAILQ_FOREACH_SAFE(queue
, &s
->queues
, next
, n
) {
264 if (queue
->valid
> 0) {
267 while (!QTAILQ_EMPTY(&queue
->asyncs
)) {
268 async
= QTAILQ_FIRST(&queue
->asyncs
);
269 uhci_async_unlink(async
);
270 uhci_async_cancel(async
);
272 uhci_queue_free(queue
);
276 static void uhci_async_cancel_device(UHCIState
*s
, USBDevice
*dev
)
281 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
282 QTAILQ_FOREACH_SAFE(curr
, &queue
->asyncs
, next
, n
) {
283 if (!usb_packet_is_inflight(&curr
->packet
) ||
284 curr
->packet
.ep
->dev
!= dev
) {
287 uhci_async_unlink(curr
);
288 uhci_async_cancel(curr
);
293 static void uhci_async_cancel_all(UHCIState
*s
)
295 UHCIQueue
*queue
, *nq
;
298 QTAILQ_FOREACH_SAFE(queue
, &s
->queues
, next
, nq
) {
299 QTAILQ_FOREACH_SAFE(curr
, &queue
->asyncs
, next
, n
) {
300 uhci_async_unlink(curr
);
301 uhci_async_cancel(curr
);
303 uhci_queue_free(queue
);
307 static UHCIAsync
*uhci_async_find_td(UHCIState
*s
, uint32_t addr
, UHCI_TD
*td
)
309 uint32_t token
= uhci_queue_token(td
);
313 QTAILQ_FOREACH(queue
, &s
->queues
, next
) {
314 if (queue
->token
== token
) {
322 QTAILQ_FOREACH(async
, &queue
->asyncs
, next
) {
323 if (async
->td
== addr
) {
331 static void uhci_update_irq(UHCIState
*s
)
334 if (((s
->status2
& 1) && (s
->intr
& (1 << 2))) ||
335 ((s
->status2
& 2) && (s
->intr
& (1 << 3))) ||
336 ((s
->status
& UHCI_STS_USBERR
) && (s
->intr
& (1 << 0))) ||
337 ((s
->status
& UHCI_STS_RD
) && (s
->intr
& (1 << 1))) ||
338 (s
->status
& UHCI_STS_HSERR
) ||
339 (s
->status
& UHCI_STS_HCPERR
)) {
344 qemu_set_irq(s
->dev
.irq
[s
->irq_pin
], level
);
347 static void uhci_reset(void *opaque
)
349 UHCIState
*s
= opaque
;
354 trace_usb_uhci_reset();
356 pci_conf
= s
->dev
.config
;
358 pci_conf
[0x6a] = 0x01; /* usb clock */
359 pci_conf
[0x6b] = 0x00;
367 for(i
= 0; i
< NB_PORTS
; i
++) {
370 if (port
->port
.dev
&& port
->port
.dev
->attached
) {
371 usb_port_reset(&port
->port
);
375 uhci_async_cancel_all(s
);
376 qemu_bh_cancel(s
->bh
);
380 static const VMStateDescription vmstate_uhci_port
= {
383 .minimum_version_id
= 1,
384 .minimum_version_id_old
= 1,
385 .fields
= (VMStateField
[]) {
386 VMSTATE_UINT16(ctrl
, UHCIPort
),
387 VMSTATE_END_OF_LIST()
391 static int uhci_post_load(void *opaque
, int version_id
)
393 UHCIState
*s
= opaque
;
395 if (version_id
< 2) {
396 s
->expire_time
= qemu_get_clock_ns(vm_clock
) +
397 (get_ticks_per_sec() / FRAME_TIMER_FREQ
);
402 static const VMStateDescription vmstate_uhci
= {
405 .minimum_version_id
= 1,
406 .minimum_version_id_old
= 1,
407 .post_load
= uhci_post_load
,
408 .fields
= (VMStateField
[]) {
409 VMSTATE_PCI_DEVICE(dev
, UHCIState
),
410 VMSTATE_UINT8_EQUAL(num_ports_vmstate
, UHCIState
),
411 VMSTATE_STRUCT_ARRAY(ports
, UHCIState
, NB_PORTS
, 1,
412 vmstate_uhci_port
, UHCIPort
),
413 VMSTATE_UINT16(cmd
, UHCIState
),
414 VMSTATE_UINT16(status
, UHCIState
),
415 VMSTATE_UINT16(intr
, UHCIState
),
416 VMSTATE_UINT16(frnum
, UHCIState
),
417 VMSTATE_UINT32(fl_base_addr
, UHCIState
),
418 VMSTATE_UINT8(sof_timing
, UHCIState
),
419 VMSTATE_UINT8(status2
, UHCIState
),
420 VMSTATE_TIMER(frame_timer
, UHCIState
),
421 VMSTATE_INT64_V(expire_time
, UHCIState
, 2),
422 VMSTATE_END_OF_LIST()
426 static void uhci_ioport_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
428 UHCIState
*s
= opaque
;
438 static uint32_t uhci_ioport_readb(void *opaque
, uint32_t addr
)
440 UHCIState
*s
= opaque
;
455 static void uhci_ioport_writew(void *opaque
, uint32_t addr
, uint32_t val
)
457 UHCIState
*s
= opaque
;
460 trace_usb_uhci_mmio_writew(addr
, val
);
464 if ((val
& UHCI_CMD_RS
) && !(s
->cmd
& UHCI_CMD_RS
)) {
465 /* start frame processing */
466 trace_usb_uhci_schedule_start();
467 s
->expire_time
= qemu_get_clock_ns(vm_clock
) +
468 (get_ticks_per_sec() / FRAME_TIMER_FREQ
);
469 qemu_mod_timer(s
->frame_timer
, qemu_get_clock_ns(vm_clock
));
470 s
->status
&= ~UHCI_STS_HCHALTED
;
471 } else if (!(val
& UHCI_CMD_RS
)) {
472 s
->status
|= UHCI_STS_HCHALTED
;
474 if (val
& UHCI_CMD_GRESET
) {
478 /* send reset on the USB bus */
479 for(i
= 0; i
< NB_PORTS
; i
++) {
481 usb_device_reset(port
->port
.dev
);
486 if (val
& UHCI_CMD_HCRESET
) {
494 /* XXX: the chip spec is not coherent, so we add a hidden
495 register to distinguish between IOC and SPD */
496 if (val
& UHCI_STS_USBINT
)
505 if (s
->status
& UHCI_STS_HCHALTED
)
506 s
->frnum
= val
& 0x7ff;
518 dev
= port
->port
.dev
;
519 if (dev
&& dev
->attached
) {
521 if ( (val
& UHCI_PORT_RESET
) &&
522 !(port
->ctrl
& UHCI_PORT_RESET
) ) {
523 usb_device_reset(dev
);
526 port
->ctrl
&= UHCI_PORT_READ_ONLY
;
527 port
->ctrl
|= (val
& ~UHCI_PORT_READ_ONLY
);
528 /* some bits are reset when a '1' is written to them */
529 port
->ctrl
&= ~(val
& UHCI_PORT_WRITE_CLEAR
);
535 static uint32_t uhci_ioport_readw(void *opaque
, uint32_t addr
)
537 UHCIState
*s
= opaque
;
567 val
= 0xff7f; /* disabled port */
571 trace_usb_uhci_mmio_readw(addr
, val
);
576 static void uhci_ioport_writel(void *opaque
, uint32_t addr
, uint32_t val
)
578 UHCIState
*s
= opaque
;
581 trace_usb_uhci_mmio_writel(addr
, val
);
585 s
->fl_base_addr
= val
& ~0xfff;
590 static uint32_t uhci_ioport_readl(void *opaque
, uint32_t addr
)
592 UHCIState
*s
= opaque
;
598 val
= s
->fl_base_addr
;
604 trace_usb_uhci_mmio_readl(addr
, val
);
608 /* signal resume if controller suspended */
609 static void uhci_resume (void *opaque
)
611 UHCIState
*s
= (UHCIState
*)opaque
;
616 if (s
->cmd
& UHCI_CMD_EGSM
) {
617 s
->cmd
|= UHCI_CMD_FGR
;
618 s
->status
|= UHCI_STS_RD
;
623 static void uhci_attach(USBPort
*port1
)
625 UHCIState
*s
= port1
->opaque
;
626 UHCIPort
*port
= &s
->ports
[port1
->index
];
628 /* set connect status */
629 port
->ctrl
|= UHCI_PORT_CCS
| UHCI_PORT_CSC
;
632 if (port
->port
.dev
->speed
== USB_SPEED_LOW
) {
633 port
->ctrl
|= UHCI_PORT_LSDA
;
635 port
->ctrl
&= ~UHCI_PORT_LSDA
;
641 static void uhci_detach(USBPort
*port1
)
643 UHCIState
*s
= port1
->opaque
;
644 UHCIPort
*port
= &s
->ports
[port1
->index
];
646 uhci_async_cancel_device(s
, port1
->dev
);
648 /* set connect status */
649 if (port
->ctrl
& UHCI_PORT_CCS
) {
650 port
->ctrl
&= ~UHCI_PORT_CCS
;
651 port
->ctrl
|= UHCI_PORT_CSC
;
654 if (port
->ctrl
& UHCI_PORT_EN
) {
655 port
->ctrl
&= ~UHCI_PORT_EN
;
656 port
->ctrl
|= UHCI_PORT_ENC
;
662 static void uhci_child_detach(USBPort
*port1
, USBDevice
*child
)
664 UHCIState
*s
= port1
->opaque
;
666 uhci_async_cancel_device(s
, child
);
669 static void uhci_wakeup(USBPort
*port1
)
671 UHCIState
*s
= port1
->opaque
;
672 UHCIPort
*port
= &s
->ports
[port1
->index
];
674 if (port
->ctrl
& UHCI_PORT_SUSPEND
&& !(port
->ctrl
& UHCI_PORT_RD
)) {
675 port
->ctrl
|= UHCI_PORT_RD
;
680 static USBDevice
*uhci_find_device(UHCIState
*s
, uint8_t addr
)
685 for (i
= 0; i
< NB_PORTS
; i
++) {
686 UHCIPort
*port
= &s
->ports
[i
];
687 if (!(port
->ctrl
& UHCI_PORT_EN
)) {
690 dev
= usb_find_device(&port
->port
, addr
);
698 static void uhci_async_complete(USBPort
*port
, USBPacket
*packet
);
699 static void uhci_process_frame(UHCIState
*s
);
701 /* return -1 if fatal error (frame must be stopped)
703 1 if TD unsuccessful or inactive
705 static int uhci_complete_td(UHCIState
*s
, UHCI_TD
*td
, UHCIAsync
*async
, uint32_t *int_mask
)
707 int len
= 0, max_len
, err
, ret
;
710 max_len
= ((td
->token
>> 21) + 1) & 0x7ff;
711 pid
= td
->token
& 0xff;
713 ret
= async
->packet
.result
;
715 if (td
->ctrl
& TD_CTRL_IOS
)
716 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
721 len
= async
->packet
.result
;
722 td
->ctrl
= (td
->ctrl
& ~0x7ff) | ((len
- 1) & 0x7ff);
724 /* The NAK bit may have been set by a previous frame, so clear it
725 here. The docs are somewhat unclear, but win2k relies on this
727 td
->ctrl
&= ~(TD_CTRL_ACTIVE
| TD_CTRL_NAK
);
728 if (td
->ctrl
& TD_CTRL_IOC
)
731 if (pid
== USB_TOKEN_IN
) {
733 ret
= USB_RET_BABBLE
;
737 if ((td
->ctrl
& TD_CTRL_SPD
) && len
< max_len
) {
739 /* short packet: do not update QH */
740 trace_usb_uhci_packet_complete_shortxfer(async
->queue
->token
,
742 return TD_RESULT_NEXT_QH
;
747 trace_usb_uhci_packet_complete_success(async
->queue
->token
, async
->td
);
748 return TD_RESULT_COMPLETE
;
753 td
->ctrl
|= TD_CTRL_STALL
;
754 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
755 s
->status
|= UHCI_STS_USBERR
;
756 if (td
->ctrl
& TD_CTRL_IOC
) {
760 trace_usb_uhci_packet_complete_stall(async
->queue
->token
, async
->td
);
761 return TD_RESULT_NEXT_QH
;
764 td
->ctrl
|= TD_CTRL_BABBLE
| TD_CTRL_STALL
;
765 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
766 s
->status
|= UHCI_STS_USBERR
;
767 if (td
->ctrl
& TD_CTRL_IOC
) {
771 /* frame interrupted */
772 trace_usb_uhci_packet_complete_babble(async
->queue
->token
, async
->td
);
773 return TD_RESULT_STOP_FRAME
;
776 td
->ctrl
|= TD_CTRL_NAK
;
777 if (pid
== USB_TOKEN_SETUP
)
779 return TD_RESULT_NEXT_QH
;
781 case USB_RET_IOERROR
:
787 /* Retry the TD if error count is not zero */
789 td
->ctrl
|= TD_CTRL_TIMEOUT
;
790 err
= (td
->ctrl
>> TD_CTRL_ERROR_SHIFT
) & 3;
794 td
->ctrl
&= ~TD_CTRL_ACTIVE
;
795 s
->status
|= UHCI_STS_USBERR
;
796 if (td
->ctrl
& TD_CTRL_IOC
)
799 trace_usb_uhci_packet_complete_error(async
->queue
->token
,
803 td
->ctrl
= (td
->ctrl
& ~(3 << TD_CTRL_ERROR_SHIFT
)) |
804 (err
<< TD_CTRL_ERROR_SHIFT
);
805 return TD_RESULT_NEXT_QH
;
808 static int uhci_handle_td(UHCIState
*s
, uint32_t addr
, UHCI_TD
*td
,
809 uint32_t *int_mask
, bool queuing
)
812 int len
= 0, max_len
;
818 if (!(td
->ctrl
& TD_CTRL_ACTIVE
))
819 return TD_RESULT_NEXT_QH
;
821 async
= uhci_async_find_td(s
, addr
, td
);
823 /* Already submitted */
824 async
->queue
->valid
= 32;
827 return TD_RESULT_ASYNC_CONT
;
829 /* we are busy filling the queue, we are not prepared
830 to consume completed packages then, just leave them
832 return TD_RESULT_ASYNC_CONT
;
835 uhci_async_unlink(async
);
839 /* Allocate new packet */
840 async
= uhci_async_alloc(uhci_queue_get(s
, td
), addr
);
842 /* valid needs to be large enough to handle 10 frame delay
843 * for initial isochronous requests
845 async
->queue
->valid
= 32;
846 async
->isoc
= td
->ctrl
& TD_CTRL_IOS
;
848 max_len
= ((td
->token
>> 21) + 1) & 0x7ff;
849 pid
= td
->token
& 0xff;
851 dev
= uhci_find_device(s
, (td
->token
>> 8) & 0x7f);
852 ep
= usb_ep_get(dev
, pid
, (td
->token
>> 15) & 0xf);
853 usb_packet_setup(&async
->packet
, pid
, ep
);
854 qemu_sglist_add(&async
->sgl
, td
->buffer
, max_len
);
855 usb_packet_map(&async
->packet
, &async
->sgl
);
859 case USB_TOKEN_SETUP
:
860 len
= usb_handle_packet(dev
, &async
->packet
);
866 len
= usb_handle_packet(dev
, &async
->packet
);
870 /* invalid pid : frame interrupted */
871 uhci_async_free(async
);
872 s
->status
|= UHCI_STS_HCPERR
;
874 return TD_RESULT_STOP_FRAME
;
877 if (len
== USB_RET_ASYNC
) {
878 uhci_async_link(async
);
879 return TD_RESULT_ASYNC_START
;
882 async
->packet
.result
= len
;
885 len
= uhci_complete_td(s
, td
, async
, int_mask
);
886 usb_packet_unmap(&async
->packet
, &async
->sgl
);
887 uhci_async_free(async
);
891 static void uhci_async_complete(USBPort
*port
, USBPacket
*packet
)
893 UHCIAsync
*async
= container_of(packet
, UHCIAsync
, packet
);
894 UHCIState
*s
= async
->queue
->uhci
;
898 uint32_t link
= async
->td
;
899 uint32_t int_mask
= 0, val
;
901 pci_dma_read(&s
->dev
, link
& ~0xf, &td
, sizeof(td
));
902 le32_to_cpus(&td
.link
);
903 le32_to_cpus(&td
.ctrl
);
904 le32_to_cpus(&td
.token
);
905 le32_to_cpus(&td
.buffer
);
907 uhci_async_unlink(async
);
908 uhci_complete_td(s
, &td
, async
, &int_mask
);
909 s
->pending_int_mask
|= int_mask
;
911 /* update the status bits of the TD */
912 val
= cpu_to_le32(td
.ctrl
);
913 pci_dma_write(&s
->dev
, (link
& ~0xf) + 4, &val
, sizeof(val
));
914 uhci_async_free(async
);
917 if (s
->frame_bytes
< s
->frame_bandwidth
) {
918 qemu_bh_schedule(s
->bh
);
923 static int is_valid(uint32_t link
)
925 return (link
& 1) == 0;
928 static int is_qh(uint32_t link
)
930 return (link
& 2) != 0;
933 static int depth_first(uint32_t link
)
935 return (link
& 4) != 0;
938 /* QH DB used for detecting QH loops */
939 #define UHCI_MAX_QUEUES 128
941 uint32_t addr
[UHCI_MAX_QUEUES
];
945 static void qhdb_reset(QhDb
*db
)
950 /* Add QH to DB. Returns 1 if already present or DB is full. */
951 static int qhdb_insert(QhDb
*db
, uint32_t addr
)
954 for (i
= 0; i
< db
->count
; i
++)
955 if (db
->addr
[i
] == addr
)
958 if (db
->count
>= UHCI_MAX_QUEUES
)
961 db
->addr
[db
->count
++] = addr
;
965 static void uhci_fill_queue(UHCIState
*s
, UHCI_TD
*td
)
967 uint32_t int_mask
= 0;
968 uint32_t plink
= td
->link
;
969 uint32_t token
= uhci_queue_token(td
);
973 while (is_valid(plink
)) {
974 pci_dma_read(&s
->dev
, plink
& ~0xf, &ptd
, sizeof(ptd
));
975 le32_to_cpus(&ptd
.link
);
976 le32_to_cpus(&ptd
.ctrl
);
977 le32_to_cpus(&ptd
.token
);
978 le32_to_cpus(&ptd
.buffer
);
979 if (!(ptd
.ctrl
& TD_CTRL_ACTIVE
)) {
982 if (uhci_queue_token(&ptd
) != token
) {
985 trace_usb_uhci_td_queue(plink
& ~0xf, ptd
.ctrl
, ptd
.token
);
986 ret
= uhci_handle_td(s
, plink
, &ptd
, &int_mask
, true);
987 if (ret
== TD_RESULT_ASYNC_CONT
) {
990 assert(ret
== TD_RESULT_ASYNC_START
);
991 assert(int_mask
== 0);
996 static void uhci_process_frame(UHCIState
*s
)
998 uint32_t frame_addr
, link
, old_td_ctrl
, val
, int_mask
;
999 uint32_t curr_qh
, td_count
= 0;
1005 frame_addr
= s
->fl_base_addr
+ ((s
->frnum
& 0x3ff) << 2);
1007 pci_dma_read(&s
->dev
, frame_addr
, &link
, 4);
1008 le32_to_cpus(&link
);
1015 for (cnt
= FRAME_MAX_LOOPS
; is_valid(link
) && cnt
; cnt
--) {
1016 if (s
->frame_bytes
>= s
->frame_bandwidth
) {
1017 /* We've reached the usb 1.1 bandwidth, which is
1018 1280 bytes/frame, stop processing */
1019 trace_usb_uhci_frame_stop_bandwidth();
1024 trace_usb_uhci_qh_load(link
& ~0xf);
1026 if (qhdb_insert(&qhdb
, link
)) {
1028 * We're going in circles. Which is not a bug because
1029 * HCD is allowed to do that as part of the BW management.
1031 * Stop processing here if no transaction has been done
1032 * since we've been here last time.
1034 if (td_count
== 0) {
1035 trace_usb_uhci_frame_loop_stop_idle();
1038 trace_usb_uhci_frame_loop_continue();
1041 qhdb_insert(&qhdb
, link
);
1045 pci_dma_read(&s
->dev
, link
& ~0xf, &qh
, sizeof(qh
));
1046 le32_to_cpus(&qh
.link
);
1047 le32_to_cpus(&qh
.el_link
);
1049 if (!is_valid(qh
.el_link
)) {
1050 /* QH w/o elements */
1054 /* QH with elements */
1062 pci_dma_read(&s
->dev
, link
& ~0xf, &td
, sizeof(td
));
1063 le32_to_cpus(&td
.link
);
1064 le32_to_cpus(&td
.ctrl
);
1065 le32_to_cpus(&td
.token
);
1066 le32_to_cpus(&td
.buffer
);
1067 trace_usb_uhci_td_load(curr_qh
& ~0xf, link
& ~0xf, td
.ctrl
, td
.token
);
1069 old_td_ctrl
= td
.ctrl
;
1070 ret
= uhci_handle_td(s
, link
, &td
, &int_mask
, false);
1071 if (old_td_ctrl
!= td
.ctrl
) {
1072 /* update the status bits of the TD */
1073 val
= cpu_to_le32(td
.ctrl
);
1074 pci_dma_write(&s
->dev
, (link
& ~0xf) + 4, &val
, sizeof(val
));
1078 case TD_RESULT_STOP_FRAME
: /* interrupted frame */
1081 case TD_RESULT_NEXT_QH
:
1082 case TD_RESULT_ASYNC_CONT
:
1083 trace_usb_uhci_td_nextqh(curr_qh
& ~0xf, link
& ~0xf);
1084 link
= curr_qh
? qh
.link
: td
.link
;
1087 case TD_RESULT_ASYNC_START
:
1088 trace_usb_uhci_td_async(curr_qh
& ~0xf, link
& ~0xf);
1089 if (is_valid(td
.link
)) {
1090 uhci_fill_queue(s
, &td
);
1092 link
= curr_qh
? qh
.link
: td
.link
;
1095 case TD_RESULT_COMPLETE
:
1096 trace_usb_uhci_td_complete(curr_qh
& ~0xf, link
& ~0xf);
1099 s
->frame_bytes
+= (td
.ctrl
& 0x7ff) + 1;
1102 /* update QH element link */
1104 val
= cpu_to_le32(qh
.el_link
);
1105 pci_dma_write(&s
->dev
, (curr_qh
& ~0xf) + 4, &val
, sizeof(val
));
1107 if (!depth_first(link
)) {
1108 /* done with this QH */
1116 assert(!"unknown return code");
1119 /* go to the next entry */
1123 s
->pending_int_mask
|= int_mask
;
1126 static void uhci_bh(void *opaque
)
1128 UHCIState
*s
= opaque
;
1129 uhci_process_frame(s
);
1132 static void uhci_frame_timer(void *opaque
)
1134 UHCIState
*s
= opaque
;
1136 /* prepare the timer for the next frame */
1137 s
->expire_time
+= (get_ticks_per_sec() / FRAME_TIMER_FREQ
);
1139 qemu_bh_cancel(s
->bh
);
1141 if (!(s
->cmd
& UHCI_CMD_RS
)) {
1143 trace_usb_uhci_schedule_stop();
1144 qemu_del_timer(s
->frame_timer
);
1145 uhci_async_cancel_all(s
);
1146 /* set hchalted bit in status - UHCI11D 2.1.2 */
1147 s
->status
|= UHCI_STS_HCHALTED
;
1151 /* Complete the previous frame */
1152 if (s
->pending_int_mask
) {
1153 s
->status2
|= s
->pending_int_mask
;
1154 s
->status
|= UHCI_STS_USBINT
;
1157 s
->pending_int_mask
= 0;
1159 /* Start new frame */
1160 s
->frnum
= (s
->frnum
+ 1) & 0x7ff;
1162 trace_usb_uhci_frame_start(s
->frnum
);
1164 uhci_async_validate_begin(s
);
1166 uhci_process_frame(s
);
1168 uhci_async_validate_end(s
);
1170 qemu_mod_timer(s
->frame_timer
, s
->expire_time
);
1173 static const MemoryRegionPortio uhci_portio
[] = {
1174 { 0, 32, 2, .write
= uhci_ioport_writew
, },
1175 { 0, 32, 2, .read
= uhci_ioport_readw
, },
1176 { 0, 32, 4, .write
= uhci_ioport_writel
, },
1177 { 0, 32, 4, .read
= uhci_ioport_readl
, },
1178 { 0, 32, 1, .write
= uhci_ioport_writeb
, },
1179 { 0, 32, 1, .read
= uhci_ioport_readb
, },
1180 PORTIO_END_OF_LIST()
1183 static const MemoryRegionOps uhci_ioport_ops
= {
1184 .old_portio
= uhci_portio
,
1187 static USBPortOps uhci_port_ops
= {
1188 .attach
= uhci_attach
,
1189 .detach
= uhci_detach
,
1190 .child_detach
= uhci_child_detach
,
1191 .wakeup
= uhci_wakeup
,
1192 .complete
= uhci_async_complete
,
1195 static USBBusOps uhci_bus_ops
= {
1198 static int usb_uhci_common_initfn(PCIDevice
*dev
)
1200 PCIDeviceClass
*pc
= PCI_DEVICE_GET_CLASS(dev
);
1201 UHCIState
*s
= DO_UPCAST(UHCIState
, dev
, dev
);
1202 uint8_t *pci_conf
= s
->dev
.config
;
1205 pci_conf
[PCI_CLASS_PROG
] = 0x00;
1206 /* TODO: reset value should be 0. */
1207 pci_conf
[USB_SBRN
] = USB_RELEASE_1
; // release number
1209 switch (pc
->device_id
) {
1210 case PCI_DEVICE_ID_INTEL_82801I_UHCI1
:
1211 s
->irq_pin
= 0; /* A */
1213 case PCI_DEVICE_ID_INTEL_82801I_UHCI2
:
1214 s
->irq_pin
= 1; /* B */
1216 case PCI_DEVICE_ID_INTEL_82801I_UHCI3
:
1217 s
->irq_pin
= 2; /* C */
1220 s
->irq_pin
= 3; /* D */
1223 pci_config_set_interrupt_pin(pci_conf
, s
->irq_pin
+ 1);
1226 USBPort
*ports
[NB_PORTS
];
1227 for(i
= 0; i
< NB_PORTS
; i
++) {
1228 ports
[i
] = &s
->ports
[i
].port
;
1230 if (usb_register_companion(s
->masterbus
, ports
, NB_PORTS
,
1231 s
->firstport
, s
, &uhci_port_ops
,
1232 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
) != 0) {
1236 usb_bus_new(&s
->bus
, &uhci_bus_ops
, &s
->dev
.qdev
);
1237 for (i
= 0; i
< NB_PORTS
; i
++) {
1238 usb_register_port(&s
->bus
, &s
->ports
[i
].port
, s
, i
, &uhci_port_ops
,
1239 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
);
1242 s
->bh
= qemu_bh_new(uhci_bh
, s
);
1243 s
->frame_timer
= qemu_new_timer_ns(vm_clock
, uhci_frame_timer
, s
);
1244 s
->num_ports_vmstate
= NB_PORTS
;
1245 QTAILQ_INIT(&s
->queues
);
1247 qemu_register_reset(uhci_reset
, s
);
1249 memory_region_init_io(&s
->io_bar
, &uhci_ioport_ops
, s
, "uhci", 0x20);
1250 /* Use region 4 for consistency with real hardware. BSD guests seem
1252 pci_register_bar(&s
->dev
, 4, PCI_BASE_ADDRESS_SPACE_IO
, &s
->io_bar
);
1257 static int usb_uhci_vt82c686b_initfn(PCIDevice
*dev
)
1259 UHCIState
*s
= DO_UPCAST(UHCIState
, dev
, dev
);
1260 uint8_t *pci_conf
= s
->dev
.config
;
1262 /* USB misc control 1/2 */
1263 pci_set_long(pci_conf
+ 0x40,0x00001000);
1265 pci_set_long(pci_conf
+ 0x80,0x00020001);
1266 /* USB legacy support */
1267 pci_set_long(pci_conf
+ 0xc0,0x00002000);
1269 return usb_uhci_common_initfn(dev
);
1272 static void usb_uhci_exit(PCIDevice
*dev
)
1274 UHCIState
*s
= DO_UPCAST(UHCIState
, dev
, dev
);
1276 memory_region_destroy(&s
->io_bar
);
1279 static Property uhci_properties
[] = {
1280 DEFINE_PROP_STRING("masterbus", UHCIState
, masterbus
),
1281 DEFINE_PROP_UINT32("firstport", UHCIState
, firstport
, 0),
1282 DEFINE_PROP_UINT32("bandwidth", UHCIState
, frame_bandwidth
, 1280),
1283 DEFINE_PROP_END_OF_LIST(),
1286 static void piix3_uhci_class_init(ObjectClass
*klass
, void *data
)
1288 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1289 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1291 k
->init
= usb_uhci_common_initfn
;
1292 k
->exit
= usb_uhci_exit
;
1293 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
1294 k
->device_id
= PCI_DEVICE_ID_INTEL_82371SB_2
;
1296 k
->class_id
= PCI_CLASS_SERIAL_USB
;
1297 dc
->vmsd
= &vmstate_uhci
;
1298 dc
->props
= uhci_properties
;
1301 static TypeInfo piix3_uhci_info
= {
1302 .name
= "piix3-usb-uhci",
1303 .parent
= TYPE_PCI_DEVICE
,
1304 .instance_size
= sizeof(UHCIState
),
1305 .class_init
= piix3_uhci_class_init
,
1308 static void piix4_uhci_class_init(ObjectClass
*klass
, void *data
)
1310 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1311 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1313 k
->init
= usb_uhci_common_initfn
;
1314 k
->exit
= usb_uhci_exit
;
1315 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
1316 k
->device_id
= PCI_DEVICE_ID_INTEL_82371AB_2
;
1318 k
->class_id
= PCI_CLASS_SERIAL_USB
;
1319 dc
->vmsd
= &vmstate_uhci
;
1320 dc
->props
= uhci_properties
;
1323 static TypeInfo piix4_uhci_info
= {
1324 .name
= "piix4-usb-uhci",
1325 .parent
= TYPE_PCI_DEVICE
,
1326 .instance_size
= sizeof(UHCIState
),
1327 .class_init
= piix4_uhci_class_init
,
1330 static void vt82c686b_uhci_class_init(ObjectClass
*klass
, void *data
)
1332 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1333 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1335 k
->init
= usb_uhci_vt82c686b_initfn
;
1336 k
->exit
= usb_uhci_exit
;
1337 k
->vendor_id
= PCI_VENDOR_ID_VIA
;
1338 k
->device_id
= PCI_DEVICE_ID_VIA_UHCI
;
1340 k
->class_id
= PCI_CLASS_SERIAL_USB
;
1341 dc
->vmsd
= &vmstate_uhci
;
1342 dc
->props
= uhci_properties
;
1345 static TypeInfo vt82c686b_uhci_info
= {
1346 .name
= "vt82c686b-usb-uhci",
1347 .parent
= TYPE_PCI_DEVICE
,
1348 .instance_size
= sizeof(UHCIState
),
1349 .class_init
= vt82c686b_uhci_class_init
,
1352 static void ich9_uhci1_class_init(ObjectClass
*klass
, void *data
)
1354 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1355 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1357 k
->init
= usb_uhci_common_initfn
;
1358 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
1359 k
->device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI1
;
1361 k
->class_id
= PCI_CLASS_SERIAL_USB
;
1362 dc
->vmsd
= &vmstate_uhci
;
1363 dc
->props
= uhci_properties
;
1366 static TypeInfo ich9_uhci1_info
= {
1367 .name
= "ich9-usb-uhci1",
1368 .parent
= TYPE_PCI_DEVICE
,
1369 .instance_size
= sizeof(UHCIState
),
1370 .class_init
= ich9_uhci1_class_init
,
1373 static void ich9_uhci2_class_init(ObjectClass
*klass
, void *data
)
1375 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1376 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1378 k
->init
= usb_uhci_common_initfn
;
1379 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
1380 k
->device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI2
;
1382 k
->class_id
= PCI_CLASS_SERIAL_USB
;
1383 dc
->vmsd
= &vmstate_uhci
;
1384 dc
->props
= uhci_properties
;
1387 static TypeInfo ich9_uhci2_info
= {
1388 .name
= "ich9-usb-uhci2",
1389 .parent
= TYPE_PCI_DEVICE
,
1390 .instance_size
= sizeof(UHCIState
),
1391 .class_init
= ich9_uhci2_class_init
,
1394 static void ich9_uhci3_class_init(ObjectClass
*klass
, void *data
)
1396 DeviceClass
*dc
= DEVICE_CLASS(klass
);
1397 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
1399 k
->init
= usb_uhci_common_initfn
;
1400 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
1401 k
->device_id
= PCI_DEVICE_ID_INTEL_82801I_UHCI3
;
1403 k
->class_id
= PCI_CLASS_SERIAL_USB
;
1404 dc
->vmsd
= &vmstate_uhci
;
1405 dc
->props
= uhci_properties
;
1408 static TypeInfo ich9_uhci3_info
= {
1409 .name
= "ich9-usb-uhci3",
1410 .parent
= TYPE_PCI_DEVICE
,
1411 .instance_size
= sizeof(UHCIState
),
1412 .class_init
= ich9_uhci3_class_init
,
1415 static void uhci_register_types(void)
1417 type_register_static(&piix3_uhci_info
);
1418 type_register_static(&piix4_uhci_info
);
1419 type_register_static(&vt82c686b_uhci_info
);
1420 type_register_static(&ich9_uhci1_info
);
1421 type_register_static(&ich9_uhci2_info
);
1422 type_register_static(&ich9_uhci3_info
);
1425 type_init(uhci_register_types
)