2 * USB xHCI controller emulation
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu/timer.h"
24 #include "hw/pci/pci.h"
25 #include "hw/pci/msi.h"
26 #include "hw/pci/msix.h"
33 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
35 #define DPRINTF(...) do {} while (0)
37 #define FIXME() do { fprintf(stderr, "FIXME %s:%d\n", \
38 __func__, __LINE__); abort(); } while (0)
43 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3)
49 /* Very pessimistic, let's hope it's enough for all cases */
50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS)
51 /* Do not deliver ER Full events. NEC's driver does some things not bound
52 * to the specs when it gets them */
56 #define LEN_OPER (0x400 + 0x10 * MAXPORTS)
57 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20)
58 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
60 #define OFF_OPER LEN_CAP
61 #define OFF_RUNTIME 0x1000
62 #define OFF_DOORBELL 0x2000
63 #define OFF_MSIX_TABLE 0x3000
64 #define OFF_MSIX_PBA 0x3800
65 /* must be power of 2 */
66 #define LEN_REGS 0x4000
68 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
69 #error Increase OFF_RUNTIME
71 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
72 #error Increase OFF_DOORBELL
74 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
75 # error Increase LEN_REGS
79 #define USBCMD_RS (1<<0)
80 #define USBCMD_HCRST (1<<1)
81 #define USBCMD_INTE (1<<2)
82 #define USBCMD_HSEE (1<<3)
83 #define USBCMD_LHCRST (1<<7)
84 #define USBCMD_CSS (1<<8)
85 #define USBCMD_CRS (1<<9)
86 #define USBCMD_EWE (1<<10)
87 #define USBCMD_EU3S (1<<11)
89 #define USBSTS_HCH (1<<0)
90 #define USBSTS_HSE (1<<2)
91 #define USBSTS_EINT (1<<3)
92 #define USBSTS_PCD (1<<4)
93 #define USBSTS_SSS (1<<8)
94 #define USBSTS_RSS (1<<9)
95 #define USBSTS_SRE (1<<10)
96 #define USBSTS_CNR (1<<11)
97 #define USBSTS_HCE (1<<12)
100 #define PORTSC_CCS (1<<0)
101 #define PORTSC_PED (1<<1)
102 #define PORTSC_OCA (1<<3)
103 #define PORTSC_PR (1<<4)
104 #define PORTSC_PLS_SHIFT 5
105 #define PORTSC_PLS_MASK 0xf
106 #define PORTSC_PP (1<<9)
107 #define PORTSC_SPEED_SHIFT 10
108 #define PORTSC_SPEED_MASK 0xf
109 #define PORTSC_SPEED_FULL (1<<10)
110 #define PORTSC_SPEED_LOW (2<<10)
111 #define PORTSC_SPEED_HIGH (3<<10)
112 #define PORTSC_SPEED_SUPER (4<<10)
113 #define PORTSC_PIC_SHIFT 14
114 #define PORTSC_PIC_MASK 0x3
115 #define PORTSC_LWS (1<<16)
116 #define PORTSC_CSC (1<<17)
117 #define PORTSC_PEC (1<<18)
118 #define PORTSC_WRC (1<<19)
119 #define PORTSC_OCC (1<<20)
120 #define PORTSC_PRC (1<<21)
121 #define PORTSC_PLC (1<<22)
122 #define PORTSC_CEC (1<<23)
123 #define PORTSC_CAS (1<<24)
124 #define PORTSC_WCE (1<<25)
125 #define PORTSC_WDE (1<<26)
126 #define PORTSC_WOE (1<<27)
127 #define PORTSC_DR (1<<30)
128 #define PORTSC_WPR (1<<31)
130 #define CRCR_RCS (1<<0)
131 #define CRCR_CS (1<<1)
132 #define CRCR_CA (1<<2)
133 #define CRCR_CRR (1<<3)
135 #define IMAN_IP (1<<0)
136 #define IMAN_IE (1<<1)
138 #define ERDP_EHB (1<<3)
141 typedef struct XHCITRB
{
160 PLS_COMPILANCE_MODE
= 10,
165 typedef enum TRBType
{
178 CR_CONFIGURE_ENDPOINT
,
186 CR_SET_LATENCY_TOLERANCE
,
187 CR_GET_PORT_BANDWIDTH
,
192 ER_PORT_STATUS_CHANGE
,
193 ER_BANDWIDTH_REQUEST
,
196 ER_DEVICE_NOTIFICATION
,
198 /* vendor specific bits */
199 CR_VENDOR_VIA_CHALLENGE_RESPONSE
= 48,
200 CR_VENDOR_NEC_FIRMWARE_REVISION
= 49,
201 CR_VENDOR_NEC_CHALLENGE_RESPONSE
= 50,
204 #define CR_LINK TR_LINK
206 typedef enum TRBCCode
{
209 CC_DATA_BUFFER_ERROR
,
211 CC_USB_TRANSACTION_ERROR
,
217 CC_INVALID_STREAM_TYPE_ERROR
,
218 CC_SLOT_NOT_ENABLED_ERROR
,
219 CC_EP_NOT_ENABLED_ERROR
,
225 CC_BANDWIDTH_OVERRUN
,
226 CC_CONTEXT_STATE_ERROR
,
227 CC_NO_PING_RESPONSE_ERROR
,
228 CC_EVENT_RING_FULL_ERROR
,
229 CC_INCOMPATIBLE_DEVICE_ERROR
,
230 CC_MISSED_SERVICE_ERROR
,
231 CC_COMMAND_RING_STOPPED
,
234 CC_STOPPED_LENGTH_INVALID
,
235 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR
= 29,
236 CC_ISOCH_BUFFER_OVERRUN
= 31,
239 CC_INVALID_STREAM_ID_ERROR
,
240 CC_SECONDARY_BANDWIDTH_ERROR
,
241 CC_SPLIT_TRANSACTION_ERROR
245 #define TRB_TYPE_SHIFT 10
246 #define TRB_TYPE_MASK 0x3f
247 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
249 #define TRB_EV_ED (1<<2)
251 #define TRB_TR_ENT (1<<1)
252 #define TRB_TR_ISP (1<<2)
253 #define TRB_TR_NS (1<<3)
254 #define TRB_TR_CH (1<<4)
255 #define TRB_TR_IOC (1<<5)
256 #define TRB_TR_IDT (1<<6)
257 #define TRB_TR_TBC_SHIFT 7
258 #define TRB_TR_TBC_MASK 0x3
259 #define TRB_TR_BEI (1<<9)
260 #define TRB_TR_TLBPC_SHIFT 16
261 #define TRB_TR_TLBPC_MASK 0xf
262 #define TRB_TR_FRAMEID_SHIFT 20
263 #define TRB_TR_FRAMEID_MASK 0x7ff
264 #define TRB_TR_SIA (1<<31)
266 #define TRB_TR_DIR (1<<16)
268 #define TRB_CR_SLOTID_SHIFT 24
269 #define TRB_CR_SLOTID_MASK 0xff
270 #define TRB_CR_EPID_SHIFT 16
271 #define TRB_CR_EPID_MASK 0x1f
273 #define TRB_CR_BSR (1<<9)
274 #define TRB_CR_DC (1<<9)
276 #define TRB_LK_TC (1<<1)
278 #define TRB_INTR_SHIFT 22
279 #define TRB_INTR_MASK 0x3ff
280 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
282 #define EP_TYPE_MASK 0x7
283 #define EP_TYPE_SHIFT 3
285 #define EP_STATE_MASK 0x7
286 #define EP_DISABLED (0<<0)
287 #define EP_RUNNING (1<<0)
288 #define EP_HALTED (2<<0)
289 #define EP_STOPPED (3<<0)
290 #define EP_ERROR (4<<0)
292 #define SLOT_STATE_MASK 0x1f
293 #define SLOT_STATE_SHIFT 27
294 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
295 #define SLOT_ENABLED 0
296 #define SLOT_DEFAULT 1
297 #define SLOT_ADDRESSED 2
298 #define SLOT_CONFIGURED 3
300 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
301 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
303 typedef struct XHCIState XHCIState
;
305 #define get_field(data, field) \
306 (((data) >> field##_SHIFT) & field##_MASK)
308 #define set_field(data, newval, field) do { \
309 uint32_t val = *data; \
310 val &= ~(field##_MASK << field##_SHIFT); \
311 val |= ((newval) & field##_MASK) << field##_SHIFT; \
315 typedef enum EPType
{
326 typedef struct XHCIRing
{
332 typedef struct XHCIPort
{
342 typedef struct XHCITransfer
{
351 unsigned int iso_pkts
;
357 unsigned int trb_count
;
358 unsigned int trb_alloced
;
364 unsigned int pktsize
;
365 unsigned int cur_pkt
;
367 uint64_t mfindex_kick
;
370 typedef struct XHCIEPContext
{
376 unsigned int next_xfer
;
377 unsigned int comp_xfer
;
378 XHCITransfer transfers
[TD_QUEUE
];
382 unsigned int max_psize
;
385 /* iso xfer scheduling */
386 unsigned int interval
;
387 int64_t mfindex_last
;
388 QEMUTimer
*kick_timer
;
391 typedef struct XHCISlot
{
395 unsigned int devaddr
;
396 XHCIEPContext
* eps
[31];
399 typedef struct XHCIEvent
{
409 typedef struct XHCIInterrupter
{
414 uint32_t erstba_high
;
418 bool msix_used
, er_pcs
, er_full
;
422 unsigned int er_ep_idx
;
424 XHCIEvent ev_buffer
[EV_QUEUE
];
425 unsigned int ev_buffer_put
;
426 unsigned int ev_buffer_get
;
435 MemoryRegion mem_cap
;
436 MemoryRegion mem_oper
;
437 MemoryRegion mem_runtime
;
438 MemoryRegion mem_doorbell
;
440 unsigned int devaddr
;
449 /* Operational Registers */
456 uint32_t dcbaap_high
;
459 USBPort uports
[MAX(MAXPORTS_2
, MAXPORTS_3
)];
460 XHCIPort ports
[MAXPORTS
];
461 XHCISlot slots
[MAXSLOTS
];
464 /* Runtime Registers */
465 int64_t mfindex_start
;
466 QEMUTimer
*mfwrap_timer
;
467 XHCIInterrupter intr
[MAXINTRS
];
472 typedef struct XHCIEvRingSeg
{
480 XHCI_FLAG_USE_MSI
= 1,
484 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
,
486 static TRBCCode
xhci_disable_ep(XHCIState
*xhci
, unsigned int slotid
,
488 static void xhci_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
);
489 static void xhci_write_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
);
491 static const char *TRBType_names
[] = {
492 [TRB_RESERVED
] = "TRB_RESERVED",
493 [TR_NORMAL
] = "TR_NORMAL",
494 [TR_SETUP
] = "TR_SETUP",
495 [TR_DATA
] = "TR_DATA",
496 [TR_STATUS
] = "TR_STATUS",
497 [TR_ISOCH
] = "TR_ISOCH",
498 [TR_LINK
] = "TR_LINK",
499 [TR_EVDATA
] = "TR_EVDATA",
500 [TR_NOOP
] = "TR_NOOP",
501 [CR_ENABLE_SLOT
] = "CR_ENABLE_SLOT",
502 [CR_DISABLE_SLOT
] = "CR_DISABLE_SLOT",
503 [CR_ADDRESS_DEVICE
] = "CR_ADDRESS_DEVICE",
504 [CR_CONFIGURE_ENDPOINT
] = "CR_CONFIGURE_ENDPOINT",
505 [CR_EVALUATE_CONTEXT
] = "CR_EVALUATE_CONTEXT",
506 [CR_RESET_ENDPOINT
] = "CR_RESET_ENDPOINT",
507 [CR_STOP_ENDPOINT
] = "CR_STOP_ENDPOINT",
508 [CR_SET_TR_DEQUEUE
] = "CR_SET_TR_DEQUEUE",
509 [CR_RESET_DEVICE
] = "CR_RESET_DEVICE",
510 [CR_FORCE_EVENT
] = "CR_FORCE_EVENT",
511 [CR_NEGOTIATE_BW
] = "CR_NEGOTIATE_BW",
512 [CR_SET_LATENCY_TOLERANCE
] = "CR_SET_LATENCY_TOLERANCE",
513 [CR_GET_PORT_BANDWIDTH
] = "CR_GET_PORT_BANDWIDTH",
514 [CR_FORCE_HEADER
] = "CR_FORCE_HEADER",
515 [CR_NOOP
] = "CR_NOOP",
516 [ER_TRANSFER
] = "ER_TRANSFER",
517 [ER_COMMAND_COMPLETE
] = "ER_COMMAND_COMPLETE",
518 [ER_PORT_STATUS_CHANGE
] = "ER_PORT_STATUS_CHANGE",
519 [ER_BANDWIDTH_REQUEST
] = "ER_BANDWIDTH_REQUEST",
520 [ER_DOORBELL
] = "ER_DOORBELL",
521 [ER_HOST_CONTROLLER
] = "ER_HOST_CONTROLLER",
522 [ER_DEVICE_NOTIFICATION
] = "ER_DEVICE_NOTIFICATION",
523 [ER_MFINDEX_WRAP
] = "ER_MFINDEX_WRAP",
524 [CR_VENDOR_VIA_CHALLENGE_RESPONSE
] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
525 [CR_VENDOR_NEC_FIRMWARE_REVISION
] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
526 [CR_VENDOR_NEC_CHALLENGE_RESPONSE
] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
529 static const char *TRBCCode_names
[] = {
530 [CC_INVALID
] = "CC_INVALID",
531 [CC_SUCCESS
] = "CC_SUCCESS",
532 [CC_DATA_BUFFER_ERROR
] = "CC_DATA_BUFFER_ERROR",
533 [CC_BABBLE_DETECTED
] = "CC_BABBLE_DETECTED",
534 [CC_USB_TRANSACTION_ERROR
] = "CC_USB_TRANSACTION_ERROR",
535 [CC_TRB_ERROR
] = "CC_TRB_ERROR",
536 [CC_STALL_ERROR
] = "CC_STALL_ERROR",
537 [CC_RESOURCE_ERROR
] = "CC_RESOURCE_ERROR",
538 [CC_BANDWIDTH_ERROR
] = "CC_BANDWIDTH_ERROR",
539 [CC_NO_SLOTS_ERROR
] = "CC_NO_SLOTS_ERROR",
540 [CC_INVALID_STREAM_TYPE_ERROR
] = "CC_INVALID_STREAM_TYPE_ERROR",
541 [CC_SLOT_NOT_ENABLED_ERROR
] = "CC_SLOT_NOT_ENABLED_ERROR",
542 [CC_EP_NOT_ENABLED_ERROR
] = "CC_EP_NOT_ENABLED_ERROR",
543 [CC_SHORT_PACKET
] = "CC_SHORT_PACKET",
544 [CC_RING_UNDERRUN
] = "CC_RING_UNDERRUN",
545 [CC_RING_OVERRUN
] = "CC_RING_OVERRUN",
546 [CC_VF_ER_FULL
] = "CC_VF_ER_FULL",
547 [CC_PARAMETER_ERROR
] = "CC_PARAMETER_ERROR",
548 [CC_BANDWIDTH_OVERRUN
] = "CC_BANDWIDTH_OVERRUN",
549 [CC_CONTEXT_STATE_ERROR
] = "CC_CONTEXT_STATE_ERROR",
550 [CC_NO_PING_RESPONSE_ERROR
] = "CC_NO_PING_RESPONSE_ERROR",
551 [CC_EVENT_RING_FULL_ERROR
] = "CC_EVENT_RING_FULL_ERROR",
552 [CC_INCOMPATIBLE_DEVICE_ERROR
] = "CC_INCOMPATIBLE_DEVICE_ERROR",
553 [CC_MISSED_SERVICE_ERROR
] = "CC_MISSED_SERVICE_ERROR",
554 [CC_COMMAND_RING_STOPPED
] = "CC_COMMAND_RING_STOPPED",
555 [CC_COMMAND_ABORTED
] = "CC_COMMAND_ABORTED",
556 [CC_STOPPED
] = "CC_STOPPED",
557 [CC_STOPPED_LENGTH_INVALID
] = "CC_STOPPED_LENGTH_INVALID",
558 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR
]
559 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
560 [CC_ISOCH_BUFFER_OVERRUN
] = "CC_ISOCH_BUFFER_OVERRUN",
561 [CC_EVENT_LOST_ERROR
] = "CC_EVENT_LOST_ERROR",
562 [CC_UNDEFINED_ERROR
] = "CC_UNDEFINED_ERROR",
563 [CC_INVALID_STREAM_ID_ERROR
] = "CC_INVALID_STREAM_ID_ERROR",
564 [CC_SECONDARY_BANDWIDTH_ERROR
] = "CC_SECONDARY_BANDWIDTH_ERROR",
565 [CC_SPLIT_TRANSACTION_ERROR
] = "CC_SPLIT_TRANSACTION_ERROR",
568 static const char *lookup_name(uint32_t index
, const char **list
, uint32_t llen
)
570 if (index
>= llen
|| list
[index
] == NULL
) {
576 static const char *trb_name(XHCITRB
*trb
)
578 return lookup_name(TRB_TYPE(*trb
), TRBType_names
,
579 ARRAY_SIZE(TRBType_names
));
582 static const char *event_name(XHCIEvent
*event
)
584 return lookup_name(event
->ccode
, TRBCCode_names
,
585 ARRAY_SIZE(TRBCCode_names
));
588 static uint64_t xhci_mfindex_get(XHCIState
*xhci
)
590 int64_t now
= qemu_get_clock_ns(vm_clock
);
591 return (now
- xhci
->mfindex_start
) / 125000;
594 static void xhci_mfwrap_update(XHCIState
*xhci
)
596 const uint32_t bits
= USBCMD_RS
| USBCMD_EWE
;
597 uint32_t mfindex
, left
;
600 if ((xhci
->usbcmd
& bits
) == bits
) {
601 now
= qemu_get_clock_ns(vm_clock
);
602 mfindex
= ((now
- xhci
->mfindex_start
) / 125000) & 0x3fff;
603 left
= 0x4000 - mfindex
;
604 qemu_mod_timer(xhci
->mfwrap_timer
, now
+ left
* 125000);
606 qemu_del_timer(xhci
->mfwrap_timer
);
610 static void xhci_mfwrap_timer(void *opaque
)
612 XHCIState
*xhci
= opaque
;
613 XHCIEvent wrap
= { ER_MFINDEX_WRAP
, CC_SUCCESS
};
615 xhci_event(xhci
, &wrap
, 0);
616 xhci_mfwrap_update(xhci
);
619 static inline dma_addr_t
xhci_addr64(uint32_t low
, uint32_t high
)
621 if (sizeof(dma_addr_t
) == 4) {
624 return low
| (((dma_addr_t
)high
<< 16) << 16);
628 static inline dma_addr_t
xhci_mask64(uint64_t addr
)
630 if (sizeof(dma_addr_t
) == 4) {
631 return addr
& 0xffffffff;
637 static inline void xhci_dma_read_u32s(XHCIState
*xhci
, dma_addr_t addr
,
638 uint32_t *buf
, size_t len
)
642 assert((len
% sizeof(uint32_t)) == 0);
644 pci_dma_read(&xhci
->pci_dev
, addr
, buf
, len
);
646 for (i
= 0; i
< (len
/ sizeof(uint32_t)); i
++) {
647 buf
[i
] = le32_to_cpu(buf
[i
]);
651 static inline void xhci_dma_write_u32s(XHCIState
*xhci
, dma_addr_t addr
,
652 uint32_t *buf
, size_t len
)
655 uint32_t tmp
[len
/ sizeof(uint32_t)];
657 assert((len
% sizeof(uint32_t)) == 0);
659 for (i
= 0; i
< (len
/ sizeof(uint32_t)); i
++) {
660 tmp
[i
] = cpu_to_le32(buf
[i
]);
662 pci_dma_write(&xhci
->pci_dev
, addr
, tmp
, len
);
665 static XHCIPort
*xhci_lookup_port(XHCIState
*xhci
, struct USBPort
*uport
)
672 switch (uport
->dev
->speed
) {
676 index
= uport
->index
;
678 case USB_SPEED_SUPER
:
679 index
= uport
->index
+ xhci
->numports_2
;
684 return &xhci
->ports
[index
];
687 static void xhci_intx_update(XHCIState
*xhci
)
691 if (msix_enabled(&xhci
->pci_dev
) ||
692 msi_enabled(&xhci
->pci_dev
)) {
696 if (xhci
->intr
[0].iman
& IMAN_IP
&&
697 xhci
->intr
[0].iman
& IMAN_IE
&&
698 xhci
->usbcmd
& USBCMD_INTE
) {
702 trace_usb_xhci_irq_intx(level
);
703 qemu_set_irq(xhci
->irq
, level
);
706 static void xhci_msix_update(XHCIState
*xhci
, int v
)
710 if (!msix_enabled(&xhci
->pci_dev
)) {
714 enabled
= xhci
->intr
[v
].iman
& IMAN_IE
;
715 if (enabled
== xhci
->intr
[v
].msix_used
) {
720 trace_usb_xhci_irq_msix_use(v
);
721 msix_vector_use(&xhci
->pci_dev
, v
);
722 xhci
->intr
[v
].msix_used
= true;
724 trace_usb_xhci_irq_msix_unuse(v
);
725 msix_vector_unuse(&xhci
->pci_dev
, v
);
726 xhci
->intr
[v
].msix_used
= false;
730 static void xhci_intr_raise(XHCIState
*xhci
, int v
)
732 xhci
->intr
[v
].erdp_low
|= ERDP_EHB
;
733 xhci
->intr
[v
].iman
|= IMAN_IP
;
734 xhci
->usbsts
|= USBSTS_EINT
;
736 if (!(xhci
->intr
[v
].iman
& IMAN_IE
)) {
740 if (!(xhci
->usbcmd
& USBCMD_INTE
)) {
744 if (msix_enabled(&xhci
->pci_dev
)) {
745 trace_usb_xhci_irq_msix(v
);
746 msix_notify(&xhci
->pci_dev
, v
);
750 if (msi_enabled(&xhci
->pci_dev
)) {
751 trace_usb_xhci_irq_msi(v
);
752 msi_notify(&xhci
->pci_dev
, v
);
757 trace_usb_xhci_irq_intx(1);
758 qemu_set_irq(xhci
->irq
, 1);
762 static inline int xhci_running(XHCIState
*xhci
)
764 return !(xhci
->usbsts
& USBSTS_HCH
) && !xhci
->intr
[0].er_full
;
767 static void xhci_die(XHCIState
*xhci
)
769 xhci
->usbsts
|= USBSTS_HCE
;
770 fprintf(stderr
, "xhci: asserted controller error\n");
773 static void xhci_write_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
)
775 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
779 ev_trb
.parameter
= cpu_to_le64(event
->ptr
);
780 ev_trb
.status
= cpu_to_le32(event
->length
| (event
->ccode
<< 24));
781 ev_trb
.control
= (event
->slotid
<< 24) | (event
->epid
<< 16) |
782 event
->flags
| (event
->type
<< TRB_TYPE_SHIFT
);
784 ev_trb
.control
|= TRB_C
;
786 ev_trb
.control
= cpu_to_le32(ev_trb
.control
);
788 trace_usb_xhci_queue_event(v
, intr
->er_ep_idx
, trb_name(&ev_trb
),
789 event_name(event
), ev_trb
.parameter
,
790 ev_trb
.status
, ev_trb
.control
);
792 addr
= intr
->er_start
+ TRB_SIZE
*intr
->er_ep_idx
;
793 pci_dma_write(&xhci
->pci_dev
, addr
, &ev_trb
, TRB_SIZE
);
796 if (intr
->er_ep_idx
>= intr
->er_size
) {
798 intr
->er_pcs
= !intr
->er_pcs
;
802 static void xhci_events_update(XHCIState
*xhci
, int v
)
804 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
809 if (xhci
->usbsts
& USBSTS_HCH
) {
813 erdp
= xhci_addr64(intr
->erdp_low
, intr
->erdp_high
);
814 if (erdp
< intr
->er_start
||
815 erdp
>= (intr
->er_start
+ TRB_SIZE
*intr
->er_size
)) {
816 fprintf(stderr
, "xhci: ERDP out of bounds: "DMA_ADDR_FMT
"\n", erdp
);
817 fprintf(stderr
, "xhci: ER[%d] at "DMA_ADDR_FMT
" len %d\n",
818 v
, intr
->er_start
, intr
->er_size
);
822 dp_idx
= (erdp
- intr
->er_start
) / TRB_SIZE
;
823 assert(dp_idx
< intr
->er_size
);
825 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
826 * deadlocks when the ER is full. Hack it by holding off events until
827 * the driver decides to free at least half of the ring */
829 int er_free
= dp_idx
- intr
->er_ep_idx
;
831 er_free
+= intr
->er_size
;
833 if (er_free
< (intr
->er_size
/2)) {
834 DPRINTF("xhci_events_update(): event ring still "
835 "more than half full (hack)\n");
840 while (intr
->ev_buffer_put
!= intr
->ev_buffer_get
) {
841 assert(intr
->er_full
);
842 if (((intr
->er_ep_idx
+1) % intr
->er_size
) == dp_idx
) {
843 DPRINTF("xhci_events_update(): event ring full again\n");
845 XHCIEvent full
= {ER_HOST_CONTROLLER
, CC_EVENT_RING_FULL_ERROR
};
846 xhci_write_event(xhci
, &full
, v
);
851 XHCIEvent
*event
= &intr
->ev_buffer
[intr
->ev_buffer_get
];
852 xhci_write_event(xhci
, event
, v
);
853 intr
->ev_buffer_get
++;
855 if (intr
->ev_buffer_get
== EV_QUEUE
) {
856 intr
->ev_buffer_get
= 0;
861 xhci_intr_raise(xhci
, v
);
864 if (intr
->er_full
&& intr
->ev_buffer_put
== intr
->ev_buffer_get
) {
865 DPRINTF("xhci_events_update(): event ring no longer full\n");
870 static void xhci_event(XHCIState
*xhci
, XHCIEvent
*event
, int v
)
872 XHCIInterrupter
*intr
;
876 if (v
>= xhci
->numintrs
) {
877 DPRINTF("intr nr out of range (%d >= %d)\n", v
, xhci
->numintrs
);
880 intr
= &xhci
->intr
[v
];
883 DPRINTF("xhci_event(): ER full, queueing\n");
884 if (((intr
->ev_buffer_put
+1) % EV_QUEUE
) == intr
->ev_buffer_get
) {
885 fprintf(stderr
, "xhci: event queue full, dropping event!\n");
888 intr
->ev_buffer
[intr
->ev_buffer_put
++] = *event
;
889 if (intr
->ev_buffer_put
== EV_QUEUE
) {
890 intr
->ev_buffer_put
= 0;
895 erdp
= xhci_addr64(intr
->erdp_low
, intr
->erdp_high
);
896 if (erdp
< intr
->er_start
||
897 erdp
>= (intr
->er_start
+ TRB_SIZE
*intr
->er_size
)) {
898 fprintf(stderr
, "xhci: ERDP out of bounds: "DMA_ADDR_FMT
"\n", erdp
);
899 fprintf(stderr
, "xhci: ER[%d] at "DMA_ADDR_FMT
" len %d\n",
900 v
, intr
->er_start
, intr
->er_size
);
905 dp_idx
= (erdp
- intr
->er_start
) / TRB_SIZE
;
906 assert(dp_idx
< intr
->er_size
);
908 if ((intr
->er_ep_idx
+1) % intr
->er_size
== dp_idx
) {
909 DPRINTF("xhci_event(): ER full, queueing\n");
911 XHCIEvent full
= {ER_HOST_CONTROLLER
, CC_EVENT_RING_FULL_ERROR
};
912 xhci_write_event(xhci
, &full
);
915 if (((intr
->ev_buffer_put
+1) % EV_QUEUE
) == intr
->ev_buffer_get
) {
916 fprintf(stderr
, "xhci: event queue full, dropping event!\n");
919 intr
->ev_buffer
[intr
->ev_buffer_put
++] = *event
;
920 if (intr
->ev_buffer_put
== EV_QUEUE
) {
921 intr
->ev_buffer_put
= 0;
924 xhci_write_event(xhci
, event
, v
);
927 xhci_intr_raise(xhci
, v
);
930 static void xhci_ring_init(XHCIState
*xhci
, XHCIRing
*ring
,
934 ring
->dequeue
= base
;
938 static TRBType
xhci_ring_fetch(XHCIState
*xhci
, XHCIRing
*ring
, XHCITRB
*trb
,
943 pci_dma_read(&xhci
->pci_dev
, ring
->dequeue
, trb
, TRB_SIZE
);
944 trb
->addr
= ring
->dequeue
;
945 trb
->ccs
= ring
->ccs
;
946 le64_to_cpus(&trb
->parameter
);
947 le32_to_cpus(&trb
->status
);
948 le32_to_cpus(&trb
->control
);
950 trace_usb_xhci_fetch_trb(ring
->dequeue
, trb_name(trb
),
951 trb
->parameter
, trb
->status
, trb
->control
);
953 if ((trb
->control
& TRB_C
) != ring
->ccs
) {
957 type
= TRB_TYPE(*trb
);
959 if (type
!= TR_LINK
) {
961 *addr
= ring
->dequeue
;
963 ring
->dequeue
+= TRB_SIZE
;
966 ring
->dequeue
= xhci_mask64(trb
->parameter
);
967 if (trb
->control
& TRB_LK_TC
) {
968 ring
->ccs
= !ring
->ccs
;
974 static int xhci_ring_chain_length(XHCIState
*xhci
, const XHCIRing
*ring
)
978 dma_addr_t dequeue
= ring
->dequeue
;
979 bool ccs
= ring
->ccs
;
980 /* hack to bundle together the two/three TDs that make a setup transfer */
981 bool control_td_set
= 0;
985 pci_dma_read(&xhci
->pci_dev
, dequeue
, &trb
, TRB_SIZE
);
986 le64_to_cpus(&trb
.parameter
);
987 le32_to_cpus(&trb
.status
);
988 le32_to_cpus(&trb
.control
);
990 if ((trb
.control
& TRB_C
) != ccs
) {
994 type
= TRB_TYPE(trb
);
996 if (type
== TR_LINK
) {
997 dequeue
= xhci_mask64(trb
.parameter
);
998 if (trb
.control
& TRB_LK_TC
) {
1005 dequeue
+= TRB_SIZE
;
1007 if (type
== TR_SETUP
) {
1009 } else if (type
== TR_STATUS
) {
1013 if (!control_td_set
&& !(trb
.control
& TRB_TR_CH
)) {
1019 static void xhci_er_reset(XHCIState
*xhci
, int v
)
1021 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
1024 if (intr
->erstsz
== 0) {
1030 /* cache the (sole) event ring segment location */
1031 if (intr
->erstsz
!= 1) {
1032 fprintf(stderr
, "xhci: invalid value for ERSTSZ: %d\n", intr
->erstsz
);
1036 dma_addr_t erstba
= xhci_addr64(intr
->erstba_low
, intr
->erstba_high
);
1037 pci_dma_read(&xhci
->pci_dev
, erstba
, &seg
, sizeof(seg
));
1038 le32_to_cpus(&seg
.addr_low
);
1039 le32_to_cpus(&seg
.addr_high
);
1040 le32_to_cpus(&seg
.size
);
1041 if (seg
.size
< 16 || seg
.size
> 4096) {
1042 fprintf(stderr
, "xhci: invalid value for segment size: %d\n", seg
.size
);
1046 intr
->er_start
= xhci_addr64(seg
.addr_low
, seg
.addr_high
);
1047 intr
->er_size
= seg
.size
;
1049 intr
->er_ep_idx
= 0;
1053 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT
" [%d]\n",
1054 v
, intr
->er_start
, intr
->er_size
);
1057 static void xhci_run(XHCIState
*xhci
)
1059 trace_usb_xhci_run();
1060 xhci
->usbsts
&= ~USBSTS_HCH
;
1061 xhci
->mfindex_start
= qemu_get_clock_ns(vm_clock
);
1064 static void xhci_stop(XHCIState
*xhci
)
1066 trace_usb_xhci_stop();
1067 xhci
->usbsts
|= USBSTS_HCH
;
1068 xhci
->crcr_low
&= ~CRCR_CRR
;
1071 static void xhci_set_ep_state(XHCIState
*xhci
, XHCIEPContext
*epctx
,
1076 xhci_dma_read_u32s(xhci
, epctx
->pctx
, ctx
, sizeof(ctx
));
1077 ctx
[0] &= ~EP_STATE_MASK
;
1079 ctx
[2] = epctx
->ring
.dequeue
| epctx
->ring
.ccs
;
1080 ctx
[3] = (epctx
->ring
.dequeue
>> 16) >> 16;
1081 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT
" state=%d dequeue=%08x%08x\n",
1082 epctx
->pctx
, state
, ctx
[3], ctx
[2]);
1083 xhci_dma_write_u32s(xhci
, epctx
->pctx
, ctx
, sizeof(ctx
));
1084 epctx
->state
= state
;
1087 static void xhci_ep_kick_timer(void *opaque
)
1089 XHCIEPContext
*epctx
= opaque
;
1090 xhci_kick_ep(epctx
->xhci
, epctx
->slotid
, epctx
->epid
);
1093 static TRBCCode
xhci_enable_ep(XHCIState
*xhci
, unsigned int slotid
,
1094 unsigned int epid
, dma_addr_t pctx
,
1098 XHCIEPContext
*epctx
;
1102 trace_usb_xhci_ep_enable(slotid
, epid
);
1103 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1104 assert(epid
>= 1 && epid
<= 31);
1106 slot
= &xhci
->slots
[slotid
-1];
1107 if (slot
->eps
[epid
-1]) {
1108 xhci_disable_ep(xhci
, slotid
, epid
);
1111 epctx
= g_malloc(sizeof(XHCIEPContext
));
1112 memset(epctx
, 0, sizeof(XHCIEPContext
));
1114 epctx
->slotid
= slotid
;
1117 slot
->eps
[epid
-1] = epctx
;
1119 dequeue
= xhci_addr64(ctx
[2] & ~0xf, ctx
[3]);
1120 xhci_ring_init(xhci
, &epctx
->ring
, dequeue
);
1121 epctx
->ring
.ccs
= ctx
[2] & 1;
1123 epctx
->type
= (ctx
[1] >> EP_TYPE_SHIFT
) & EP_TYPE_MASK
;
1124 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid
/2, epid
%2, epctx
->type
);
1126 epctx
->max_psize
= ctx
[1]>>16;
1127 epctx
->max_psize
*= 1+((ctx
[1]>>8)&0xff);
1128 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n",
1129 epid
/2, epid
%2, epctx
->max_psize
);
1130 for (i
= 0; i
< ARRAY_SIZE(epctx
->transfers
); i
++) {
1131 usb_packet_init(&epctx
->transfers
[i
].packet
);
1134 epctx
->interval
= 1 << (ctx
[0] >> 16) & 0xff;
1135 epctx
->mfindex_last
= 0;
1136 epctx
->kick_timer
= qemu_new_timer_ns(vm_clock
, xhci_ep_kick_timer
, epctx
);
1138 epctx
->state
= EP_RUNNING
;
1139 ctx
[0] &= ~EP_STATE_MASK
;
1140 ctx
[0] |= EP_RUNNING
;
1145 static int xhci_ep_nuke_one_xfer(XHCITransfer
*t
)
1149 if (t
->running_async
) {
1150 usb_cancel_packet(&t
->packet
);
1151 t
->running_async
= 0;
1153 DPRINTF("xhci: cancelling transfer, waiting for it to complete\n");
1156 if (t
->running_retry
) {
1157 XHCIEPContext
*epctx
= t
->xhci
->slots
[t
->slotid
-1].eps
[t
->epid
-1];
1159 epctx
->retry
= NULL
;
1160 qemu_del_timer(epctx
->kick_timer
);
1162 t
->running_retry
= 0;
1169 t
->trb_count
= t
->trb_alloced
= 0;
1174 static int xhci_ep_nuke_xfers(XHCIState
*xhci
, unsigned int slotid
,
1178 XHCIEPContext
*epctx
;
1179 int i
, xferi
, killed
= 0;
1180 USBEndpoint
*ep
= NULL
;
1181 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1182 assert(epid
>= 1 && epid
<= 31);
1184 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid
, epid
);
1186 slot
= &xhci
->slots
[slotid
-1];
1188 if (!slot
->eps
[epid
-1]) {
1192 epctx
= slot
->eps
[epid
-1];
1194 xferi
= epctx
->next_xfer
;
1195 for (i
= 0; i
< TD_QUEUE
; i
++) {
1196 if (epctx
->transfers
[xferi
].packet
.ep
) {
1197 ep
= epctx
->transfers
[xferi
].packet
.ep
;
1199 killed
+= xhci_ep_nuke_one_xfer(&epctx
->transfers
[xferi
]);
1200 xferi
= (xferi
+ 1) % TD_QUEUE
;
1203 usb_device_ep_stopped(ep
->dev
, ep
);
1208 static TRBCCode
xhci_disable_ep(XHCIState
*xhci
, unsigned int slotid
,
1212 XHCIEPContext
*epctx
;
1214 trace_usb_xhci_ep_disable(slotid
, epid
);
1215 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1216 assert(epid
>= 1 && epid
<= 31);
1218 slot
= &xhci
->slots
[slotid
-1];
1220 if (!slot
->eps
[epid
-1]) {
1221 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid
, epid
);
1225 xhci_ep_nuke_xfers(xhci
, slotid
, epid
);
1227 epctx
= slot
->eps
[epid
-1];
1229 xhci_set_ep_state(xhci
, epctx
, EP_DISABLED
);
1231 qemu_free_timer(epctx
->kick_timer
);
1233 slot
->eps
[epid
-1] = NULL
;
1238 static TRBCCode
xhci_stop_ep(XHCIState
*xhci
, unsigned int slotid
,
1242 XHCIEPContext
*epctx
;
1244 trace_usb_xhci_ep_stop(slotid
, epid
);
1245 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1247 if (epid
< 1 || epid
> 31) {
1248 fprintf(stderr
, "xhci: bad ep %d\n", epid
);
1249 return CC_TRB_ERROR
;
1252 slot
= &xhci
->slots
[slotid
-1];
1254 if (!slot
->eps
[epid
-1]) {
1255 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1256 return CC_EP_NOT_ENABLED_ERROR
;
1259 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
) > 0) {
1260 fprintf(stderr
, "xhci: FIXME: endpoint stopped w/ xfers running, "
1261 "data might be lost\n");
1264 epctx
= slot
->eps
[epid
-1];
1266 xhci_set_ep_state(xhci
, epctx
, EP_STOPPED
);
1271 static TRBCCode
xhci_reset_ep(XHCIState
*xhci
, unsigned int slotid
,
1275 XHCIEPContext
*epctx
;
1278 trace_usb_xhci_ep_reset(slotid
, epid
);
1279 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1281 if (epid
< 1 || epid
> 31) {
1282 fprintf(stderr
, "xhci: bad ep %d\n", epid
);
1283 return CC_TRB_ERROR
;
1286 slot
= &xhci
->slots
[slotid
-1];
1288 if (!slot
->eps
[epid
-1]) {
1289 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1290 return CC_EP_NOT_ENABLED_ERROR
;
1293 epctx
= slot
->eps
[epid
-1];
1295 if (epctx
->state
!= EP_HALTED
) {
1296 fprintf(stderr
, "xhci: reset EP while EP %d not halted (%d)\n",
1297 epid
, epctx
->state
);
1298 return CC_CONTEXT_STATE_ERROR
;
1301 if (xhci_ep_nuke_xfers(xhci
, slotid
, epid
) > 0) {
1302 fprintf(stderr
, "xhci: FIXME: endpoint reset w/ xfers running, "
1303 "data might be lost\n");
1306 uint8_t ep
= epid
>>1;
1312 dev
= xhci
->slots
[slotid
-1].uport
->dev
;
1314 return CC_USB_TRANSACTION_ERROR
;
1317 xhci_set_ep_state(xhci
, epctx
, EP_STOPPED
);
1322 static TRBCCode
xhci_set_ep_dequeue(XHCIState
*xhci
, unsigned int slotid
,
1323 unsigned int epid
, uint64_t pdequeue
)
1326 XHCIEPContext
*epctx
;
1329 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1331 if (epid
< 1 || epid
> 31) {
1332 fprintf(stderr
, "xhci: bad ep %d\n", epid
);
1333 return CC_TRB_ERROR
;
1336 trace_usb_xhci_ep_set_dequeue(slotid
, epid
, pdequeue
);
1337 dequeue
= xhci_mask64(pdequeue
);
1339 slot
= &xhci
->slots
[slotid
-1];
1341 if (!slot
->eps
[epid
-1]) {
1342 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid
, epid
);
1343 return CC_EP_NOT_ENABLED_ERROR
;
1346 epctx
= slot
->eps
[epid
-1];
1349 if (epctx
->state
!= EP_STOPPED
) {
1350 fprintf(stderr
, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid
);
1351 return CC_CONTEXT_STATE_ERROR
;
1354 xhci_ring_init(xhci
, &epctx
->ring
, dequeue
& ~0xF);
1355 epctx
->ring
.ccs
= dequeue
& 1;
1357 xhci_set_ep_state(xhci
, epctx
, EP_STOPPED
);
1362 static int xhci_xfer_create_sgl(XHCITransfer
*xfer
, int in_xfer
)
1364 XHCIState
*xhci
= xfer
->xhci
;
1367 xfer
->int_req
= false;
1368 pci_dma_sglist_init(&xfer
->sgl
, &xhci
->pci_dev
, xfer
->trb_count
);
1369 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1370 XHCITRB
*trb
= &xfer
->trbs
[i
];
1372 unsigned int chunk
= 0;
1374 if (trb
->control
& TRB_TR_IOC
) {
1375 xfer
->int_req
= true;
1378 switch (TRB_TYPE(*trb
)) {
1380 if ((!(trb
->control
& TRB_TR_DIR
)) != (!in_xfer
)) {
1381 fprintf(stderr
, "xhci: data direction mismatch for TR_DATA\n");
1387 addr
= xhci_mask64(trb
->parameter
);
1388 chunk
= trb
->status
& 0x1ffff;
1389 if (trb
->control
& TRB_TR_IDT
) {
1390 if (chunk
> 8 || in_xfer
) {
1391 fprintf(stderr
, "xhci: invalid immediate data TRB\n");
1394 qemu_sglist_add(&xfer
->sgl
, trb
->addr
, chunk
);
1396 qemu_sglist_add(&xfer
->sgl
, addr
, chunk
);
1405 qemu_sglist_destroy(&xfer
->sgl
);
1410 static void xhci_xfer_unmap(XHCITransfer
*xfer
)
1412 usb_packet_unmap(&xfer
->packet
, &xfer
->sgl
);
1413 qemu_sglist_destroy(&xfer
->sgl
);
1416 static void xhci_xfer_report(XHCITransfer
*xfer
)
1422 XHCIEvent event
= {ER_TRANSFER
, CC_SUCCESS
};
1423 XHCIState
*xhci
= xfer
->xhci
;
1426 left
= xfer
->packet
.actual_length
;
1428 for (i
= 0; i
< xfer
->trb_count
; i
++) {
1429 XHCITRB
*trb
= &xfer
->trbs
[i
];
1430 unsigned int chunk
= 0;
1432 switch (TRB_TYPE(*trb
)) {
1436 chunk
= trb
->status
& 0x1ffff;
1439 if (xfer
->status
== CC_SUCCESS
) {
1452 if (!reported
&& ((trb
->control
& TRB_TR_IOC
) ||
1453 (shortpkt
&& (trb
->control
& TRB_TR_ISP
)) ||
1454 (xfer
->status
!= CC_SUCCESS
&& left
== 0))) {
1455 event
.slotid
= xfer
->slotid
;
1456 event
.epid
= xfer
->epid
;
1457 event
.length
= (trb
->status
& 0x1ffff) - chunk
;
1459 event
.ptr
= trb
->addr
;
1460 if (xfer
->status
== CC_SUCCESS
) {
1461 event
.ccode
= shortpkt
? CC_SHORT_PACKET
: CC_SUCCESS
;
1463 event
.ccode
= xfer
->status
;
1465 if (TRB_TYPE(*trb
) == TR_EVDATA
) {
1466 event
.ptr
= trb
->parameter
;
1467 event
.flags
|= TRB_EV_ED
;
1468 event
.length
= edtla
& 0xffffff;
1469 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event
.length
);
1472 xhci_event(xhci
, &event
, TRB_INTR(*trb
));
1474 if (xfer
->status
!= CC_SUCCESS
) {
1481 static void xhci_stall_ep(XHCITransfer
*xfer
)
1483 XHCIState
*xhci
= xfer
->xhci
;
1484 XHCISlot
*slot
= &xhci
->slots
[xfer
->slotid
-1];
1485 XHCIEPContext
*epctx
= slot
->eps
[xfer
->epid
-1];
1487 epctx
->ring
.dequeue
= xfer
->trbs
[0].addr
;
1488 epctx
->ring
.ccs
= xfer
->trbs
[0].ccs
;
1489 xhci_set_ep_state(xhci
, epctx
, EP_HALTED
);
1490 DPRINTF("xhci: stalled slot %d ep %d\n", xfer
->slotid
, xfer
->epid
);
1491 DPRINTF("xhci: will continue at "DMA_ADDR_FMT
"\n", epctx
->ring
.dequeue
);
1494 static int xhci_submit(XHCIState
*xhci
, XHCITransfer
*xfer
,
1495 XHCIEPContext
*epctx
);
1497 static int xhci_setup_packet(XHCITransfer
*xfer
)
1499 XHCIState
*xhci
= xfer
->xhci
;
1504 dir
= xfer
->in_xfer
? USB_TOKEN_IN
: USB_TOKEN_OUT
;
1506 if (xfer
->packet
.ep
) {
1507 ep
= xfer
->packet
.ep
;
1510 if (!xhci
->slots
[xfer
->slotid
-1].uport
) {
1511 fprintf(stderr
, "xhci: slot %d has no device\n",
1515 dev
= xhci
->slots
[xfer
->slotid
-1].uport
->dev
;
1516 ep
= usb_ep_get(dev
, dir
, xfer
->epid
>> 1);
1519 xhci_xfer_create_sgl(xfer
, dir
== USB_TOKEN_IN
); /* Also sets int_req */
1520 usb_packet_setup(&xfer
->packet
, dir
, ep
, xfer
->trbs
[0].addr
, false,
1522 usb_packet_map(&xfer
->packet
, &xfer
->sgl
);
1523 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1524 xfer
->packet
.pid
, dev
->addr
, ep
->nr
);
1528 static int xhci_complete_packet(XHCITransfer
*xfer
)
1530 if (xfer
->packet
.status
== USB_RET_ASYNC
) {
1531 trace_usb_xhci_xfer_async(xfer
);
1532 xfer
->running_async
= 1;
1533 xfer
->running_retry
= 0;
1535 xfer
->cancelled
= 0;
1537 } else if (xfer
->packet
.status
== USB_RET_NAK
) {
1538 trace_usb_xhci_xfer_nak(xfer
);
1539 xfer
->running_async
= 0;
1540 xfer
->running_retry
= 1;
1542 xfer
->cancelled
= 0;
1545 xfer
->running_async
= 0;
1546 xfer
->running_retry
= 0;
1548 xhci_xfer_unmap(xfer
);
1551 if (xfer
->packet
.status
== USB_RET_SUCCESS
) {
1552 trace_usb_xhci_xfer_success(xfer
, xfer
->packet
.actual_length
);
1553 xfer
->status
= CC_SUCCESS
;
1554 xhci_xfer_report(xfer
);
1559 trace_usb_xhci_xfer_error(xfer
, xfer
->packet
.status
);
1560 switch (xfer
->packet
.status
) {
1562 xfer
->status
= CC_USB_TRANSACTION_ERROR
;
1563 xhci_xfer_report(xfer
);
1564 xhci_stall_ep(xfer
);
1567 xfer
->status
= CC_STALL_ERROR
;
1568 xhci_xfer_report(xfer
);
1569 xhci_stall_ep(xfer
);
1572 fprintf(stderr
, "%s: FIXME: status = %d\n", __func__
,
1573 xfer
->packet
.status
);
1579 static int xhci_fire_ctl_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
)
1581 XHCITRB
*trb_setup
, *trb_status
;
1582 uint8_t bmRequestType
;
1584 trb_setup
= &xfer
->trbs
[0];
1585 trb_status
= &xfer
->trbs
[xfer
->trb_count
-1];
1587 trace_usb_xhci_xfer_start(xfer
, xfer
->slotid
, xfer
->epid
);
1589 /* at most one Event Data TRB allowed after STATUS */
1590 if (TRB_TYPE(*trb_status
) == TR_EVDATA
&& xfer
->trb_count
> 2) {
1594 /* do some sanity checks */
1595 if (TRB_TYPE(*trb_setup
) != TR_SETUP
) {
1596 fprintf(stderr
, "xhci: ep0 first TD not SETUP: %d\n",
1597 TRB_TYPE(*trb_setup
));
1600 if (TRB_TYPE(*trb_status
) != TR_STATUS
) {
1601 fprintf(stderr
, "xhci: ep0 last TD not STATUS: %d\n",
1602 TRB_TYPE(*trb_status
));
1605 if (!(trb_setup
->control
& TRB_TR_IDT
)) {
1606 fprintf(stderr
, "xhci: Setup TRB doesn't have IDT set\n");
1609 if ((trb_setup
->status
& 0x1ffff) != 8) {
1610 fprintf(stderr
, "xhci: Setup TRB has bad length (%d)\n",
1611 (trb_setup
->status
& 0x1ffff));
1615 bmRequestType
= trb_setup
->parameter
;
1617 xfer
->in_xfer
= bmRequestType
& USB_DIR_IN
;
1618 xfer
->iso_xfer
= false;
1620 if (xhci_setup_packet(xfer
) < 0) {
1623 xfer
->packet
.parameter
= trb_setup
->parameter
;
1625 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1627 xhci_complete_packet(xfer
);
1628 if (!xfer
->running_async
&& !xfer
->running_retry
) {
1629 xhci_kick_ep(xhci
, xfer
->slotid
, xfer
->epid
);
1634 static void xhci_calc_iso_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1635 XHCIEPContext
*epctx
, uint64_t mfindex
)
1637 if (xfer
->trbs
[0].control
& TRB_TR_SIA
) {
1638 uint64_t asap
= ((mfindex
+ epctx
->interval
- 1) &
1639 ~(epctx
->interval
-1));
1640 if (asap
>= epctx
->mfindex_last
&&
1641 asap
<= epctx
->mfindex_last
+ epctx
->interval
* 4) {
1642 xfer
->mfindex_kick
= epctx
->mfindex_last
+ epctx
->interval
;
1644 xfer
->mfindex_kick
= asap
;
1647 xfer
->mfindex_kick
= (xfer
->trbs
[0].control
>> TRB_TR_FRAMEID_SHIFT
)
1648 & TRB_TR_FRAMEID_MASK
;
1649 xfer
->mfindex_kick
|= mfindex
& ~0x3fff;
1650 if (xfer
->mfindex_kick
< mfindex
) {
1651 xfer
->mfindex_kick
+= 0x4000;
1656 static void xhci_check_iso_kick(XHCIState
*xhci
, XHCITransfer
*xfer
,
1657 XHCIEPContext
*epctx
, uint64_t mfindex
)
1659 if (xfer
->mfindex_kick
> mfindex
) {
1660 qemu_mod_timer(epctx
->kick_timer
, qemu_get_clock_ns(vm_clock
) +
1661 (xfer
->mfindex_kick
- mfindex
) * 125000);
1662 xfer
->running_retry
= 1;
1664 epctx
->mfindex_last
= xfer
->mfindex_kick
;
1665 qemu_del_timer(epctx
->kick_timer
);
1666 xfer
->running_retry
= 0;
1671 static int xhci_submit(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
1675 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer
->slotid
, xfer
->epid
);
1677 xfer
->in_xfer
= epctx
->type
>>2;
1679 switch(epctx
->type
) {
1685 xfer
->iso_xfer
= false;
1690 xfer
->iso_xfer
= true;
1691 mfindex
= xhci_mfindex_get(xhci
);
1692 xhci_calc_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1693 xhci_check_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1694 if (xfer
->running_retry
) {
1699 fprintf(stderr
, "xhci: unknown or unhandled EP "
1700 "(type %d, in %d, ep %02x)\n",
1701 epctx
->type
, xfer
->in_xfer
, xfer
->epid
);
1705 if (xhci_setup_packet(xfer
) < 0) {
1708 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1710 xhci_complete_packet(xfer
);
1711 if (!xfer
->running_async
&& !xfer
->running_retry
) {
1712 xhci_kick_ep(xhci
, xfer
->slotid
, xfer
->epid
);
1717 static int xhci_fire_transfer(XHCIState
*xhci
, XHCITransfer
*xfer
, XHCIEPContext
*epctx
)
1719 trace_usb_xhci_xfer_start(xfer
, xfer
->slotid
, xfer
->epid
);
1720 return xhci_submit(xhci
, xfer
, epctx
);
1723 static void xhci_kick_ep(XHCIState
*xhci
, unsigned int slotid
, unsigned int epid
)
1725 XHCIEPContext
*epctx
;
1726 USBEndpoint
*ep
= NULL
;
1731 trace_usb_xhci_ep_kick(slotid
, epid
);
1732 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1733 assert(epid
>= 1 && epid
<= 31);
1735 if (!xhci
->slots
[slotid
-1].enabled
) {
1736 fprintf(stderr
, "xhci: xhci_kick_ep for disabled slot %d\n", slotid
);
1739 epctx
= xhci
->slots
[slotid
-1].eps
[epid
-1];
1741 fprintf(stderr
, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1747 XHCITransfer
*xfer
= epctx
->retry
;
1749 trace_usb_xhci_xfer_retry(xfer
);
1750 assert(xfer
->running_retry
);
1751 if (xfer
->iso_xfer
) {
1752 /* retry delayed iso transfer */
1753 mfindex
= xhci_mfindex_get(xhci
);
1754 xhci_check_iso_kick(xhci
, xfer
, epctx
, mfindex
);
1755 if (xfer
->running_retry
) {
1758 if (xhci_setup_packet(xfer
) < 0) {
1761 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1762 assert(xfer
->packet
.status
!= USB_RET_NAK
);
1763 xhci_complete_packet(xfer
);
1765 /* retry nak'ed transfer */
1766 if (xhci_setup_packet(xfer
) < 0) {
1769 usb_handle_packet(xfer
->packet
.ep
->dev
, &xfer
->packet
);
1770 if (xfer
->packet
.status
== USB_RET_NAK
) {
1773 xhci_complete_packet(xfer
);
1775 assert(!xfer
->running_retry
);
1776 epctx
->retry
= NULL
;
1779 if (epctx
->state
== EP_HALTED
) {
1780 DPRINTF("xhci: ep halted, not running schedule\n");
1784 xhci_set_ep_state(xhci
, epctx
, EP_RUNNING
);
1787 XHCITransfer
*xfer
= &epctx
->transfers
[epctx
->next_xfer
];
1788 if (xfer
->running_async
|| xfer
->running_retry
) {
1791 length
= xhci_ring_chain_length(xhci
, &epctx
->ring
);
1794 } else if (length
== 0) {
1797 if (xfer
->trbs
&& xfer
->trb_alloced
< length
) {
1798 xfer
->trb_count
= 0;
1799 xfer
->trb_alloced
= 0;
1804 xfer
->trbs
= g_malloc(sizeof(XHCITRB
) * length
);
1805 xfer
->trb_alloced
= length
;
1807 xfer
->trb_count
= length
;
1809 for (i
= 0; i
< length
; i
++) {
1810 assert(xhci_ring_fetch(xhci
, &epctx
->ring
, &xfer
->trbs
[i
], NULL
));
1814 xfer
->slotid
= slotid
;
1817 if (xhci_fire_ctl_transfer(xhci
, xfer
) >= 0) {
1818 epctx
->next_xfer
= (epctx
->next_xfer
+ 1) % TD_QUEUE
;
1819 ep
= xfer
->packet
.ep
;
1821 fprintf(stderr
, "xhci: error firing CTL transfer\n");
1824 if (xhci_fire_transfer(xhci
, xfer
, epctx
) >= 0) {
1825 epctx
->next_xfer
= (epctx
->next_xfer
+ 1) % TD_QUEUE
;
1826 ep
= xfer
->packet
.ep
;
1828 if (!xfer
->iso_xfer
) {
1829 fprintf(stderr
, "xhci: error firing data transfer\n");
1834 if (epctx
->state
== EP_HALTED
) {
1837 if (xfer
->running_retry
) {
1838 DPRINTF("xhci: xfer nacked, stopping schedule\n");
1839 epctx
->retry
= xfer
;
1844 usb_device_flush_ep_queue(ep
->dev
, ep
);
1848 static TRBCCode
xhci_enable_slot(XHCIState
*xhci
, unsigned int slotid
)
1850 trace_usb_xhci_slot_enable(slotid
);
1851 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1852 xhci
->slots
[slotid
-1].enabled
= 1;
1853 xhci
->slots
[slotid
-1].uport
= NULL
;
1854 memset(xhci
->slots
[slotid
-1].eps
, 0, sizeof(XHCIEPContext
*)*31);
1859 static TRBCCode
xhci_disable_slot(XHCIState
*xhci
, unsigned int slotid
)
1863 trace_usb_xhci_slot_disable(slotid
);
1864 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1866 for (i
= 1; i
<= 31; i
++) {
1867 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
1868 xhci_disable_ep(xhci
, slotid
, i
);
1872 xhci
->slots
[slotid
-1].enabled
= 0;
1876 static USBPort
*xhci_lookup_uport(XHCIState
*xhci
, uint32_t *slot_ctx
)
1882 port
= (slot_ctx
[1]>>16) & 0xFF;
1883 port
= xhci
->ports
[port
-1].uport
->index
+1;
1884 pos
= snprintf(path
, sizeof(path
), "%d", port
);
1885 for (i
= 0; i
< 5; i
++) {
1886 port
= (slot_ctx
[0] >> 4*i
) & 0x0f;
1890 pos
+= snprintf(path
+ pos
, sizeof(path
) - pos
, ".%d", port
);
1893 QTAILQ_FOREACH(uport
, &xhci
->bus
.used
, next
) {
1894 if (strcmp(uport
->path
, path
) == 0) {
1901 static TRBCCode
xhci_address_slot(XHCIState
*xhci
, unsigned int slotid
,
1902 uint64_t pictx
, bool bsr
)
1907 dma_addr_t ictx
, octx
, dcbaap
;
1909 uint32_t ictl_ctx
[2];
1910 uint32_t slot_ctx
[4];
1911 uint32_t ep0_ctx
[5];
1915 trace_usb_xhci_slot_address(slotid
);
1916 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
1918 dcbaap
= xhci_addr64(xhci
->dcbaap_low
, xhci
->dcbaap_high
);
1919 poctx
= ldq_le_pci_dma(&xhci
->pci_dev
, dcbaap
+ 8*slotid
);
1920 ictx
= xhci_mask64(pictx
);
1921 octx
= xhci_mask64(poctx
);
1923 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
1924 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
1926 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
1928 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] != 0x3) {
1929 fprintf(stderr
, "xhci: invalid input context control %08x %08x\n",
1930 ictl_ctx
[0], ictl_ctx
[1]);
1931 return CC_TRB_ERROR
;
1934 xhci_dma_read_u32s(xhci
, ictx
+32, slot_ctx
, sizeof(slot_ctx
));
1935 xhci_dma_read_u32s(xhci
, ictx
+64, ep0_ctx
, sizeof(ep0_ctx
));
1937 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
1938 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
1940 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
1941 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
1943 uport
= xhci_lookup_uport(xhci
, slot_ctx
);
1944 if (uport
== NULL
) {
1945 fprintf(stderr
, "xhci: port not found\n");
1946 return CC_TRB_ERROR
;
1951 fprintf(stderr
, "xhci: port %s not connected\n", uport
->path
);
1952 return CC_USB_TRANSACTION_ERROR
;
1955 for (i
= 0; i
< xhci
->numslots
; i
++) {
1956 if (i
== slotid
-1) {
1959 if (xhci
->slots
[i
].uport
== uport
) {
1960 fprintf(stderr
, "xhci: port %s already assigned to slot %d\n",
1962 return CC_TRB_ERROR
;
1966 slot
= &xhci
->slots
[slotid
-1];
1967 slot
->uport
= uport
;
1971 slot_ctx
[3] = SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
1974 slot
->devaddr
= xhci
->devaddr
++;
1975 slot_ctx
[3] = (SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
) | slot
->devaddr
;
1976 DPRINTF("xhci: device address is %d\n", slot
->devaddr
);
1977 usb_device_reset(dev
);
1978 usb_packet_setup(&p
, USB_TOKEN_OUT
,
1979 usb_ep_get(dev
, USB_TOKEN_OUT
, 0),
1981 usb_device_handle_control(dev
, &p
,
1982 DeviceOutRequest
| USB_REQ_SET_ADDRESS
,
1983 slot
->devaddr
, 0, 0, NULL
);
1984 assert(p
.status
!= USB_RET_ASYNC
);
1987 res
= xhci_enable_ep(xhci
, slotid
, 1, octx
+32, ep0_ctx
);
1989 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1990 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
1991 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
1992 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
1994 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
1995 xhci_dma_write_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2001 static TRBCCode
xhci_configure_slot(XHCIState
*xhci
, unsigned int slotid
,
2002 uint64_t pictx
, bool dc
)
2004 dma_addr_t ictx
, octx
;
2005 uint32_t ictl_ctx
[2];
2006 uint32_t slot_ctx
[4];
2007 uint32_t islot_ctx
[4];
2012 trace_usb_xhci_slot_configure(slotid
);
2013 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2015 ictx
= xhci_mask64(pictx
);
2016 octx
= xhci
->slots
[slotid
-1].ctx
;
2018 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2019 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2022 for (i
= 2; i
<= 31; i
++) {
2023 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2024 xhci_disable_ep(xhci
, slotid
, i
);
2028 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2029 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2030 slot_ctx
[3] |= SLOT_ADDRESSED
<< SLOT_STATE_SHIFT
;
2031 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2032 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2033 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2038 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2040 if ((ictl_ctx
[0] & 0x3) != 0x0 || (ictl_ctx
[1] & 0x3) != 0x1) {
2041 fprintf(stderr
, "xhci: invalid input context control %08x %08x\n",
2042 ictl_ctx
[0], ictl_ctx
[1]);
2043 return CC_TRB_ERROR
;
2046 xhci_dma_read_u32s(xhci
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
2047 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2049 if (SLOT_STATE(slot_ctx
[3]) < SLOT_ADDRESSED
) {
2050 fprintf(stderr
, "xhci: invalid slot state %08x\n", slot_ctx
[3]);
2051 return CC_CONTEXT_STATE_ERROR
;
2054 for (i
= 2; i
<= 31; i
++) {
2055 if (ictl_ctx
[0] & (1<<i
)) {
2056 xhci_disable_ep(xhci
, slotid
, i
);
2058 if (ictl_ctx
[1] & (1<<i
)) {
2059 xhci_dma_read_u32s(xhci
, ictx
+32+(32*i
), ep_ctx
, sizeof(ep_ctx
));
2060 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
2061 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
2062 ep_ctx
[3], ep_ctx
[4]);
2063 xhci_disable_ep(xhci
, slotid
, i
);
2064 res
= xhci_enable_ep(xhci
, slotid
, i
, octx
+(32*i
), ep_ctx
);
2065 if (res
!= CC_SUCCESS
) {
2068 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
2069 i
/2, i
%2, ep_ctx
[0], ep_ctx
[1], ep_ctx
[2],
2070 ep_ctx
[3], ep_ctx
[4]);
2071 xhci_dma_write_u32s(xhci
, octx
+(32*i
), ep_ctx
, sizeof(ep_ctx
));
2075 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2076 slot_ctx
[3] |= SLOT_CONFIGURED
<< SLOT_STATE_SHIFT
;
2077 slot_ctx
[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK
<< SLOT_CONTEXT_ENTRIES_SHIFT
);
2078 slot_ctx
[0] |= islot_ctx
[0] & (SLOT_CONTEXT_ENTRIES_MASK
<<
2079 SLOT_CONTEXT_ENTRIES_SHIFT
);
2080 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2081 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2083 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2089 static TRBCCode
xhci_evaluate_slot(XHCIState
*xhci
, unsigned int slotid
,
2092 dma_addr_t ictx
, octx
;
2093 uint32_t ictl_ctx
[2];
2094 uint32_t iep0_ctx
[5];
2095 uint32_t ep0_ctx
[5];
2096 uint32_t islot_ctx
[4];
2097 uint32_t slot_ctx
[4];
2099 trace_usb_xhci_slot_evaluate(slotid
);
2100 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2102 ictx
= xhci_mask64(pictx
);
2103 octx
= xhci
->slots
[slotid
-1].ctx
;
2105 DPRINTF("xhci: input context at "DMA_ADDR_FMT
"\n", ictx
);
2106 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2108 xhci_dma_read_u32s(xhci
, ictx
, ictl_ctx
, sizeof(ictl_ctx
));
2110 if (ictl_ctx
[0] != 0x0 || ictl_ctx
[1] & ~0x3) {
2111 fprintf(stderr
, "xhci: invalid input context control %08x %08x\n",
2112 ictl_ctx
[0], ictl_ctx
[1]);
2113 return CC_TRB_ERROR
;
2116 if (ictl_ctx
[1] & 0x1) {
2117 xhci_dma_read_u32s(xhci
, ictx
+32, islot_ctx
, sizeof(islot_ctx
));
2119 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2120 islot_ctx
[0], islot_ctx
[1], islot_ctx
[2], islot_ctx
[3]);
2122 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2124 slot_ctx
[1] &= ~0xFFFF; /* max exit latency */
2125 slot_ctx
[1] |= islot_ctx
[1] & 0xFFFF;
2126 slot_ctx
[2] &= ~0xFF00000; /* interrupter target */
2127 slot_ctx
[2] |= islot_ctx
[2] & 0xFF000000;
2129 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2130 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2132 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2135 if (ictl_ctx
[1] & 0x2) {
2136 xhci_dma_read_u32s(xhci
, ictx
+64, iep0_ctx
, sizeof(iep0_ctx
));
2138 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2139 iep0_ctx
[0], iep0_ctx
[1], iep0_ctx
[2],
2140 iep0_ctx
[3], iep0_ctx
[4]);
2142 xhci_dma_read_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2144 ep0_ctx
[1] &= ~0xFFFF0000; /* max packet size*/
2145 ep0_ctx
[1] |= iep0_ctx
[1] & 0xFFFF0000;
2147 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2148 ep0_ctx
[0], ep0_ctx
[1], ep0_ctx
[2], ep0_ctx
[3], ep0_ctx
[4]);
2150 xhci_dma_write_u32s(xhci
, octx
+32, ep0_ctx
, sizeof(ep0_ctx
));
2156 static TRBCCode
xhci_reset_slot(XHCIState
*xhci
, unsigned int slotid
)
2158 uint32_t slot_ctx
[4];
2162 trace_usb_xhci_slot_reset(slotid
);
2163 assert(slotid
>= 1 && slotid
<= xhci
->numslots
);
2165 octx
= xhci
->slots
[slotid
-1].ctx
;
2167 DPRINTF("xhci: output context at "DMA_ADDR_FMT
"\n", octx
);
2169 for (i
= 2; i
<= 31; i
++) {
2170 if (xhci
->slots
[slotid
-1].eps
[i
-1]) {
2171 xhci_disable_ep(xhci
, slotid
, i
);
2175 xhci_dma_read_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2176 slot_ctx
[3] &= ~(SLOT_STATE_MASK
<< SLOT_STATE_SHIFT
);
2177 slot_ctx
[3] |= SLOT_DEFAULT
<< SLOT_STATE_SHIFT
;
2178 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2179 slot_ctx
[0], slot_ctx
[1], slot_ctx
[2], slot_ctx
[3]);
2180 xhci_dma_write_u32s(xhci
, octx
, slot_ctx
, sizeof(slot_ctx
));
2185 static unsigned int xhci_get_slot(XHCIState
*xhci
, XHCIEvent
*event
, XHCITRB
*trb
)
2187 unsigned int slotid
;
2188 slotid
= (trb
->control
>> TRB_CR_SLOTID_SHIFT
) & TRB_CR_SLOTID_MASK
;
2189 if (slotid
< 1 || slotid
> xhci
->numslots
) {
2190 fprintf(stderr
, "xhci: bad slot id %d\n", slotid
);
2191 event
->ccode
= CC_TRB_ERROR
;
2193 } else if (!xhci
->slots
[slotid
-1].enabled
) {
2194 fprintf(stderr
, "xhci: slot id %d not enabled\n", slotid
);
2195 event
->ccode
= CC_SLOT_NOT_ENABLED_ERROR
;
2201 static TRBCCode
xhci_get_port_bandwidth(XHCIState
*xhci
, uint64_t pctx
)
2204 uint8_t bw_ctx
[xhci
->numports
+1];
2206 DPRINTF("xhci_get_port_bandwidth()\n");
2208 ctx
= xhci_mask64(pctx
);
2210 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT
"\n", ctx
);
2212 /* TODO: actually implement real values here */
2214 memset(&bw_ctx
[1], 80, xhci
->numports
); /* 80% */
2215 pci_dma_write(&xhci
->pci_dev
, ctx
, bw_ctx
, sizeof(bw_ctx
));
2220 static uint32_t rotl(uint32_t v
, unsigned count
)
2223 return (v
<< count
) | (v
>> (32 - count
));
2227 static uint32_t xhci_nec_challenge(uint32_t hi
, uint32_t lo
)
2230 val
= rotl(lo
- 0x49434878, 32 - ((hi
>>8) & 0x1F));
2231 val
+= rotl(lo
+ 0x49434878, hi
& 0x1F);
2232 val
-= rotl(hi
^ 0x49434878, (lo
>> 16) & 0x1F);
2236 static void xhci_via_challenge(XHCIState
*xhci
, uint64_t addr
)
2240 dma_addr_t paddr
= xhci_mask64(addr
);
2242 pci_dma_read(&xhci
->pci_dev
, paddr
, &buf
, 32);
2244 memcpy(obuf
, buf
, sizeof(obuf
));
2246 if ((buf
[0] & 0xff) == 2) {
2247 obuf
[0] = 0x49932000 + 0x54dc200 * buf
[2] + 0x7429b578 * buf
[3];
2248 obuf
[0] |= (buf
[2] * buf
[3]) & 0xff;
2249 obuf
[1] = 0x0132bb37 + 0xe89 * buf
[2] + 0xf09 * buf
[3];
2250 obuf
[2] = 0x0066c2e9 + 0x2091 * buf
[2] + 0x19bd * buf
[3];
2251 obuf
[3] = 0xd5281342 + 0x2cc9691 * buf
[2] + 0x2367662 * buf
[3];
2252 obuf
[4] = 0x0123c75c + 0x1595 * buf
[2] + 0x19ec * buf
[3];
2253 obuf
[5] = 0x00f695de + 0x26fd * buf
[2] + 0x3e9 * buf
[3];
2254 obuf
[6] = obuf
[2] ^ obuf
[3] ^ 0x29472956;
2255 obuf
[7] = obuf
[2] ^ obuf
[3] ^ 0x65866593;
2258 pci_dma_write(&xhci
->pci_dev
, paddr
, &obuf
, 32);
2261 static void xhci_process_commands(XHCIState
*xhci
)
2265 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_SUCCESS
};
2267 unsigned int i
, slotid
= 0;
2269 DPRINTF("xhci_process_commands()\n");
2270 if (!xhci_running(xhci
)) {
2271 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2275 xhci
->crcr_low
|= CRCR_CRR
;
2277 while ((type
= xhci_ring_fetch(xhci
, &xhci
->cmd_ring
, &trb
, &addr
))) {
2280 case CR_ENABLE_SLOT
:
2281 for (i
= 0; i
< xhci
->numslots
; i
++) {
2282 if (!xhci
->slots
[i
].enabled
) {
2286 if (i
>= xhci
->numslots
) {
2287 fprintf(stderr
, "xhci: no device slots available\n");
2288 event
.ccode
= CC_NO_SLOTS_ERROR
;
2291 event
.ccode
= xhci_enable_slot(xhci
, slotid
);
2294 case CR_DISABLE_SLOT
:
2295 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2297 event
.ccode
= xhci_disable_slot(xhci
, slotid
);
2300 case CR_ADDRESS_DEVICE
:
2301 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2303 event
.ccode
= xhci_address_slot(xhci
, slotid
, trb
.parameter
,
2304 trb
.control
& TRB_CR_BSR
);
2307 case CR_CONFIGURE_ENDPOINT
:
2308 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2310 event
.ccode
= xhci_configure_slot(xhci
, slotid
, trb
.parameter
,
2311 trb
.control
& TRB_CR_DC
);
2314 case CR_EVALUATE_CONTEXT
:
2315 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2317 event
.ccode
= xhci_evaluate_slot(xhci
, slotid
, trb
.parameter
);
2320 case CR_STOP_ENDPOINT
:
2321 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2323 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2325 event
.ccode
= xhci_stop_ep(xhci
, slotid
, epid
);
2328 case CR_RESET_ENDPOINT
:
2329 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2331 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2333 event
.ccode
= xhci_reset_ep(xhci
, slotid
, epid
);
2336 case CR_SET_TR_DEQUEUE
:
2337 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2339 unsigned int epid
= (trb
.control
>> TRB_CR_EPID_SHIFT
)
2341 event
.ccode
= xhci_set_ep_dequeue(xhci
, slotid
, epid
,
2345 case CR_RESET_DEVICE
:
2346 slotid
= xhci_get_slot(xhci
, &event
, &trb
);
2348 event
.ccode
= xhci_reset_slot(xhci
, slotid
);
2351 case CR_GET_PORT_BANDWIDTH
:
2352 event
.ccode
= xhci_get_port_bandwidth(xhci
, trb
.parameter
);
2354 case CR_VENDOR_VIA_CHALLENGE_RESPONSE
:
2355 xhci_via_challenge(xhci
, trb
.parameter
);
2357 case CR_VENDOR_NEC_FIRMWARE_REVISION
:
2358 event
.type
= 48; /* NEC reply */
2359 event
.length
= 0x3025;
2361 case CR_VENDOR_NEC_CHALLENGE_RESPONSE
:
2363 uint32_t chi
= trb
.parameter
>> 32;
2364 uint32_t clo
= trb
.parameter
;
2365 uint32_t val
= xhci_nec_challenge(chi
, clo
);
2366 event
.length
= val
& 0xFFFF;
2367 event
.epid
= val
>> 16;
2369 event
.type
= 48; /* NEC reply */
2373 fprintf(stderr
, "xhci: unimplemented command %d\n", type
);
2374 event
.ccode
= CC_TRB_ERROR
;
2377 event
.slotid
= slotid
;
2378 xhci_event(xhci
, &event
, 0);
2382 static bool xhci_port_have_device(XHCIPort
*port
)
2384 if (!port
->uport
->dev
|| !port
->uport
->dev
->attached
) {
2385 return false; /* no device present */
2387 if (!((1 << port
->uport
->dev
->speed
) & port
->speedmask
)) {
2388 return false; /* speed mismatch */
2393 static void xhci_port_notify(XHCIPort
*port
, uint32_t bits
)
2395 XHCIEvent ev
= { ER_PORT_STATUS_CHANGE
, CC_SUCCESS
,
2396 port
->portnr
<< 24 };
2398 if ((port
->portsc
& bits
) == bits
) {
2401 port
->portsc
|= bits
;
2402 if (!xhci_running(port
->xhci
)) {
2405 xhci_event(port
->xhci
, &ev
, 0);
2408 static void xhci_port_update(XHCIPort
*port
, int is_detach
)
2410 uint32_t pls
= PLS_RX_DETECT
;
2412 port
->portsc
= PORTSC_PP
;
2413 if (!is_detach
&& xhci_port_have_device(port
)) {
2414 port
->portsc
|= PORTSC_CCS
;
2415 switch (port
->uport
->dev
->speed
) {
2417 port
->portsc
|= PORTSC_SPEED_LOW
;
2420 case USB_SPEED_FULL
:
2421 port
->portsc
|= PORTSC_SPEED_FULL
;
2424 case USB_SPEED_HIGH
:
2425 port
->portsc
|= PORTSC_SPEED_HIGH
;
2428 case USB_SPEED_SUPER
:
2429 port
->portsc
|= PORTSC_SPEED_SUPER
;
2430 port
->portsc
|= PORTSC_PED
;
2435 set_field(&port
->portsc
, pls
, PORTSC_PLS
);
2436 trace_usb_xhci_port_link(port
->portnr
, pls
);
2437 xhci_port_notify(port
, PORTSC_CSC
);
2440 static void xhci_port_reset(XHCIPort
*port
)
2442 trace_usb_xhci_port_reset(port
->portnr
);
2444 if (!xhci_port_have_device(port
)) {
2448 usb_device_reset(port
->uport
->dev
);
2450 switch (port
->uport
->dev
->speed
) {
2452 case USB_SPEED_FULL
:
2453 case USB_SPEED_HIGH
:
2454 set_field(&port
->portsc
, PLS_U0
, PORTSC_PLS
);
2455 trace_usb_xhci_port_link(port
->portnr
, PLS_U0
);
2456 port
->portsc
|= PORTSC_PED
;
2460 port
->portsc
&= ~PORTSC_PR
;
2461 xhci_port_notify(port
, PORTSC_PRC
);
2464 static void xhci_reset(DeviceState
*dev
)
2466 XHCIState
*xhci
= DO_UPCAST(XHCIState
, pci_dev
.qdev
, dev
);
2469 trace_usb_xhci_reset();
2470 if (!(xhci
->usbsts
& USBSTS_HCH
)) {
2471 fprintf(stderr
, "xhci: reset while running!\n");
2475 xhci
->usbsts
= USBSTS_HCH
;
2478 xhci
->crcr_high
= 0;
2479 xhci
->dcbaap_low
= 0;
2480 xhci
->dcbaap_high
= 0;
2484 for (i
= 0; i
< xhci
->numslots
; i
++) {
2485 xhci_disable_slot(xhci
, i
+1);
2488 for (i
= 0; i
< xhci
->numports
; i
++) {
2489 xhci_port_update(xhci
->ports
+ i
, 0);
2492 for (i
= 0; i
< xhci
->numintrs
; i
++) {
2493 xhci
->intr
[i
].iman
= 0;
2494 xhci
->intr
[i
].imod
= 0;
2495 xhci
->intr
[i
].erstsz
= 0;
2496 xhci
->intr
[i
].erstba_low
= 0;
2497 xhci
->intr
[i
].erstba_high
= 0;
2498 xhci
->intr
[i
].erdp_low
= 0;
2499 xhci
->intr
[i
].erdp_high
= 0;
2500 xhci
->intr
[i
].msix_used
= 0;
2502 xhci
->intr
[i
].er_ep_idx
= 0;
2503 xhci
->intr
[i
].er_pcs
= 1;
2504 xhci
->intr
[i
].er_full
= 0;
2505 xhci
->intr
[i
].ev_buffer_put
= 0;
2506 xhci
->intr
[i
].ev_buffer_get
= 0;
2509 xhci
->mfindex_start
= qemu_get_clock_ns(vm_clock
);
2510 xhci_mfwrap_update(xhci
);
2513 static uint64_t xhci_cap_read(void *ptr
, hwaddr reg
, unsigned size
)
2515 XHCIState
*xhci
= ptr
;
2519 case 0x00: /* HCIVERSION, CAPLENGTH */
2520 ret
= 0x01000000 | LEN_CAP
;
2522 case 0x04: /* HCSPARAMS 1 */
2523 ret
= ((xhci
->numports_2
+xhci
->numports_3
)<<24)
2524 | (xhci
->numintrs
<<8) | xhci
->numslots
;
2526 case 0x08: /* HCSPARAMS 2 */
2529 case 0x0c: /* HCSPARAMS 3 */
2532 case 0x10: /* HCCPARAMS */
2533 if (sizeof(dma_addr_t
) == 4) {
2539 case 0x14: /* DBOFF */
2542 case 0x18: /* RTSOFF */
2546 /* extended capabilities */
2547 case 0x20: /* Supported Protocol:00 */
2548 ret
= 0x02000402; /* USB 2.0 */
2550 case 0x24: /* Supported Protocol:04 */
2551 ret
= 0x20425355; /* "USB " */
2553 case 0x28: /* Supported Protocol:08 */
2554 ret
= 0x00000001 | (xhci
->numports_2
<<8);
2556 case 0x2c: /* Supported Protocol:0c */
2557 ret
= 0x00000000; /* reserved */
2559 case 0x30: /* Supported Protocol:00 */
2560 ret
= 0x03000002; /* USB 3.0 */
2562 case 0x34: /* Supported Protocol:04 */
2563 ret
= 0x20425355; /* "USB " */
2565 case 0x38: /* Supported Protocol:08 */
2566 ret
= 0x00000000 | (xhci
->numports_2
+1) | (xhci
->numports_3
<<8);
2568 case 0x3c: /* Supported Protocol:0c */
2569 ret
= 0x00000000; /* reserved */
2572 fprintf(stderr
, "xhci_cap_read: reg %d unimplemented\n", (int)reg
);
2576 trace_usb_xhci_cap_read(reg
, ret
);
2580 static uint64_t xhci_port_read(void *ptr
, hwaddr reg
, unsigned size
)
2582 XHCIPort
*port
= ptr
;
2586 case 0x00: /* PORTSC */
2589 case 0x04: /* PORTPMSC */
2590 case 0x08: /* PORTLI */
2593 case 0x0c: /* reserved */
2595 fprintf(stderr
, "xhci_port_read (port %d): reg 0x%x unimplemented\n",
2596 port
->portnr
, (uint32_t)reg
);
2600 trace_usb_xhci_port_read(port
->portnr
, reg
, ret
);
2604 static void xhci_port_write(void *ptr
, hwaddr reg
,
2605 uint64_t val
, unsigned size
)
2607 XHCIPort
*port
= ptr
;
2610 trace_usb_xhci_port_write(port
->portnr
, reg
, val
);
2613 case 0x00: /* PORTSC */
2614 portsc
= port
->portsc
;
2615 /* write-1-to-clear bits*/
2616 portsc
&= ~(val
& (PORTSC_CSC
|PORTSC_PEC
|PORTSC_WRC
|PORTSC_OCC
|
2617 PORTSC_PRC
|PORTSC_PLC
|PORTSC_CEC
));
2618 if (val
& PORTSC_LWS
) {
2619 /* overwrite PLS only when LWS=1 */
2620 uint32_t pls
= get_field(val
, PORTSC_PLS
);
2621 set_field(&portsc
, pls
, PORTSC_PLS
);
2622 trace_usb_xhci_port_link(port
->portnr
, pls
);
2624 /* read/write bits */
2625 portsc
&= ~(PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
);
2626 portsc
|= (val
& (PORTSC_PP
|PORTSC_WCE
|PORTSC_WDE
|PORTSC_WOE
));
2627 port
->portsc
= portsc
;
2628 /* write-1-to-start bits */
2629 if (val
& PORTSC_PR
) {
2630 xhci_port_reset(port
);
2633 case 0x04: /* PORTPMSC */
2634 case 0x08: /* PORTLI */
2636 fprintf(stderr
, "xhci_port_write (port %d): reg 0x%x unimplemented\n",
2637 port
->portnr
, (uint32_t)reg
);
2641 static uint64_t xhci_oper_read(void *ptr
, hwaddr reg
, unsigned size
)
2643 XHCIState
*xhci
= ptr
;
2647 case 0x00: /* USBCMD */
2650 case 0x04: /* USBSTS */
2653 case 0x08: /* PAGESIZE */
2656 case 0x14: /* DNCTRL */
2659 case 0x18: /* CRCR low */
2660 ret
= xhci
->crcr_low
& ~0xe;
2662 case 0x1c: /* CRCR high */
2663 ret
= xhci
->crcr_high
;
2665 case 0x30: /* DCBAAP low */
2666 ret
= xhci
->dcbaap_low
;
2668 case 0x34: /* DCBAAP high */
2669 ret
= xhci
->dcbaap_high
;
2671 case 0x38: /* CONFIG */
2675 fprintf(stderr
, "xhci_oper_read: reg 0x%x unimplemented\n", (int)reg
);
2679 trace_usb_xhci_oper_read(reg
, ret
);
2683 static void xhci_oper_write(void *ptr
, hwaddr reg
,
2684 uint64_t val
, unsigned size
)
2686 XHCIState
*xhci
= ptr
;
2688 trace_usb_xhci_oper_write(reg
, val
);
2691 case 0x00: /* USBCMD */
2692 if ((val
& USBCMD_RS
) && !(xhci
->usbcmd
& USBCMD_RS
)) {
2694 } else if (!(val
& USBCMD_RS
) && (xhci
->usbcmd
& USBCMD_RS
)) {
2697 xhci
->usbcmd
= val
& 0xc0f;
2698 xhci_mfwrap_update(xhci
);
2699 if (val
& USBCMD_HCRST
) {
2700 xhci_reset(&xhci
->pci_dev
.qdev
);
2702 xhci_intx_update(xhci
);
2705 case 0x04: /* USBSTS */
2706 /* these bits are write-1-to-clear */
2707 xhci
->usbsts
&= ~(val
& (USBSTS_HSE
|USBSTS_EINT
|USBSTS_PCD
|USBSTS_SRE
));
2708 xhci_intx_update(xhci
);
2711 case 0x14: /* DNCTRL */
2712 xhci
->dnctrl
= val
& 0xffff;
2714 case 0x18: /* CRCR low */
2715 xhci
->crcr_low
= (val
& 0xffffffcf) | (xhci
->crcr_low
& CRCR_CRR
);
2717 case 0x1c: /* CRCR high */
2718 xhci
->crcr_high
= val
;
2719 if (xhci
->crcr_low
& (CRCR_CA
|CRCR_CS
) && (xhci
->crcr_low
& CRCR_CRR
)) {
2720 XHCIEvent event
= {ER_COMMAND_COMPLETE
, CC_COMMAND_RING_STOPPED
};
2721 xhci
->crcr_low
&= ~CRCR_CRR
;
2722 xhci_event(xhci
, &event
, 0);
2723 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci
->crcr_low
);
2725 dma_addr_t base
= xhci_addr64(xhci
->crcr_low
& ~0x3f, val
);
2726 xhci_ring_init(xhci
, &xhci
->cmd_ring
, base
);
2728 xhci
->crcr_low
&= ~(CRCR_CA
| CRCR_CS
);
2730 case 0x30: /* DCBAAP low */
2731 xhci
->dcbaap_low
= val
& 0xffffffc0;
2733 case 0x34: /* DCBAAP high */
2734 xhci
->dcbaap_high
= val
;
2736 case 0x38: /* CONFIG */
2737 xhci
->config
= val
& 0xff;
2740 fprintf(stderr
, "xhci_oper_write: reg 0x%x unimplemented\n", (int)reg
);
2744 static uint64_t xhci_runtime_read(void *ptr
, hwaddr reg
,
2747 XHCIState
*xhci
= ptr
;
2752 case 0x00: /* MFINDEX */
2753 ret
= xhci_mfindex_get(xhci
) & 0x3fff;
2756 fprintf(stderr
, "xhci_runtime_read: reg 0x%x unimplemented\n",
2761 int v
= (reg
- 0x20) / 0x20;
2762 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
2763 switch (reg
& 0x1f) {
2764 case 0x00: /* IMAN */
2767 case 0x04: /* IMOD */
2770 case 0x08: /* ERSTSZ */
2773 case 0x10: /* ERSTBA low */
2774 ret
= intr
->erstba_low
;
2776 case 0x14: /* ERSTBA high */
2777 ret
= intr
->erstba_high
;
2779 case 0x18: /* ERDP low */
2780 ret
= intr
->erdp_low
;
2782 case 0x1c: /* ERDP high */
2783 ret
= intr
->erdp_high
;
2788 trace_usb_xhci_runtime_read(reg
, ret
);
2792 static void xhci_runtime_write(void *ptr
, hwaddr reg
,
2793 uint64_t val
, unsigned size
)
2795 XHCIState
*xhci
= ptr
;
2796 int v
= (reg
- 0x20) / 0x20;
2797 XHCIInterrupter
*intr
= &xhci
->intr
[v
];
2798 trace_usb_xhci_runtime_write(reg
, val
);
2801 fprintf(stderr
, "%s: reg 0x%x unimplemented\n", __func__
, (int)reg
);
2805 switch (reg
& 0x1f) {
2806 case 0x00: /* IMAN */
2807 if (val
& IMAN_IP
) {
2808 intr
->iman
&= ~IMAN_IP
;
2810 intr
->iman
&= ~IMAN_IE
;
2811 intr
->iman
|= val
& IMAN_IE
;
2813 xhci_intx_update(xhci
);
2815 xhci_msix_update(xhci
, v
);
2817 case 0x04: /* IMOD */
2820 case 0x08: /* ERSTSZ */
2821 intr
->erstsz
= val
& 0xffff;
2823 case 0x10: /* ERSTBA low */
2824 /* XXX NEC driver bug: it doesn't align this to 64 bytes
2825 intr->erstba_low = val & 0xffffffc0; */
2826 intr
->erstba_low
= val
& 0xfffffff0;
2828 case 0x14: /* ERSTBA high */
2829 intr
->erstba_high
= val
;
2830 xhci_er_reset(xhci
, v
);
2832 case 0x18: /* ERDP low */
2833 if (val
& ERDP_EHB
) {
2834 intr
->erdp_low
&= ~ERDP_EHB
;
2836 intr
->erdp_low
= (val
& ~ERDP_EHB
) | (intr
->erdp_low
& ERDP_EHB
);
2838 case 0x1c: /* ERDP high */
2839 intr
->erdp_high
= val
;
2840 xhci_events_update(xhci
, v
);
2843 fprintf(stderr
, "xhci_oper_write: reg 0x%x unimplemented\n",
2848 static uint64_t xhci_doorbell_read(void *ptr
, hwaddr reg
,
2851 /* doorbells always read as 0 */
2852 trace_usb_xhci_doorbell_read(reg
, 0);
2856 static void xhci_doorbell_write(void *ptr
, hwaddr reg
,
2857 uint64_t val
, unsigned size
)
2859 XHCIState
*xhci
= ptr
;
2861 trace_usb_xhci_doorbell_write(reg
, val
);
2863 if (!xhci_running(xhci
)) {
2864 fprintf(stderr
, "xhci: wrote doorbell while xHC stopped or paused\n");
2872 xhci_process_commands(xhci
);
2874 fprintf(stderr
, "xhci: bad doorbell 0 write: 0x%x\n",
2878 if (reg
> xhci
->numslots
) {
2879 fprintf(stderr
, "xhci: bad doorbell %d\n", (int)reg
);
2880 } else if (val
> 31) {
2881 fprintf(stderr
, "xhci: bad doorbell %d write: 0x%x\n",
2882 (int)reg
, (uint32_t)val
);
2884 xhci_kick_ep(xhci
, reg
, val
);
2889 static const MemoryRegionOps xhci_cap_ops
= {
2890 .read
= xhci_cap_read
,
2891 .valid
.min_access_size
= 1,
2892 .valid
.max_access_size
= 4,
2893 .impl
.min_access_size
= 4,
2894 .impl
.max_access_size
= 4,
2895 .endianness
= DEVICE_LITTLE_ENDIAN
,
2898 static const MemoryRegionOps xhci_oper_ops
= {
2899 .read
= xhci_oper_read
,
2900 .write
= xhci_oper_write
,
2901 .valid
.min_access_size
= 4,
2902 .valid
.max_access_size
= 4,
2903 .endianness
= DEVICE_LITTLE_ENDIAN
,
2906 static const MemoryRegionOps xhci_port_ops
= {
2907 .read
= xhci_port_read
,
2908 .write
= xhci_port_write
,
2909 .valid
.min_access_size
= 4,
2910 .valid
.max_access_size
= 4,
2911 .endianness
= DEVICE_LITTLE_ENDIAN
,
2914 static const MemoryRegionOps xhci_runtime_ops
= {
2915 .read
= xhci_runtime_read
,
2916 .write
= xhci_runtime_write
,
2917 .valid
.min_access_size
= 4,
2918 .valid
.max_access_size
= 4,
2919 .endianness
= DEVICE_LITTLE_ENDIAN
,
2922 static const MemoryRegionOps xhci_doorbell_ops
= {
2923 .read
= xhci_doorbell_read
,
2924 .write
= xhci_doorbell_write
,
2925 .valid
.min_access_size
= 4,
2926 .valid
.max_access_size
= 4,
2927 .endianness
= DEVICE_LITTLE_ENDIAN
,
2930 static void xhci_attach(USBPort
*usbport
)
2932 XHCIState
*xhci
= usbport
->opaque
;
2933 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
2935 xhci_port_update(port
, 0);
2938 static void xhci_detach(USBPort
*usbport
)
2940 XHCIState
*xhci
= usbport
->opaque
;
2941 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
2943 xhci_port_update(port
, 1);
2946 static void xhci_wakeup(USBPort
*usbport
)
2948 XHCIState
*xhci
= usbport
->opaque
;
2949 XHCIPort
*port
= xhci_lookup_port(xhci
, usbport
);
2951 if (get_field(port
->portsc
, PORTSC_PLS
) != PLS_U3
) {
2954 set_field(&port
->portsc
, PLS_RESUME
, PORTSC_PLS
);
2955 xhci_port_notify(port
, PORTSC_PLC
);
2958 static void xhci_complete(USBPort
*port
, USBPacket
*packet
)
2960 XHCITransfer
*xfer
= container_of(packet
, XHCITransfer
, packet
);
2962 if (packet
->status
== USB_RET_REMOVE_FROM_QUEUE
) {
2963 xhci_ep_nuke_one_xfer(xfer
);
2966 xhci_complete_packet(xfer
);
2967 xhci_kick_ep(xfer
->xhci
, xfer
->slotid
, xfer
->epid
);
2970 static void xhci_child_detach(USBPort
*uport
, USBDevice
*child
)
2972 USBBus
*bus
= usb_bus_from_device(child
);
2973 XHCIState
*xhci
= container_of(bus
, XHCIState
, bus
);
2976 for (i
= 0; i
< xhci
->numslots
; i
++) {
2977 if (xhci
->slots
[i
].uport
== uport
) {
2978 xhci
->slots
[i
].uport
= NULL
;
2983 static USBPortOps xhci_uport_ops
= {
2984 .attach
= xhci_attach
,
2985 .detach
= xhci_detach
,
2986 .wakeup
= xhci_wakeup
,
2987 .complete
= xhci_complete
,
2988 .child_detach
= xhci_child_detach
,
2991 static int xhci_find_slotid(XHCIState
*xhci
, USBDevice
*dev
)
2996 for (slotid
= 1; slotid
<= xhci
->numslots
; slotid
++) {
2997 slot
= &xhci
->slots
[slotid
-1];
2998 if (slot
->devaddr
== dev
->addr
) {
3005 static int xhci_find_epid(USBEndpoint
*ep
)
3010 if (ep
->pid
== USB_TOKEN_IN
) {
3011 return ep
->nr
* 2 + 1;
3017 static void xhci_wakeup_endpoint(USBBus
*bus
, USBEndpoint
*ep
)
3019 XHCIState
*xhci
= container_of(bus
, XHCIState
, bus
);
3022 DPRINTF("%s\n", __func__
);
3023 slotid
= xhci_find_slotid(xhci
, ep
->dev
);
3024 if (slotid
== 0 || !xhci
->slots
[slotid
-1].enabled
) {
3025 DPRINTF("%s: oops, no slot for dev %d\n", __func__
, ep
->dev
->addr
);
3028 xhci_kick_ep(xhci
, slotid
, xhci_find_epid(ep
));
3031 static USBBusOps xhci_bus_ops
= {
3032 .wakeup_endpoint
= xhci_wakeup_endpoint
,
3035 static void usb_xhci_init(XHCIState
*xhci
, DeviceState
*dev
)
3038 int i
, usbports
, speedmask
;
3040 xhci
->usbsts
= USBSTS_HCH
;
3042 if (xhci
->numports_2
> MAXPORTS_2
) {
3043 xhci
->numports_2
= MAXPORTS_2
;
3045 if (xhci
->numports_3
> MAXPORTS_3
) {
3046 xhci
->numports_3
= MAXPORTS_3
;
3048 usbports
= MAX(xhci
->numports_2
, xhci
->numports_3
);
3049 xhci
->numports
= xhci
->numports_2
+ xhci
->numports_3
;
3051 usb_bus_new(&xhci
->bus
, &xhci_bus_ops
, &xhci
->pci_dev
.qdev
);
3053 for (i
= 0; i
< usbports
; i
++) {
3055 if (i
< xhci
->numports_2
) {
3056 port
= &xhci
->ports
[i
];
3057 port
->portnr
= i
+ 1;
3058 port
->uport
= &xhci
->uports
[i
];
3060 USB_SPEED_MASK_LOW
|
3061 USB_SPEED_MASK_FULL
|
3062 USB_SPEED_MASK_HIGH
;
3063 snprintf(port
->name
, sizeof(port
->name
), "usb2 port #%d", i
+1);
3064 speedmask
|= port
->speedmask
;
3066 if (i
< xhci
->numports_3
) {
3067 port
= &xhci
->ports
[i
+ xhci
->numports_2
];
3068 port
->portnr
= i
+ 1 + xhci
->numports_2
;
3069 port
->uport
= &xhci
->uports
[i
];
3070 port
->speedmask
= USB_SPEED_MASK_SUPER
;
3071 snprintf(port
->name
, sizeof(port
->name
), "usb3 port #%d", i
+1);
3072 speedmask
|= port
->speedmask
;
3074 usb_register_port(&xhci
->bus
, &xhci
->uports
[i
], xhci
, i
,
3075 &xhci_uport_ops
, speedmask
);
3079 static int usb_xhci_initfn(struct PCIDevice
*dev
)
3083 XHCIState
*xhci
= DO_UPCAST(XHCIState
, pci_dev
, dev
);
3085 xhci
->pci_dev
.config
[PCI_CLASS_PROG
] = 0x30; /* xHCI */
3086 xhci
->pci_dev
.config
[PCI_INTERRUPT_PIN
] = 0x01; /* interrupt pin 1 */
3087 xhci
->pci_dev
.config
[PCI_CACHE_LINE_SIZE
] = 0x10;
3088 xhci
->pci_dev
.config
[0x60] = 0x30; /* release number */
3090 usb_xhci_init(xhci
, &dev
->qdev
);
3092 if (xhci
->numintrs
> MAXINTRS
) {
3093 xhci
->numintrs
= MAXINTRS
;
3095 if (xhci
->numintrs
< 1) {
3098 if (xhci
->numslots
> MAXSLOTS
) {
3099 xhci
->numslots
= MAXSLOTS
;
3101 if (xhci
->numslots
< 1) {
3105 xhci
->mfwrap_timer
= qemu_new_timer_ns(vm_clock
, xhci_mfwrap_timer
, xhci
);
3107 xhci
->irq
= xhci
->pci_dev
.irq
[0];
3109 memory_region_init(&xhci
->mem
, "xhci", LEN_REGS
);
3110 memory_region_init_io(&xhci
->mem_cap
, &xhci_cap_ops
, xhci
,
3111 "capabilities", LEN_CAP
);
3112 memory_region_init_io(&xhci
->mem_oper
, &xhci_oper_ops
, xhci
,
3113 "operational", 0x400);
3114 memory_region_init_io(&xhci
->mem_runtime
, &xhci_runtime_ops
, xhci
,
3115 "runtime", LEN_RUNTIME
);
3116 memory_region_init_io(&xhci
->mem_doorbell
, &xhci_doorbell_ops
, xhci
,
3117 "doorbell", LEN_DOORBELL
);
3119 memory_region_add_subregion(&xhci
->mem
, 0, &xhci
->mem_cap
);
3120 memory_region_add_subregion(&xhci
->mem
, OFF_OPER
, &xhci
->mem_oper
);
3121 memory_region_add_subregion(&xhci
->mem
, OFF_RUNTIME
, &xhci
->mem_runtime
);
3122 memory_region_add_subregion(&xhci
->mem
, OFF_DOORBELL
, &xhci
->mem_doorbell
);
3124 for (i
= 0; i
< xhci
->numports
; i
++) {
3125 XHCIPort
*port
= &xhci
->ports
[i
];
3126 uint32_t offset
= OFF_OPER
+ 0x400 + 0x10 * i
;
3128 memory_region_init_io(&port
->mem
, &xhci_port_ops
, port
,
3130 memory_region_add_subregion(&xhci
->mem
, offset
, &port
->mem
);
3133 pci_register_bar(&xhci
->pci_dev
, 0,
3134 PCI_BASE_ADDRESS_SPACE_MEMORY
|PCI_BASE_ADDRESS_MEM_TYPE_64
,
3137 ret
= pcie_cap_init(&xhci
->pci_dev
, 0xa0, PCI_EXP_TYPE_ENDPOINT
, 0);
3140 if (xhci
->flags
& (1 << XHCI_FLAG_USE_MSI
)) {
3141 msi_init(&xhci
->pci_dev
, 0x70, xhci
->numintrs
, true, false);
3143 if (xhci
->flags
& (1 << XHCI_FLAG_USE_MSI_X
)) {
3144 msix_init(&xhci
->pci_dev
, xhci
->numintrs
,
3145 &xhci
->mem
, 0, OFF_MSIX_TABLE
,
3146 &xhci
->mem
, 0, OFF_MSIX_PBA
,
3153 static const VMStateDescription vmstate_xhci
= {
3158 static Property xhci_properties
[] = {
3159 DEFINE_PROP_BIT("msi", XHCIState
, flags
, XHCI_FLAG_USE_MSI
, true),
3160 DEFINE_PROP_BIT("msix", XHCIState
, flags
, XHCI_FLAG_USE_MSI_X
, true),
3161 DEFINE_PROP_UINT32("intrs", XHCIState
, numintrs
, MAXINTRS
),
3162 DEFINE_PROP_UINT32("slots", XHCIState
, numslots
, MAXSLOTS
),
3163 DEFINE_PROP_UINT32("p2", XHCIState
, numports_2
, 4),
3164 DEFINE_PROP_UINT32("p3", XHCIState
, numports_3
, 4),
3165 DEFINE_PROP_END_OF_LIST(),
3168 static void xhci_class_init(ObjectClass
*klass
, void *data
)
3170 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
3171 DeviceClass
*dc
= DEVICE_CLASS(klass
);
3173 dc
->vmsd
= &vmstate_xhci
;
3174 dc
->props
= xhci_properties
;
3175 dc
->reset
= xhci_reset
;
3176 k
->init
= usb_xhci_initfn
;
3177 k
->vendor_id
= PCI_VENDOR_ID_NEC
;
3178 k
->device_id
= PCI_DEVICE_ID_NEC_UPD720200
;
3179 k
->class_id
= PCI_CLASS_SERIAL_USB
;
3185 static const TypeInfo xhci_info
= {
3186 .name
= "nec-usb-xhci",
3187 .parent
= TYPE_PCI_DEVICE
,
3188 .instance_size
= sizeof(XHCIState
),
3189 .class_init
= xhci_class_init
,
3192 static void xhci_register_types(void)
3194 type_register_static(&xhci_info
);
3197 type_init(xhci_register_types
)