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xhci: iso xfer support
[mirror_qemu.git] / hw / usb / hcd-xhci.c
1 /*
2 * USB xHCI controller emulation
3 *
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21 #include "hw/hw.h"
22 #include "qemu-timer.h"
23 #include "hw/usb.h"
24 #include "hw/pci.h"
25 #include "hw/msi.h"
26 #include "trace.h"
27
28 //#define DEBUG_XHCI
29 //#define DEBUG_DATA
30
31 #ifdef DEBUG_XHCI
32 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
33 #else
34 #define DPRINTF(...) do {} while (0)
35 #endif
36 #define FIXME() do { fprintf(stderr, "FIXME %s:%d\n", \
37 __func__, __LINE__); abort(); } while (0)
38
39 #define MAXSLOTS 8
40 #define MAXINTRS 1
41
42 #define USB2_PORTS 4
43 #define USB3_PORTS 4
44
45 #define MAXPORTS (USB2_PORTS+USB3_PORTS)
46
47 #define TD_QUEUE 24
48
49 /* Very pessimistic, let's hope it's enough for all cases */
50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS)
51 /* Do not deliver ER Full events. NEC's driver does some things not bound
52 * to the specs when it gets them */
53 #define ER_FULL_HACK
54
55 #define LEN_CAP 0x40
56 #define OFF_OPER LEN_CAP
57 #define LEN_OPER (0x400 + 0x10 * MAXPORTS)
58 #define OFF_RUNTIME ((OFF_OPER + LEN_OPER + 0x20) & ~0x1f)
59 #define LEN_RUNTIME (0x20 + MAXINTRS * 0x20)
60 #define OFF_DOORBELL (OFF_RUNTIME + LEN_RUNTIME)
61 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
62
63 /* must be power of 2 */
64 #define LEN_REGS 0x2000
65
66 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
67 # error Increase LEN_REGS
68 #endif
69
70 #if MAXINTRS > 1
71 # error TODO: only one interrupter supported
72 #endif
73
74 /* bit definitions */
75 #define USBCMD_RS (1<<0)
76 #define USBCMD_HCRST (1<<1)
77 #define USBCMD_INTE (1<<2)
78 #define USBCMD_HSEE (1<<3)
79 #define USBCMD_LHCRST (1<<7)
80 #define USBCMD_CSS (1<<8)
81 #define USBCMD_CRS (1<<9)
82 #define USBCMD_EWE (1<<10)
83 #define USBCMD_EU3S (1<<11)
84
85 #define USBSTS_HCH (1<<0)
86 #define USBSTS_HSE (1<<2)
87 #define USBSTS_EINT (1<<3)
88 #define USBSTS_PCD (1<<4)
89 #define USBSTS_SSS (1<<8)
90 #define USBSTS_RSS (1<<9)
91 #define USBSTS_SRE (1<<10)
92 #define USBSTS_CNR (1<<11)
93 #define USBSTS_HCE (1<<12)
94
95
96 #define PORTSC_CCS (1<<0)
97 #define PORTSC_PED (1<<1)
98 #define PORTSC_OCA (1<<3)
99 #define PORTSC_PR (1<<4)
100 #define PORTSC_PLS_SHIFT 5
101 #define PORTSC_PLS_MASK 0xf
102 #define PORTSC_PP (1<<9)
103 #define PORTSC_SPEED_SHIFT 10
104 #define PORTSC_SPEED_MASK 0xf
105 #define PORTSC_SPEED_FULL (1<<10)
106 #define PORTSC_SPEED_LOW (2<<10)
107 #define PORTSC_SPEED_HIGH (3<<10)
108 #define PORTSC_SPEED_SUPER (4<<10)
109 #define PORTSC_PIC_SHIFT 14
110 #define PORTSC_PIC_MASK 0x3
111 #define PORTSC_LWS (1<<16)
112 #define PORTSC_CSC (1<<17)
113 #define PORTSC_PEC (1<<18)
114 #define PORTSC_WRC (1<<19)
115 #define PORTSC_OCC (1<<20)
116 #define PORTSC_PRC (1<<21)
117 #define PORTSC_PLC (1<<22)
118 #define PORTSC_CEC (1<<23)
119 #define PORTSC_CAS (1<<24)
120 #define PORTSC_WCE (1<<25)
121 #define PORTSC_WDE (1<<26)
122 #define PORTSC_WOE (1<<27)
123 #define PORTSC_DR (1<<30)
124 #define PORTSC_WPR (1<<31)
125
126 #define CRCR_RCS (1<<0)
127 #define CRCR_CS (1<<1)
128 #define CRCR_CA (1<<2)
129 #define CRCR_CRR (1<<3)
130
131 #define IMAN_IP (1<<0)
132 #define IMAN_IE (1<<1)
133
134 #define ERDP_EHB (1<<3)
135
136 #define TRB_SIZE 16
137 typedef struct XHCITRB {
138 uint64_t parameter;
139 uint32_t status;
140 uint32_t control;
141 dma_addr_t addr;
142 bool ccs;
143 } XHCITRB;
144
145
146 typedef enum TRBType {
147 TRB_RESERVED = 0,
148 TR_NORMAL,
149 TR_SETUP,
150 TR_DATA,
151 TR_STATUS,
152 TR_ISOCH,
153 TR_LINK,
154 TR_EVDATA,
155 TR_NOOP,
156 CR_ENABLE_SLOT,
157 CR_DISABLE_SLOT,
158 CR_ADDRESS_DEVICE,
159 CR_CONFIGURE_ENDPOINT,
160 CR_EVALUATE_CONTEXT,
161 CR_RESET_ENDPOINT,
162 CR_STOP_ENDPOINT,
163 CR_SET_TR_DEQUEUE,
164 CR_RESET_DEVICE,
165 CR_FORCE_EVENT,
166 CR_NEGOTIATE_BW,
167 CR_SET_LATENCY_TOLERANCE,
168 CR_GET_PORT_BANDWIDTH,
169 CR_FORCE_HEADER,
170 CR_NOOP,
171 ER_TRANSFER = 32,
172 ER_COMMAND_COMPLETE,
173 ER_PORT_STATUS_CHANGE,
174 ER_BANDWIDTH_REQUEST,
175 ER_DOORBELL,
176 ER_HOST_CONTROLLER,
177 ER_DEVICE_NOTIFICATION,
178 ER_MFINDEX_WRAP,
179 /* vendor specific bits */
180 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48,
181 CR_VENDOR_NEC_FIRMWARE_REVISION = 49,
182 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50,
183 } TRBType;
184
185 #define CR_LINK TR_LINK
186
187 typedef enum TRBCCode {
188 CC_INVALID = 0,
189 CC_SUCCESS,
190 CC_DATA_BUFFER_ERROR,
191 CC_BABBLE_DETECTED,
192 CC_USB_TRANSACTION_ERROR,
193 CC_TRB_ERROR,
194 CC_STALL_ERROR,
195 CC_RESOURCE_ERROR,
196 CC_BANDWIDTH_ERROR,
197 CC_NO_SLOTS_ERROR,
198 CC_INVALID_STREAM_TYPE_ERROR,
199 CC_SLOT_NOT_ENABLED_ERROR,
200 CC_EP_NOT_ENABLED_ERROR,
201 CC_SHORT_PACKET,
202 CC_RING_UNDERRUN,
203 CC_RING_OVERRUN,
204 CC_VF_ER_FULL,
205 CC_PARAMETER_ERROR,
206 CC_BANDWIDTH_OVERRUN,
207 CC_CONTEXT_STATE_ERROR,
208 CC_NO_PING_RESPONSE_ERROR,
209 CC_EVENT_RING_FULL_ERROR,
210 CC_INCOMPATIBLE_DEVICE_ERROR,
211 CC_MISSED_SERVICE_ERROR,
212 CC_COMMAND_RING_STOPPED,
213 CC_COMMAND_ABORTED,
214 CC_STOPPED,
215 CC_STOPPED_LENGTH_INVALID,
216 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29,
217 CC_ISOCH_BUFFER_OVERRUN = 31,
218 CC_EVENT_LOST_ERROR,
219 CC_UNDEFINED_ERROR,
220 CC_INVALID_STREAM_ID_ERROR,
221 CC_SECONDARY_BANDWIDTH_ERROR,
222 CC_SPLIT_TRANSACTION_ERROR
223 } TRBCCode;
224
225 #define TRB_C (1<<0)
226 #define TRB_TYPE_SHIFT 10
227 #define TRB_TYPE_MASK 0x3f
228 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
229
230 #define TRB_EV_ED (1<<2)
231
232 #define TRB_TR_ENT (1<<1)
233 #define TRB_TR_ISP (1<<2)
234 #define TRB_TR_NS (1<<3)
235 #define TRB_TR_CH (1<<4)
236 #define TRB_TR_IOC (1<<5)
237 #define TRB_TR_IDT (1<<6)
238 #define TRB_TR_TBC_SHIFT 7
239 #define TRB_TR_TBC_MASK 0x3
240 #define TRB_TR_BEI (1<<9)
241 #define TRB_TR_TLBPC_SHIFT 16
242 #define TRB_TR_TLBPC_MASK 0xf
243 #define TRB_TR_FRAMEID_SHIFT 20
244 #define TRB_TR_FRAMEID_MASK 0x7ff
245 #define TRB_TR_SIA (1<<31)
246
247 #define TRB_TR_DIR (1<<16)
248
249 #define TRB_CR_SLOTID_SHIFT 24
250 #define TRB_CR_SLOTID_MASK 0xff
251 #define TRB_CR_EPID_SHIFT 16
252 #define TRB_CR_EPID_MASK 0x1f
253
254 #define TRB_CR_BSR (1<<9)
255 #define TRB_CR_DC (1<<9)
256
257 #define TRB_LK_TC (1<<1)
258
259 #define EP_TYPE_MASK 0x7
260 #define EP_TYPE_SHIFT 3
261
262 #define EP_STATE_MASK 0x7
263 #define EP_DISABLED (0<<0)
264 #define EP_RUNNING (1<<0)
265 #define EP_HALTED (2<<0)
266 #define EP_STOPPED (3<<0)
267 #define EP_ERROR (4<<0)
268
269 #define SLOT_STATE_MASK 0x1f
270 #define SLOT_STATE_SHIFT 27
271 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
272 #define SLOT_ENABLED 0
273 #define SLOT_DEFAULT 1
274 #define SLOT_ADDRESSED 2
275 #define SLOT_CONFIGURED 3
276
277 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
278 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
279
280 typedef enum EPType {
281 ET_INVALID = 0,
282 ET_ISO_OUT,
283 ET_BULK_OUT,
284 ET_INTR_OUT,
285 ET_CONTROL,
286 ET_ISO_IN,
287 ET_BULK_IN,
288 ET_INTR_IN,
289 } EPType;
290
291 typedef struct XHCIRing {
292 dma_addr_t base;
293 dma_addr_t dequeue;
294 bool ccs;
295 } XHCIRing;
296
297 typedef struct XHCIPort {
298 USBPort port;
299 uint32_t portsc;
300 } XHCIPort;
301
302 struct XHCIState;
303 typedef struct XHCIState XHCIState;
304
305 typedef struct XHCITransfer {
306 XHCIState *xhci;
307 USBPacket packet;
308 QEMUSGList sgl;
309 bool running_async;
310 bool running_retry;
311 bool cancelled;
312 bool complete;
313 unsigned int iso_pkts;
314 unsigned int slotid;
315 unsigned int epid;
316 bool in_xfer;
317 bool iso_xfer;
318
319 unsigned int trb_count;
320 unsigned int trb_alloced;
321 XHCITRB *trbs;
322
323 TRBCCode status;
324
325 unsigned int pkts;
326 unsigned int pktsize;
327 unsigned int cur_pkt;
328
329 uint64_t mfindex_kick;
330 } XHCITransfer;
331
332 typedef struct XHCIEPContext {
333 XHCIState *xhci;
334 unsigned int slotid;
335 unsigned int epid;
336
337 XHCIRing ring;
338 unsigned int next_xfer;
339 unsigned int comp_xfer;
340 XHCITransfer transfers[TD_QUEUE];
341 XHCITransfer *retry;
342 EPType type;
343 dma_addr_t pctx;
344 unsigned int max_psize;
345 uint32_t state;
346
347 /* iso xfer scheduling */
348 unsigned int interval;
349 int64_t mfindex_last;
350 QEMUTimer *kick_timer;
351 } XHCIEPContext;
352
353 typedef struct XHCISlot {
354 bool enabled;
355 dma_addr_t ctx;
356 unsigned int port;
357 unsigned int devaddr;
358 XHCIEPContext * eps[31];
359 } XHCISlot;
360
361 typedef struct XHCIEvent {
362 TRBType type;
363 TRBCCode ccode;
364 uint64_t ptr;
365 uint32_t length;
366 uint32_t flags;
367 uint8_t slotid;
368 uint8_t epid;
369 } XHCIEvent;
370
371 struct XHCIState {
372 PCIDevice pci_dev;
373 USBBus bus;
374 qemu_irq irq;
375 MemoryRegion mem;
376 const char *name;
377 uint32_t msi;
378 unsigned int devaddr;
379
380 /* Operational Registers */
381 uint32_t usbcmd;
382 uint32_t usbsts;
383 uint32_t dnctrl;
384 uint32_t crcr_low;
385 uint32_t crcr_high;
386 uint32_t dcbaap_low;
387 uint32_t dcbaap_high;
388 uint32_t config;
389
390 XHCIPort ports[MAXPORTS];
391 XHCISlot slots[MAXSLOTS];
392
393 /* Runtime Registers */
394 uint32_t iman;
395 uint32_t imod;
396 uint32_t erstsz;
397 uint32_t erstba_low;
398 uint32_t erstba_high;
399 uint32_t erdp_low;
400 uint32_t erdp_high;
401
402 int64_t mfindex_start;
403 QEMUTimer *mfwrap_timer;
404
405 dma_addr_t er_start;
406 uint32_t er_size;
407 bool er_pcs;
408 unsigned int er_ep_idx;
409 bool er_full;
410
411 XHCIEvent ev_buffer[EV_QUEUE];
412 unsigned int ev_buffer_put;
413 unsigned int ev_buffer_get;
414
415 XHCIRing cmd_ring;
416 };
417
418 typedef struct XHCIEvRingSeg {
419 uint32_t addr_low;
420 uint32_t addr_high;
421 uint32_t size;
422 uint32_t rsvd;
423 } XHCIEvRingSeg;
424
425 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
426 unsigned int epid);
427 static void xhci_event(XHCIState *xhci, XHCIEvent *event);
428 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event);
429
430 static const char *TRBType_names[] = {
431 [TRB_RESERVED] = "TRB_RESERVED",
432 [TR_NORMAL] = "TR_NORMAL",
433 [TR_SETUP] = "TR_SETUP",
434 [TR_DATA] = "TR_DATA",
435 [TR_STATUS] = "TR_STATUS",
436 [TR_ISOCH] = "TR_ISOCH",
437 [TR_LINK] = "TR_LINK",
438 [TR_EVDATA] = "TR_EVDATA",
439 [TR_NOOP] = "TR_NOOP",
440 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT",
441 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT",
442 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE",
443 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT",
444 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT",
445 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT",
446 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT",
447 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE",
448 [CR_RESET_DEVICE] = "CR_RESET_DEVICE",
449 [CR_FORCE_EVENT] = "CR_FORCE_EVENT",
450 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW",
451 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE",
452 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH",
453 [CR_FORCE_HEADER] = "CR_FORCE_HEADER",
454 [CR_NOOP] = "CR_NOOP",
455 [ER_TRANSFER] = "ER_TRANSFER",
456 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE",
457 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE",
458 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST",
459 [ER_DOORBELL] = "ER_DOORBELL",
460 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER",
461 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION",
462 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP",
463 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
464 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
465 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
466 };
467
468 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen)
469 {
470 if (index >= llen || list[index] == NULL) {
471 return "???";
472 }
473 return list[index];
474 }
475
476 static const char *trb_name(XHCITRB *trb)
477 {
478 return lookup_name(TRB_TYPE(*trb), TRBType_names,
479 ARRAY_SIZE(TRBType_names));
480 }
481
482 static uint64_t xhci_mfindex_get(XHCIState *xhci)
483 {
484 int64_t now = qemu_get_clock_ns(vm_clock);
485 return (now - xhci->mfindex_start) / 125000;
486 }
487
488 static void xhci_mfwrap_update(XHCIState *xhci)
489 {
490 const uint32_t bits = USBCMD_RS | USBCMD_EWE;
491 uint32_t mfindex, left;
492 int64_t now;
493
494 if ((xhci->usbcmd & bits) == bits) {
495 now = qemu_get_clock_ns(vm_clock);
496 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff;
497 left = 0x4000 - mfindex;
498 qemu_mod_timer(xhci->mfwrap_timer, now + left * 125000);
499 } else {
500 qemu_del_timer(xhci->mfwrap_timer);
501 }
502 }
503
504 static void xhci_mfwrap_timer(void *opaque)
505 {
506 XHCIState *xhci = opaque;
507 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS };
508
509 xhci_event(xhci, &wrap);
510 xhci_mfwrap_update(xhci);
511 }
512
513 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high)
514 {
515 if (sizeof(dma_addr_t) == 4) {
516 return low;
517 } else {
518 return low | (((dma_addr_t)high << 16) << 16);
519 }
520 }
521
522 static inline dma_addr_t xhci_mask64(uint64_t addr)
523 {
524 if (sizeof(dma_addr_t) == 4) {
525 return addr & 0xffffffff;
526 } else {
527 return addr;
528 }
529 }
530
531 static void xhci_irq_update(XHCIState *xhci)
532 {
533 int level = 0;
534
535 if (xhci->iman & IMAN_IP && xhci->iman & IMAN_IE &&
536 xhci->usbcmd & USBCMD_INTE) {
537 level = 1;
538 }
539
540 if (xhci->msi && msi_enabled(&xhci->pci_dev)) {
541 if (level) {
542 trace_usb_xhci_irq_msi(0);
543 msi_notify(&xhci->pci_dev, 0);
544 }
545 } else {
546 trace_usb_xhci_irq_intx(level);
547 qemu_set_irq(xhci->irq, level);
548 }
549 }
550
551 static inline int xhci_running(XHCIState *xhci)
552 {
553 return !(xhci->usbsts & USBSTS_HCH) && !xhci->er_full;
554 }
555
556 static void xhci_die(XHCIState *xhci)
557 {
558 xhci->usbsts |= USBSTS_HCE;
559 fprintf(stderr, "xhci: asserted controller error\n");
560 }
561
562 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event)
563 {
564 XHCITRB ev_trb;
565 dma_addr_t addr;
566
567 ev_trb.parameter = cpu_to_le64(event->ptr);
568 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
569 ev_trb.control = (event->slotid << 24) | (event->epid << 16) |
570 event->flags | (event->type << TRB_TYPE_SHIFT);
571 if (xhci->er_pcs) {
572 ev_trb.control |= TRB_C;
573 }
574 ev_trb.control = cpu_to_le32(ev_trb.control);
575
576 trace_usb_xhci_queue_event(xhci->er_ep_idx, trb_name(&ev_trb),
577 ev_trb.parameter, ev_trb.status, ev_trb.control);
578
579 addr = xhci->er_start + TRB_SIZE*xhci->er_ep_idx;
580 pci_dma_write(&xhci->pci_dev, addr, &ev_trb, TRB_SIZE);
581
582 xhci->er_ep_idx++;
583 if (xhci->er_ep_idx >= xhci->er_size) {
584 xhci->er_ep_idx = 0;
585 xhci->er_pcs = !xhci->er_pcs;
586 }
587 }
588
589 static void xhci_events_update(XHCIState *xhci)
590 {
591 dma_addr_t erdp;
592 unsigned int dp_idx;
593 bool do_irq = 0;
594
595 if (xhci->usbsts & USBSTS_HCH) {
596 return;
597 }
598
599 erdp = xhci_addr64(xhci->erdp_low, xhci->erdp_high);
600 if (erdp < xhci->er_start ||
601 erdp >= (xhci->er_start + TRB_SIZE*xhci->er_size)) {
602 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
603 fprintf(stderr, "xhci: ER at "DMA_ADDR_FMT" len %d\n",
604 xhci->er_start, xhci->er_size);
605 xhci_die(xhci);
606 return;
607 }
608 dp_idx = (erdp - xhci->er_start) / TRB_SIZE;
609 assert(dp_idx < xhci->er_size);
610
611 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
612 * deadlocks when the ER is full. Hack it by holding off events until
613 * the driver decides to free at least half of the ring */
614 if (xhci->er_full) {
615 int er_free = dp_idx - xhci->er_ep_idx;
616 if (er_free <= 0) {
617 er_free += xhci->er_size;
618 }
619 if (er_free < (xhci->er_size/2)) {
620 DPRINTF("xhci_events_update(): event ring still "
621 "more than half full (hack)\n");
622 return;
623 }
624 }
625
626 while (xhci->ev_buffer_put != xhci->ev_buffer_get) {
627 assert(xhci->er_full);
628 if (((xhci->er_ep_idx+1) % xhci->er_size) == dp_idx) {
629 DPRINTF("xhci_events_update(): event ring full again\n");
630 #ifndef ER_FULL_HACK
631 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
632 xhci_write_event(xhci, &full);
633 #endif
634 do_irq = 1;
635 break;
636 }
637 XHCIEvent *event = &xhci->ev_buffer[xhci->ev_buffer_get];
638 xhci_write_event(xhci, event);
639 xhci->ev_buffer_get++;
640 do_irq = 1;
641 if (xhci->ev_buffer_get == EV_QUEUE) {
642 xhci->ev_buffer_get = 0;
643 }
644 }
645
646 if (do_irq) {
647 xhci->erdp_low |= ERDP_EHB;
648 xhci->iman |= IMAN_IP;
649 xhci->usbsts |= USBSTS_EINT;
650 xhci_irq_update(xhci);
651 }
652
653 if (xhci->er_full && xhci->ev_buffer_put == xhci->ev_buffer_get) {
654 DPRINTF("xhci_events_update(): event ring no longer full\n");
655 xhci->er_full = 0;
656 }
657 return;
658 }
659
660 static void xhci_event(XHCIState *xhci, XHCIEvent *event)
661 {
662 dma_addr_t erdp;
663 unsigned int dp_idx;
664
665 if (xhci->er_full) {
666 DPRINTF("xhci_event(): ER full, queueing\n");
667 if (((xhci->ev_buffer_put+1) % EV_QUEUE) == xhci->ev_buffer_get) {
668 fprintf(stderr, "xhci: event queue full, dropping event!\n");
669 return;
670 }
671 xhci->ev_buffer[xhci->ev_buffer_put++] = *event;
672 if (xhci->ev_buffer_put == EV_QUEUE) {
673 xhci->ev_buffer_put = 0;
674 }
675 return;
676 }
677
678 erdp = xhci_addr64(xhci->erdp_low, xhci->erdp_high);
679 if (erdp < xhci->er_start ||
680 erdp >= (xhci->er_start + TRB_SIZE*xhci->er_size)) {
681 fprintf(stderr, "xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
682 fprintf(stderr, "xhci: ER at "DMA_ADDR_FMT" len %d\n",
683 xhci->er_start, xhci->er_size);
684 xhci_die(xhci);
685 return;
686 }
687
688 dp_idx = (erdp - xhci->er_start) / TRB_SIZE;
689 assert(dp_idx < xhci->er_size);
690
691 if ((xhci->er_ep_idx+1) % xhci->er_size == dp_idx) {
692 DPRINTF("xhci_event(): ER full, queueing\n");
693 #ifndef ER_FULL_HACK
694 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
695 xhci_write_event(xhci, &full);
696 #endif
697 xhci->er_full = 1;
698 if (((xhci->ev_buffer_put+1) % EV_QUEUE) == xhci->ev_buffer_get) {
699 fprintf(stderr, "xhci: event queue full, dropping event!\n");
700 return;
701 }
702 xhci->ev_buffer[xhci->ev_buffer_put++] = *event;
703 if (xhci->ev_buffer_put == EV_QUEUE) {
704 xhci->ev_buffer_put = 0;
705 }
706 } else {
707 xhci_write_event(xhci, event);
708 }
709
710 xhci->erdp_low |= ERDP_EHB;
711 xhci->iman |= IMAN_IP;
712 xhci->usbsts |= USBSTS_EINT;
713
714 xhci_irq_update(xhci);
715 }
716
717 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
718 dma_addr_t base)
719 {
720 ring->base = base;
721 ring->dequeue = base;
722 ring->ccs = 1;
723 }
724
725 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
726 dma_addr_t *addr)
727 {
728 while (1) {
729 TRBType type;
730 pci_dma_read(&xhci->pci_dev, ring->dequeue, trb, TRB_SIZE);
731 trb->addr = ring->dequeue;
732 trb->ccs = ring->ccs;
733 le64_to_cpus(&trb->parameter);
734 le32_to_cpus(&trb->status);
735 le32_to_cpus(&trb->control);
736
737 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb),
738 trb->parameter, trb->status, trb->control);
739
740 if ((trb->control & TRB_C) != ring->ccs) {
741 return 0;
742 }
743
744 type = TRB_TYPE(*trb);
745
746 if (type != TR_LINK) {
747 if (addr) {
748 *addr = ring->dequeue;
749 }
750 ring->dequeue += TRB_SIZE;
751 return type;
752 } else {
753 ring->dequeue = xhci_mask64(trb->parameter);
754 if (trb->control & TRB_LK_TC) {
755 ring->ccs = !ring->ccs;
756 }
757 }
758 }
759 }
760
761 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
762 {
763 XHCITRB trb;
764 int length = 0;
765 dma_addr_t dequeue = ring->dequeue;
766 bool ccs = ring->ccs;
767 /* hack to bundle together the two/three TDs that make a setup transfer */
768 bool control_td_set = 0;
769
770 while (1) {
771 TRBType type;
772 pci_dma_read(&xhci->pci_dev, dequeue, &trb, TRB_SIZE);
773 le64_to_cpus(&trb.parameter);
774 le32_to_cpus(&trb.status);
775 le32_to_cpus(&trb.control);
776
777 if ((trb.control & TRB_C) != ccs) {
778 return -length;
779 }
780
781 type = TRB_TYPE(trb);
782
783 if (type == TR_LINK) {
784 dequeue = xhci_mask64(trb.parameter);
785 if (trb.control & TRB_LK_TC) {
786 ccs = !ccs;
787 }
788 continue;
789 }
790
791 length += 1;
792 dequeue += TRB_SIZE;
793
794 if (type == TR_SETUP) {
795 control_td_set = 1;
796 } else if (type == TR_STATUS) {
797 control_td_set = 0;
798 }
799
800 if (!control_td_set && !(trb.control & TRB_TR_CH)) {
801 return length;
802 }
803 }
804 }
805
806 static void xhci_er_reset(XHCIState *xhci)
807 {
808 XHCIEvRingSeg seg;
809
810 /* cache the (sole) event ring segment location */
811 if (xhci->erstsz != 1) {
812 fprintf(stderr, "xhci: invalid value for ERSTSZ: %d\n", xhci->erstsz);
813 xhci_die(xhci);
814 return;
815 }
816 dma_addr_t erstba = xhci_addr64(xhci->erstba_low, xhci->erstba_high);
817 pci_dma_read(&xhci->pci_dev, erstba, &seg, sizeof(seg));
818 le32_to_cpus(&seg.addr_low);
819 le32_to_cpus(&seg.addr_high);
820 le32_to_cpus(&seg.size);
821 if (seg.size < 16 || seg.size > 4096) {
822 fprintf(stderr, "xhci: invalid value for segment size: %d\n", seg.size);
823 xhci_die(xhci);
824 return;
825 }
826 xhci->er_start = xhci_addr64(seg.addr_low, seg.addr_high);
827 xhci->er_size = seg.size;
828
829 xhci->er_ep_idx = 0;
830 xhci->er_pcs = 1;
831 xhci->er_full = 0;
832
833 DPRINTF("xhci: event ring:" DMA_ADDR_FMT " [%d]\n",
834 xhci->er_start, xhci->er_size);
835 }
836
837 static void xhci_run(XHCIState *xhci)
838 {
839 trace_usb_xhci_run();
840 xhci->usbsts &= ~USBSTS_HCH;
841 xhci->mfindex_start = qemu_get_clock_ns(vm_clock);
842 }
843
844 static void xhci_stop(XHCIState *xhci)
845 {
846 trace_usb_xhci_stop();
847 xhci->usbsts |= USBSTS_HCH;
848 xhci->crcr_low &= ~CRCR_CRR;
849 }
850
851 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx,
852 uint32_t state)
853 {
854 uint32_t ctx[5];
855 if (epctx->state == state) {
856 return;
857 }
858
859 pci_dma_read(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx));
860 ctx[0] &= ~EP_STATE_MASK;
861 ctx[0] |= state;
862 ctx[2] = epctx->ring.dequeue | epctx->ring.ccs;
863 ctx[3] = (epctx->ring.dequeue >> 16) >> 16;
864 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n",
865 epctx->pctx, state, ctx[3], ctx[2]);
866 pci_dma_write(&xhci->pci_dev, epctx->pctx, ctx, sizeof(ctx));
867 epctx->state = state;
868 }
869
870 static void xhci_ep_kick_timer(void *opaque)
871 {
872 XHCIEPContext *epctx = opaque;
873 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid);
874 }
875
876 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid,
877 unsigned int epid, dma_addr_t pctx,
878 uint32_t *ctx)
879 {
880 XHCISlot *slot;
881 XHCIEPContext *epctx;
882 dma_addr_t dequeue;
883 int i;
884
885 trace_usb_xhci_ep_enable(slotid, epid);
886 assert(slotid >= 1 && slotid <= MAXSLOTS);
887 assert(epid >= 1 && epid <= 31);
888
889 slot = &xhci->slots[slotid-1];
890 if (slot->eps[epid-1]) {
891 fprintf(stderr, "xhci: slot %d ep %d already enabled!\n", slotid, epid);
892 return CC_TRB_ERROR;
893 }
894
895 epctx = g_malloc(sizeof(XHCIEPContext));
896 memset(epctx, 0, sizeof(XHCIEPContext));
897 epctx->xhci = xhci;
898 epctx->slotid = slotid;
899 epctx->epid = epid;
900
901 slot->eps[epid-1] = epctx;
902
903 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]);
904 xhci_ring_init(xhci, &epctx->ring, dequeue);
905 epctx->ring.ccs = ctx[2] & 1;
906
907 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK;
908 DPRINTF("xhci: endpoint %d.%d type is %d\n", epid/2, epid%2, epctx->type);
909 epctx->pctx = pctx;
910 epctx->max_psize = ctx[1]>>16;
911 epctx->max_psize *= 1+((ctx[1]>>8)&0xff);
912 DPRINTF("xhci: endpoint %d.%d max transaction (burst) size is %d\n",
913 epid/2, epid%2, epctx->max_psize);
914 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) {
915 usb_packet_init(&epctx->transfers[i].packet);
916 }
917
918 epctx->interval = 1 << (ctx[0] >> 16) & 0xff;
919 epctx->mfindex_last = 0;
920 epctx->kick_timer = qemu_new_timer_ns(vm_clock, xhci_ep_kick_timer, epctx);
921
922 epctx->state = EP_RUNNING;
923 ctx[0] &= ~EP_STATE_MASK;
924 ctx[0] |= EP_RUNNING;
925
926 return CC_SUCCESS;
927 }
928
929 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid,
930 unsigned int epid)
931 {
932 XHCISlot *slot;
933 XHCIEPContext *epctx;
934 int i, xferi, killed = 0;
935 assert(slotid >= 1 && slotid <= MAXSLOTS);
936 assert(epid >= 1 && epid <= 31);
937
938 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid);
939
940 slot = &xhci->slots[slotid-1];
941
942 if (!slot->eps[epid-1]) {
943 return 0;
944 }
945
946 epctx = slot->eps[epid-1];
947
948 xferi = epctx->next_xfer;
949 for (i = 0; i < TD_QUEUE; i++) {
950 XHCITransfer *t = &epctx->transfers[xferi];
951 if (t->running_async) {
952 usb_cancel_packet(&t->packet);
953 t->running_async = 0;
954 t->cancelled = 1;
955 DPRINTF("xhci: cancelling transfer %d, waiting for it to complete...\n", i);
956 killed++;
957 }
958 if (t->running_retry) {
959 t->running_retry = 0;
960 epctx->retry = NULL;
961 qemu_del_timer(epctx->kick_timer);
962 }
963 if (t->trbs) {
964 g_free(t->trbs);
965 }
966
967 t->trbs = NULL;
968 t->trb_count = t->trb_alloced = 0;
969 xferi = (xferi + 1) % TD_QUEUE;
970 }
971 return killed;
972 }
973
974 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
975 unsigned int epid)
976 {
977 XHCISlot *slot;
978 XHCIEPContext *epctx;
979
980 trace_usb_xhci_ep_disable(slotid, epid);
981 assert(slotid >= 1 && slotid <= MAXSLOTS);
982 assert(epid >= 1 && epid <= 31);
983
984 slot = &xhci->slots[slotid-1];
985
986 if (!slot->eps[epid-1]) {
987 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid);
988 return CC_SUCCESS;
989 }
990
991 xhci_ep_nuke_xfers(xhci, slotid, epid);
992
993 epctx = slot->eps[epid-1];
994
995 xhci_set_ep_state(xhci, epctx, EP_DISABLED);
996
997 qemu_free_timer(epctx->kick_timer);
998 g_free(epctx);
999 slot->eps[epid-1] = NULL;
1000
1001 return CC_SUCCESS;
1002 }
1003
1004 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid,
1005 unsigned int epid)
1006 {
1007 XHCISlot *slot;
1008 XHCIEPContext *epctx;
1009
1010 trace_usb_xhci_ep_stop(slotid, epid);
1011 assert(slotid >= 1 && slotid <= MAXSLOTS);
1012
1013 if (epid < 1 || epid > 31) {
1014 fprintf(stderr, "xhci: bad ep %d\n", epid);
1015 return CC_TRB_ERROR;
1016 }
1017
1018 slot = &xhci->slots[slotid-1];
1019
1020 if (!slot->eps[epid-1]) {
1021 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1022 return CC_EP_NOT_ENABLED_ERROR;
1023 }
1024
1025 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) {
1026 fprintf(stderr, "xhci: FIXME: endpoint stopped w/ xfers running, "
1027 "data might be lost\n");
1028 }
1029
1030 epctx = slot->eps[epid-1];
1031
1032 xhci_set_ep_state(xhci, epctx, EP_STOPPED);
1033
1034 return CC_SUCCESS;
1035 }
1036
1037 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid,
1038 unsigned int epid)
1039 {
1040 XHCISlot *slot;
1041 XHCIEPContext *epctx;
1042 USBDevice *dev;
1043
1044 trace_usb_xhci_ep_reset(slotid, epid);
1045 assert(slotid >= 1 && slotid <= MAXSLOTS);
1046
1047 if (epid < 1 || epid > 31) {
1048 fprintf(stderr, "xhci: bad ep %d\n", epid);
1049 return CC_TRB_ERROR;
1050 }
1051
1052 slot = &xhci->slots[slotid-1];
1053
1054 if (!slot->eps[epid-1]) {
1055 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1056 return CC_EP_NOT_ENABLED_ERROR;
1057 }
1058
1059 epctx = slot->eps[epid-1];
1060
1061 if (epctx->state != EP_HALTED) {
1062 fprintf(stderr, "xhci: reset EP while EP %d not halted (%d)\n",
1063 epid, epctx->state);
1064 return CC_CONTEXT_STATE_ERROR;
1065 }
1066
1067 if (xhci_ep_nuke_xfers(xhci, slotid, epid) > 0) {
1068 fprintf(stderr, "xhci: FIXME: endpoint reset w/ xfers running, "
1069 "data might be lost\n");
1070 }
1071
1072 uint8_t ep = epid>>1;
1073
1074 if (epid & 1) {
1075 ep |= 0x80;
1076 }
1077
1078 dev = xhci->ports[xhci->slots[slotid-1].port-1].port.dev;
1079 if (!dev) {
1080 return CC_USB_TRANSACTION_ERROR;
1081 }
1082
1083 xhci_set_ep_state(xhci, epctx, EP_STOPPED);
1084
1085 return CC_SUCCESS;
1086 }
1087
1088 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid,
1089 unsigned int epid, uint64_t pdequeue)
1090 {
1091 XHCISlot *slot;
1092 XHCIEPContext *epctx;
1093 dma_addr_t dequeue;
1094
1095 assert(slotid >= 1 && slotid <= MAXSLOTS);
1096
1097 if (epid < 1 || epid > 31) {
1098 fprintf(stderr, "xhci: bad ep %d\n", epid);
1099 return CC_TRB_ERROR;
1100 }
1101
1102 DPRINTF("xhci_set_ep_dequeue(%d, %d, %016"PRIx64")\n", slotid, epid, pdequeue);
1103 dequeue = xhci_mask64(pdequeue);
1104
1105 slot = &xhci->slots[slotid-1];
1106
1107 if (!slot->eps[epid-1]) {
1108 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1109 return CC_EP_NOT_ENABLED_ERROR;
1110 }
1111
1112 epctx = slot->eps[epid-1];
1113
1114
1115 if (epctx->state != EP_STOPPED) {
1116 fprintf(stderr, "xhci: set EP dequeue pointer while EP %d not stopped\n", epid);
1117 return CC_CONTEXT_STATE_ERROR;
1118 }
1119
1120 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
1121 epctx->ring.ccs = dequeue & 1;
1122
1123 xhci_set_ep_state(xhci, epctx, EP_STOPPED);
1124
1125 return CC_SUCCESS;
1126 }
1127
1128 static int xhci_xfer_map(XHCITransfer *xfer)
1129 {
1130 int in_xfer = (xfer->packet.pid == USB_TOKEN_IN);
1131 XHCIState *xhci = xfer->xhci;
1132 int i;
1133
1134 pci_dma_sglist_init(&xfer->sgl, &xhci->pci_dev, xfer->trb_count);
1135 for (i = 0; i < xfer->trb_count; i++) {
1136 XHCITRB *trb = &xfer->trbs[i];
1137 dma_addr_t addr;
1138 unsigned int chunk = 0;
1139
1140 switch (TRB_TYPE(*trb)) {
1141 case TR_DATA:
1142 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) {
1143 fprintf(stderr, "xhci: data direction mismatch for TR_DATA\n");
1144 goto err;
1145 }
1146 /* fallthrough */
1147 case TR_NORMAL:
1148 case TR_ISOCH:
1149 addr = xhci_mask64(trb->parameter);
1150 chunk = trb->status & 0x1ffff;
1151 if (trb->control & TRB_TR_IDT) {
1152 if (chunk > 8 || in_xfer) {
1153 fprintf(stderr, "xhci: invalid immediate data TRB\n");
1154 goto err;
1155 }
1156 qemu_sglist_add(&xfer->sgl, trb->addr, chunk);
1157 } else {
1158 qemu_sglist_add(&xfer->sgl, addr, chunk);
1159 }
1160 break;
1161 }
1162 }
1163
1164 usb_packet_map(&xfer->packet, &xfer->sgl);
1165 return 0;
1166
1167 err:
1168 qemu_sglist_destroy(&xfer->sgl);
1169 xhci_die(xhci);
1170 return -1;
1171 }
1172
1173 static void xhci_xfer_unmap(XHCITransfer *xfer)
1174 {
1175 usb_packet_unmap(&xfer->packet, &xfer->sgl);
1176 qemu_sglist_destroy(&xfer->sgl);
1177 }
1178
1179 static void xhci_xfer_report(XHCITransfer *xfer)
1180 {
1181 uint32_t edtla = 0;
1182 unsigned int left;
1183 bool reported = 0;
1184 bool shortpkt = 0;
1185 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS};
1186 XHCIState *xhci = xfer->xhci;
1187 int i;
1188
1189 left = xfer->packet.result < 0 ? 0 : xfer->packet.result;
1190
1191 for (i = 0; i < xfer->trb_count; i++) {
1192 XHCITRB *trb = &xfer->trbs[i];
1193 unsigned int chunk = 0;
1194
1195 switch (TRB_TYPE(*trb)) {
1196 case TR_DATA:
1197 case TR_NORMAL:
1198 case TR_ISOCH:
1199 chunk = trb->status & 0x1ffff;
1200 if (chunk > left) {
1201 chunk = left;
1202 if (xfer->status == CC_SUCCESS) {
1203 shortpkt = 1;
1204 }
1205 }
1206 left -= chunk;
1207 edtla += chunk;
1208 break;
1209 case TR_STATUS:
1210 reported = 0;
1211 shortpkt = 0;
1212 break;
1213 }
1214
1215 if (!reported && ((trb->control & TRB_TR_IOC) ||
1216 (shortpkt && (trb->control & TRB_TR_ISP)) ||
1217 (xfer->status != CC_SUCCESS))) {
1218 event.slotid = xfer->slotid;
1219 event.epid = xfer->epid;
1220 event.length = (trb->status & 0x1ffff) - chunk;
1221 event.flags = 0;
1222 event.ptr = trb->addr;
1223 if (xfer->status == CC_SUCCESS) {
1224 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS;
1225 } else {
1226 event.ccode = xfer->status;
1227 }
1228 if (TRB_TYPE(*trb) == TR_EVDATA) {
1229 event.ptr = trb->parameter;
1230 event.flags |= TRB_EV_ED;
1231 event.length = edtla & 0xffffff;
1232 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length);
1233 edtla = 0;
1234 }
1235 xhci_event(xhci, &event);
1236 reported = 1;
1237 if (xfer->status != CC_SUCCESS) {
1238 return;
1239 }
1240 }
1241 }
1242 }
1243
1244 static void xhci_stall_ep(XHCITransfer *xfer)
1245 {
1246 XHCIState *xhci = xfer->xhci;
1247 XHCISlot *slot = &xhci->slots[xfer->slotid-1];
1248 XHCIEPContext *epctx = slot->eps[xfer->epid-1];
1249
1250 epctx->ring.dequeue = xfer->trbs[0].addr;
1251 epctx->ring.ccs = xfer->trbs[0].ccs;
1252 xhci_set_ep_state(xhci, epctx, EP_HALTED);
1253 DPRINTF("xhci: stalled slot %d ep %d\n", xfer->slotid, xfer->epid);
1254 DPRINTF("xhci: will continue at "DMA_ADDR_FMT"\n", epctx->ring.dequeue);
1255 }
1256
1257 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer,
1258 XHCIEPContext *epctx);
1259
1260 static USBDevice *xhci_find_device(XHCIPort *port, uint8_t addr)
1261 {
1262 if (!(port->portsc & PORTSC_PED)) {
1263 return NULL;
1264 }
1265 return usb_find_device(&port->port, addr);
1266 }
1267
1268 static int xhci_setup_packet(XHCITransfer *xfer)
1269 {
1270 XHCIState *xhci = xfer->xhci;
1271 XHCIPort *port;
1272 USBDevice *dev;
1273 USBEndpoint *ep;
1274 int dir;
1275
1276 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT;
1277
1278 if (xfer->packet.ep) {
1279 ep = xfer->packet.ep;
1280 dev = ep->dev;
1281 } else {
1282 port = &xhci->ports[xhci->slots[xfer->slotid-1].port-1];
1283 dev = xhci_find_device(port, xhci->slots[xfer->slotid-1].devaddr);
1284 if (!dev) {
1285 fprintf(stderr, "xhci: slot %d port %d has no device\n",
1286 xfer->slotid, xhci->slots[xfer->slotid-1].port);
1287 return -1;
1288 }
1289 ep = usb_ep_get(dev, dir, xfer->epid >> 1);
1290 }
1291
1292 usb_packet_setup(&xfer->packet, dir, ep, xfer->trbs[0].addr);
1293 xhci_xfer_map(xfer);
1294 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1295 xfer->packet.pid, dev->addr, ep->nr);
1296 return 0;
1297 }
1298
1299 static int xhci_complete_packet(XHCITransfer *xfer, int ret)
1300 {
1301 if (ret == USB_RET_ASYNC) {
1302 trace_usb_xhci_xfer_async(xfer);
1303 xfer->running_async = 1;
1304 xfer->running_retry = 0;
1305 xfer->complete = 0;
1306 xfer->cancelled = 0;
1307 return 0;
1308 } else if (ret == USB_RET_NAK) {
1309 trace_usb_xhci_xfer_nak(xfer);
1310 xfer->running_async = 0;
1311 xfer->running_retry = 1;
1312 xfer->complete = 0;
1313 xfer->cancelled = 0;
1314 return 0;
1315 } else {
1316 xfer->running_async = 0;
1317 xfer->running_retry = 0;
1318 xfer->complete = 1;
1319 xhci_xfer_unmap(xfer);
1320 }
1321
1322 if (ret >= 0) {
1323 trace_usb_xhci_xfer_success(xfer, ret);
1324 xfer->status = CC_SUCCESS;
1325 xhci_xfer_report(xfer);
1326 return 0;
1327 }
1328
1329 /* error */
1330 trace_usb_xhci_xfer_error(xfer, ret);
1331 switch (ret) {
1332 case USB_RET_NODEV:
1333 xfer->status = CC_USB_TRANSACTION_ERROR;
1334 xhci_xfer_report(xfer);
1335 xhci_stall_ep(xfer);
1336 break;
1337 case USB_RET_STALL:
1338 xfer->status = CC_STALL_ERROR;
1339 xhci_xfer_report(xfer);
1340 xhci_stall_ep(xfer);
1341 break;
1342 default:
1343 fprintf(stderr, "%s: FIXME: ret = %d\n", __FUNCTION__, ret);
1344 FIXME();
1345 }
1346 return 0;
1347 }
1348
1349 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer)
1350 {
1351 XHCITRB *trb_setup, *trb_status;
1352 uint8_t bmRequestType;
1353 int ret;
1354
1355 trb_setup = &xfer->trbs[0];
1356 trb_status = &xfer->trbs[xfer->trb_count-1];
1357
1358 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid);
1359
1360 /* at most one Event Data TRB allowed after STATUS */
1361 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) {
1362 trb_status--;
1363 }
1364
1365 /* do some sanity checks */
1366 if (TRB_TYPE(*trb_setup) != TR_SETUP) {
1367 fprintf(stderr, "xhci: ep0 first TD not SETUP: %d\n",
1368 TRB_TYPE(*trb_setup));
1369 return -1;
1370 }
1371 if (TRB_TYPE(*trb_status) != TR_STATUS) {
1372 fprintf(stderr, "xhci: ep0 last TD not STATUS: %d\n",
1373 TRB_TYPE(*trb_status));
1374 return -1;
1375 }
1376 if (!(trb_setup->control & TRB_TR_IDT)) {
1377 fprintf(stderr, "xhci: Setup TRB doesn't have IDT set\n");
1378 return -1;
1379 }
1380 if ((trb_setup->status & 0x1ffff) != 8) {
1381 fprintf(stderr, "xhci: Setup TRB has bad length (%d)\n",
1382 (trb_setup->status & 0x1ffff));
1383 return -1;
1384 }
1385
1386 bmRequestType = trb_setup->parameter;
1387
1388 xfer->in_xfer = bmRequestType & USB_DIR_IN;
1389 xfer->iso_xfer = false;
1390
1391 if (xhci_setup_packet(xfer) < 0) {
1392 return -1;
1393 }
1394 xfer->packet.parameter = trb_setup->parameter;
1395
1396 ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1397
1398 xhci_complete_packet(xfer, ret);
1399 if (!xfer->running_async && !xfer->running_retry) {
1400 xhci_kick_ep(xhci, xfer->slotid, xfer->epid);
1401 }
1402 return 0;
1403 }
1404
1405 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1406 XHCIEPContext *epctx, uint64_t mfindex)
1407 {
1408 if (xfer->trbs[0].control & TRB_TR_SIA) {
1409 uint64_t asap = ((mfindex + epctx->interval - 1) &
1410 ~(epctx->interval-1));
1411 if (asap >= epctx->mfindex_last &&
1412 asap <= epctx->mfindex_last + epctx->interval * 4) {
1413 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval;
1414 } else {
1415 xfer->mfindex_kick = asap;
1416 }
1417 } else {
1418 xfer->mfindex_kick = (xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT)
1419 & TRB_TR_FRAMEID_MASK;
1420 xfer->mfindex_kick |= mfindex & ~0x3fff;
1421 if (xfer->mfindex_kick < mfindex) {
1422 xfer->mfindex_kick += 0x4000;
1423 }
1424 }
1425 }
1426
1427 static void xhci_check_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1428 XHCIEPContext *epctx, uint64_t mfindex)
1429 {
1430 if (xfer->mfindex_kick > mfindex) {
1431 qemu_mod_timer(epctx->kick_timer, qemu_get_clock_ns(vm_clock) +
1432 (xfer->mfindex_kick - mfindex) * 125000);
1433 xfer->running_retry = 1;
1434 } else {
1435 epctx->mfindex_last = xfer->mfindex_kick;
1436 qemu_del_timer(epctx->kick_timer);
1437 xfer->running_retry = 0;
1438 }
1439 }
1440
1441
1442 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1443 {
1444 uint64_t mfindex;
1445 int ret;
1446
1447 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid);
1448
1449 xfer->in_xfer = epctx->type>>2;
1450
1451 switch(epctx->type) {
1452 case ET_INTR_OUT:
1453 case ET_INTR_IN:
1454 case ET_BULK_OUT:
1455 case ET_BULK_IN:
1456 xfer->pkts = 0;
1457 xfer->iso_xfer = false;
1458 break;
1459 case ET_ISO_OUT:
1460 case ET_ISO_IN:
1461 xfer->pkts = 1;
1462 xfer->iso_xfer = true;
1463 mfindex = xhci_mfindex_get(xhci);
1464 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex);
1465 xhci_check_iso_kick(xhci, xfer, epctx, mfindex);
1466 if (xfer->running_retry) {
1467 return -1;
1468 }
1469 break;
1470 default:
1471 fprintf(stderr, "xhci: unknown or unhandled EP "
1472 "(type %d, in %d, ep %02x)\n",
1473 epctx->type, xfer->in_xfer, xfer->epid);
1474 return -1;
1475 }
1476
1477 if (xhci_setup_packet(xfer) < 0) {
1478 return -1;
1479 }
1480 ret = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1481
1482 xhci_complete_packet(xfer, ret);
1483 if (!xfer->running_async && !xfer->running_retry) {
1484 xhci_kick_ep(xhci, xfer->slotid, xfer->epid);
1485 }
1486 return 0;
1487 }
1488
1489 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
1490 {
1491 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid);
1492 return xhci_submit(xhci, xfer, epctx);
1493 }
1494
1495 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, unsigned int epid)
1496 {
1497 XHCIEPContext *epctx;
1498 uint64_t mfindex;
1499 int length;
1500 int i;
1501
1502 trace_usb_xhci_ep_kick(slotid, epid);
1503 assert(slotid >= 1 && slotid <= MAXSLOTS);
1504 assert(epid >= 1 && epid <= 31);
1505
1506 if (!xhci->slots[slotid-1].enabled) {
1507 fprintf(stderr, "xhci: xhci_kick_ep for disabled slot %d\n", slotid);
1508 return;
1509 }
1510 epctx = xhci->slots[slotid-1].eps[epid-1];
1511 if (!epctx) {
1512 fprintf(stderr, "xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
1513 epid, slotid);
1514 return;
1515 }
1516
1517 if (epctx->retry) {
1518 XHCITransfer *xfer = epctx->retry;
1519 int result;
1520
1521 trace_usb_xhci_xfer_retry(xfer);
1522 assert(xfer->running_retry);
1523 if (xfer->iso_xfer) {
1524 /* retry delayed iso transfer */
1525 mfindex = xhci_mfindex_get(xhci);
1526 xhci_check_iso_kick(xhci, xfer, epctx, mfindex);
1527 if (xfer->running_retry) {
1528 return;
1529 }
1530 if (xhci_setup_packet(xfer) < 0) {
1531 return;
1532 }
1533 result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1534 assert(result != USB_RET_NAK);
1535 xhci_complete_packet(xfer, result);
1536 } else {
1537 /* retry nak'ed transfer */
1538 if (xhci_setup_packet(xfer) < 0) {
1539 return;
1540 }
1541 result = usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1542 if (result == USB_RET_NAK) {
1543 return;
1544 }
1545 xhci_complete_packet(xfer, result);
1546 }
1547 assert(!xfer->running_retry);
1548 epctx->retry = NULL;
1549 }
1550
1551 if (epctx->state == EP_HALTED) {
1552 DPRINTF("xhci: ep halted, not running schedule\n");
1553 return;
1554 }
1555
1556 xhci_set_ep_state(xhci, epctx, EP_RUNNING);
1557
1558 while (1) {
1559 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer];
1560 if (xfer->running_async || xfer->running_retry) {
1561 break;
1562 }
1563 length = xhci_ring_chain_length(xhci, &epctx->ring);
1564 if (length < 0) {
1565 break;
1566 } else if (length == 0) {
1567 break;
1568 }
1569 if (xfer->trbs && xfer->trb_alloced < length) {
1570 xfer->trb_count = 0;
1571 xfer->trb_alloced = 0;
1572 g_free(xfer->trbs);
1573 xfer->trbs = NULL;
1574 }
1575 if (!xfer->trbs) {
1576 xfer->trbs = g_malloc(sizeof(XHCITRB) * length);
1577 xfer->trb_alloced = length;
1578 }
1579 xfer->trb_count = length;
1580
1581 for (i = 0; i < length; i++) {
1582 assert(xhci_ring_fetch(xhci, &epctx->ring, &xfer->trbs[i], NULL));
1583 }
1584 xfer->xhci = xhci;
1585 xfer->epid = epid;
1586 xfer->slotid = slotid;
1587
1588 if (epid == 1) {
1589 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) {
1590 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
1591 } else {
1592 fprintf(stderr, "xhci: error firing CTL transfer\n");
1593 }
1594 } else {
1595 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) {
1596 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
1597 } else {
1598 if (!xfer->iso_xfer) {
1599 fprintf(stderr, "xhci: error firing data transfer\n");
1600 }
1601 }
1602 }
1603
1604 if (epctx->state == EP_HALTED) {
1605 break;
1606 }
1607 if (xfer->running_retry) {
1608 DPRINTF("xhci: xfer nacked, stopping schedule\n");
1609 epctx->retry = xfer;
1610 break;
1611 }
1612 }
1613 }
1614
1615 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid)
1616 {
1617 trace_usb_xhci_slot_enable(slotid);
1618 assert(slotid >= 1 && slotid <= MAXSLOTS);
1619 xhci->slots[slotid-1].enabled = 1;
1620 xhci->slots[slotid-1].port = 0;
1621 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31);
1622
1623 return CC_SUCCESS;
1624 }
1625
1626 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid)
1627 {
1628 int i;
1629
1630 trace_usb_xhci_slot_disable(slotid);
1631 assert(slotid >= 1 && slotid <= MAXSLOTS);
1632
1633 for (i = 1; i <= 31; i++) {
1634 if (xhci->slots[slotid-1].eps[i-1]) {
1635 xhci_disable_ep(xhci, slotid, i);
1636 }
1637 }
1638
1639 xhci->slots[slotid-1].enabled = 0;
1640 return CC_SUCCESS;
1641 }
1642
1643 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
1644 uint64_t pictx, bool bsr)
1645 {
1646 XHCISlot *slot;
1647 USBDevice *dev;
1648 dma_addr_t ictx, octx, dcbaap;
1649 uint64_t poctx;
1650 uint32_t ictl_ctx[2];
1651 uint32_t slot_ctx[4];
1652 uint32_t ep0_ctx[5];
1653 unsigned int port;
1654 int i;
1655 TRBCCode res;
1656
1657 trace_usb_xhci_slot_address(slotid);
1658 assert(slotid >= 1 && slotid <= MAXSLOTS);
1659
1660 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
1661 pci_dma_read(&xhci->pci_dev, dcbaap + 8*slotid, &poctx, sizeof(poctx));
1662 ictx = xhci_mask64(pictx);
1663 octx = xhci_mask64(le64_to_cpu(poctx));
1664
1665 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
1666 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
1667
1668 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx));
1669
1670 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) {
1671 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
1672 ictl_ctx[0], ictl_ctx[1]);
1673 return CC_TRB_ERROR;
1674 }
1675
1676 pci_dma_read(&xhci->pci_dev, ictx+32, slot_ctx, sizeof(slot_ctx));
1677 pci_dma_read(&xhci->pci_dev, ictx+64, ep0_ctx, sizeof(ep0_ctx));
1678
1679 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
1680 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1681
1682 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
1683 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
1684
1685 port = (slot_ctx[1]>>16) & 0xFF;
1686 dev = xhci->ports[port-1].port.dev;
1687
1688 if (port < 1 || port > MAXPORTS) {
1689 fprintf(stderr, "xhci: bad port %d\n", port);
1690 return CC_TRB_ERROR;
1691 } else if (!dev) {
1692 fprintf(stderr, "xhci: port %d not connected\n", port);
1693 return CC_USB_TRANSACTION_ERROR;
1694 }
1695
1696 for (i = 0; i < MAXSLOTS; i++) {
1697 if (xhci->slots[i].port == port) {
1698 fprintf(stderr, "xhci: port %d already assigned to slot %d\n",
1699 port, i+1);
1700 return CC_TRB_ERROR;
1701 }
1702 }
1703
1704 slot = &xhci->slots[slotid-1];
1705 slot->port = port;
1706 slot->ctx = octx;
1707
1708 if (bsr) {
1709 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT;
1710 } else {
1711 slot->devaddr = xhci->devaddr++;
1712 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slot->devaddr;
1713 DPRINTF("xhci: device address is %d\n", slot->devaddr);
1714 usb_device_handle_control(dev, NULL,
1715 DeviceOutRequest | USB_REQ_SET_ADDRESS,
1716 slot->devaddr, 0, 0, NULL);
1717 }
1718
1719 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx);
1720
1721 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1722 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1723 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
1724 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
1725
1726 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1727 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx));
1728
1729 return res;
1730 }
1731
1732
1733 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid,
1734 uint64_t pictx, bool dc)
1735 {
1736 dma_addr_t ictx, octx;
1737 uint32_t ictl_ctx[2];
1738 uint32_t slot_ctx[4];
1739 uint32_t islot_ctx[4];
1740 uint32_t ep_ctx[5];
1741 int i;
1742 TRBCCode res;
1743
1744 trace_usb_xhci_slot_configure(slotid);
1745 assert(slotid >= 1 && slotid <= MAXSLOTS);
1746
1747 ictx = xhci_mask64(pictx);
1748 octx = xhci->slots[slotid-1].ctx;
1749
1750 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
1751 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
1752
1753 if (dc) {
1754 for (i = 2; i <= 31; i++) {
1755 if (xhci->slots[slotid-1].eps[i-1]) {
1756 xhci_disable_ep(xhci, slotid, i);
1757 }
1758 }
1759
1760 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1761 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
1762 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT;
1763 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1764 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1765 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1766
1767 return CC_SUCCESS;
1768 }
1769
1770 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx));
1771
1772 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) {
1773 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
1774 ictl_ctx[0], ictl_ctx[1]);
1775 return CC_TRB_ERROR;
1776 }
1777
1778 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx));
1779 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1780
1781 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) {
1782 fprintf(stderr, "xhci: invalid slot state %08x\n", slot_ctx[3]);
1783 return CC_CONTEXT_STATE_ERROR;
1784 }
1785
1786 for (i = 2; i <= 31; i++) {
1787 if (ictl_ctx[0] & (1<<i)) {
1788 xhci_disable_ep(xhci, slotid, i);
1789 }
1790 if (ictl_ctx[1] & (1<<i)) {
1791 pci_dma_read(&xhci->pci_dev, ictx+32+(32*i), ep_ctx,
1792 sizeof(ep_ctx));
1793 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
1794 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
1795 ep_ctx[3], ep_ctx[4]);
1796 xhci_disable_ep(xhci, slotid, i);
1797 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
1798 if (res != CC_SUCCESS) {
1799 return res;
1800 }
1801 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
1802 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
1803 ep_ctx[3], ep_ctx[4]);
1804 pci_dma_write(&xhci->pci_dev, octx+(32*i), ep_ctx, sizeof(ep_ctx));
1805 }
1806 }
1807
1808 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
1809 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT;
1810 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT);
1811 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK <<
1812 SLOT_CONTEXT_ENTRIES_SHIFT);
1813 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1814 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1815
1816 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1817
1818 return CC_SUCCESS;
1819 }
1820
1821
1822 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid,
1823 uint64_t pictx)
1824 {
1825 dma_addr_t ictx, octx;
1826 uint32_t ictl_ctx[2];
1827 uint32_t iep0_ctx[5];
1828 uint32_t ep0_ctx[5];
1829 uint32_t islot_ctx[4];
1830 uint32_t slot_ctx[4];
1831
1832 trace_usb_xhci_slot_evaluate(slotid);
1833 assert(slotid >= 1 && slotid <= MAXSLOTS);
1834
1835 ictx = xhci_mask64(pictx);
1836 octx = xhci->slots[slotid-1].ctx;
1837
1838 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
1839 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
1840
1841 pci_dma_read(&xhci->pci_dev, ictx, ictl_ctx, sizeof(ictl_ctx));
1842
1843 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) {
1844 fprintf(stderr, "xhci: invalid input context control %08x %08x\n",
1845 ictl_ctx[0], ictl_ctx[1]);
1846 return CC_TRB_ERROR;
1847 }
1848
1849 if (ictl_ctx[1] & 0x1) {
1850 pci_dma_read(&xhci->pci_dev, ictx+32, islot_ctx, sizeof(islot_ctx));
1851
1852 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
1853 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]);
1854
1855 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1856
1857 slot_ctx[1] &= ~0xFFFF; /* max exit latency */
1858 slot_ctx[1] |= islot_ctx[1] & 0xFFFF;
1859 slot_ctx[2] &= ~0xFF00000; /* interrupter target */
1860 slot_ctx[2] |= islot_ctx[2] & 0xFF000000;
1861
1862 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1863 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1864
1865 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1866 }
1867
1868 if (ictl_ctx[1] & 0x2) {
1869 pci_dma_read(&xhci->pci_dev, ictx+64, iep0_ctx, sizeof(iep0_ctx));
1870
1871 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
1872 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2],
1873 iep0_ctx[3], iep0_ctx[4]);
1874
1875 pci_dma_read(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx));
1876
1877 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/
1878 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000;
1879
1880 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
1881 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
1882
1883 pci_dma_write(&xhci->pci_dev, octx+32, ep0_ctx, sizeof(ep0_ctx));
1884 }
1885
1886 return CC_SUCCESS;
1887 }
1888
1889 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid)
1890 {
1891 uint32_t slot_ctx[4];
1892 dma_addr_t octx;
1893 int i;
1894
1895 trace_usb_xhci_slot_reset(slotid);
1896 assert(slotid >= 1 && slotid <= MAXSLOTS);
1897
1898 octx = xhci->slots[slotid-1].ctx;
1899
1900 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
1901
1902 for (i = 2; i <= 31; i++) {
1903 if (xhci->slots[slotid-1].eps[i-1]) {
1904 xhci_disable_ep(xhci, slotid, i);
1905 }
1906 }
1907
1908 pci_dma_read(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1909 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
1910 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT;
1911 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
1912 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
1913 pci_dma_write(&xhci->pci_dev, octx, slot_ctx, sizeof(slot_ctx));
1914
1915 return CC_SUCCESS;
1916 }
1917
1918 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb)
1919 {
1920 unsigned int slotid;
1921 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK;
1922 if (slotid < 1 || slotid > MAXSLOTS) {
1923 fprintf(stderr, "xhci: bad slot id %d\n", slotid);
1924 event->ccode = CC_TRB_ERROR;
1925 return 0;
1926 } else if (!xhci->slots[slotid-1].enabled) {
1927 fprintf(stderr, "xhci: slot id %d not enabled\n", slotid);
1928 event->ccode = CC_SLOT_NOT_ENABLED_ERROR;
1929 return 0;
1930 }
1931 return slotid;
1932 }
1933
1934 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
1935 {
1936 dma_addr_t ctx;
1937 uint8_t bw_ctx[MAXPORTS+1];
1938
1939 DPRINTF("xhci_get_port_bandwidth()\n");
1940
1941 ctx = xhci_mask64(pctx);
1942
1943 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx);
1944
1945 /* TODO: actually implement real values here */
1946 bw_ctx[0] = 0;
1947 memset(&bw_ctx[1], 80, MAXPORTS); /* 80% */
1948 pci_dma_write(&xhci->pci_dev, ctx, bw_ctx, sizeof(bw_ctx));
1949
1950 return CC_SUCCESS;
1951 }
1952
1953 static uint32_t rotl(uint32_t v, unsigned count)
1954 {
1955 count &= 31;
1956 return (v << count) | (v >> (32 - count));
1957 }
1958
1959
1960 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
1961 {
1962 uint32_t val;
1963 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F));
1964 val += rotl(lo + 0x49434878, hi & 0x1F);
1965 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F);
1966 return ~val;
1967 }
1968
1969 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr)
1970 {
1971 uint32_t buf[8];
1972 uint32_t obuf[8];
1973 dma_addr_t paddr = xhci_mask64(addr);
1974
1975 pci_dma_read(&xhci->pci_dev, paddr, &buf, 32);
1976
1977 memcpy(obuf, buf, sizeof(obuf));
1978
1979 if ((buf[0] & 0xff) == 2) {
1980 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3];
1981 obuf[0] |= (buf[2] * buf[3]) & 0xff;
1982 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3];
1983 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3];
1984 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3];
1985 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3];
1986 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3];
1987 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956;
1988 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593;
1989 }
1990
1991 pci_dma_write(&xhci->pci_dev, paddr, &obuf, 32);
1992 }
1993
1994 static void xhci_process_commands(XHCIState *xhci)
1995 {
1996 XHCITRB trb;
1997 TRBType type;
1998 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS};
1999 dma_addr_t addr;
2000 unsigned int i, slotid = 0;
2001
2002 DPRINTF("xhci_process_commands()\n");
2003 if (!xhci_running(xhci)) {
2004 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2005 return;
2006 }
2007
2008 xhci->crcr_low |= CRCR_CRR;
2009
2010 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {
2011 event.ptr = addr;
2012 switch (type) {
2013 case CR_ENABLE_SLOT:
2014 for (i = 0; i < MAXSLOTS; i++) {
2015 if (!xhci->slots[i].enabled) {
2016 break;
2017 }
2018 }
2019 if (i >= MAXSLOTS) {
2020 fprintf(stderr, "xhci: no device slots available\n");
2021 event.ccode = CC_NO_SLOTS_ERROR;
2022 } else {
2023 slotid = i+1;
2024 event.ccode = xhci_enable_slot(xhci, slotid);
2025 }
2026 break;
2027 case CR_DISABLE_SLOT:
2028 slotid = xhci_get_slot(xhci, &event, &trb);
2029 if (slotid) {
2030 event.ccode = xhci_disable_slot(xhci, slotid);
2031 }
2032 break;
2033 case CR_ADDRESS_DEVICE:
2034 slotid = xhci_get_slot(xhci, &event, &trb);
2035 if (slotid) {
2036 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter,
2037 trb.control & TRB_CR_BSR);
2038 }
2039 break;
2040 case CR_CONFIGURE_ENDPOINT:
2041 slotid = xhci_get_slot(xhci, &event, &trb);
2042 if (slotid) {
2043 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter,
2044 trb.control & TRB_CR_DC);
2045 }
2046 break;
2047 case CR_EVALUATE_CONTEXT:
2048 slotid = xhci_get_slot(xhci, &event, &trb);
2049 if (slotid) {
2050 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter);
2051 }
2052 break;
2053 case CR_STOP_ENDPOINT:
2054 slotid = xhci_get_slot(xhci, &event, &trb);
2055 if (slotid) {
2056 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2057 & TRB_CR_EPID_MASK;
2058 event.ccode = xhci_stop_ep(xhci, slotid, epid);
2059 }
2060 break;
2061 case CR_RESET_ENDPOINT:
2062 slotid = xhci_get_slot(xhci, &event, &trb);
2063 if (slotid) {
2064 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2065 & TRB_CR_EPID_MASK;
2066 event.ccode = xhci_reset_ep(xhci, slotid, epid);
2067 }
2068 break;
2069 case CR_SET_TR_DEQUEUE:
2070 slotid = xhci_get_slot(xhci, &event, &trb);
2071 if (slotid) {
2072 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2073 & TRB_CR_EPID_MASK;
2074 event.ccode = xhci_set_ep_dequeue(xhci, slotid, epid,
2075 trb.parameter);
2076 }
2077 break;
2078 case CR_RESET_DEVICE:
2079 slotid = xhci_get_slot(xhci, &event, &trb);
2080 if (slotid) {
2081 event.ccode = xhci_reset_slot(xhci, slotid);
2082 }
2083 break;
2084 case CR_GET_PORT_BANDWIDTH:
2085 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter);
2086 break;
2087 case CR_VENDOR_VIA_CHALLENGE_RESPONSE:
2088 xhci_via_challenge(xhci, trb.parameter);
2089 break;
2090 case CR_VENDOR_NEC_FIRMWARE_REVISION:
2091 event.type = 48; /* NEC reply */
2092 event.length = 0x3025;
2093 break;
2094 case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
2095 {
2096 uint32_t chi = trb.parameter >> 32;
2097 uint32_t clo = trb.parameter;
2098 uint32_t val = xhci_nec_challenge(chi, clo);
2099 event.length = val & 0xFFFF;
2100 event.epid = val >> 16;
2101 slotid = val >> 24;
2102 event.type = 48; /* NEC reply */
2103 }
2104 break;
2105 default:
2106 fprintf(stderr, "xhci: unimplemented command %d\n", type);
2107 event.ccode = CC_TRB_ERROR;
2108 break;
2109 }
2110 event.slotid = slotid;
2111 xhci_event(xhci, &event);
2112 }
2113 }
2114
2115 static void xhci_update_port(XHCIState *xhci, XHCIPort *port, int is_detach)
2116 {
2117 int nr = port->port.index + 1;
2118
2119 port->portsc = PORTSC_PP;
2120 if (port->port.dev && port->port.dev->attached && !is_detach) {
2121 port->portsc |= PORTSC_CCS;
2122 switch (port->port.dev->speed) {
2123 case USB_SPEED_LOW:
2124 port->portsc |= PORTSC_SPEED_LOW;
2125 break;
2126 case USB_SPEED_FULL:
2127 port->portsc |= PORTSC_SPEED_FULL;
2128 break;
2129 case USB_SPEED_HIGH:
2130 port->portsc |= PORTSC_SPEED_HIGH;
2131 break;
2132 }
2133 }
2134
2135 if (xhci_running(xhci)) {
2136 port->portsc |= PORTSC_CSC;
2137 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, nr << 24};
2138 xhci_event(xhci, &ev);
2139 DPRINTF("xhci: port change event for port %d\n", nr);
2140 }
2141 }
2142
2143 static void xhci_reset(DeviceState *dev)
2144 {
2145 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev.qdev, dev);
2146 int i;
2147
2148 trace_usb_xhci_reset();
2149 if (!(xhci->usbsts & USBSTS_HCH)) {
2150 fprintf(stderr, "xhci: reset while running!\n");
2151 }
2152
2153 xhci->usbcmd = 0;
2154 xhci->usbsts = USBSTS_HCH;
2155 xhci->dnctrl = 0;
2156 xhci->crcr_low = 0;
2157 xhci->crcr_high = 0;
2158 xhci->dcbaap_low = 0;
2159 xhci->dcbaap_high = 0;
2160 xhci->config = 0;
2161 xhci->devaddr = 2;
2162
2163 for (i = 0; i < MAXSLOTS; i++) {
2164 xhci_disable_slot(xhci, i+1);
2165 }
2166
2167 for (i = 0; i < MAXPORTS; i++) {
2168 xhci_update_port(xhci, xhci->ports + i, 0);
2169 }
2170
2171 xhci->iman = 0;
2172 xhci->imod = 0;
2173 xhci->erstsz = 0;
2174 xhci->erstba_low = 0;
2175 xhci->erstba_high = 0;
2176 xhci->erdp_low = 0;
2177 xhci->erdp_high = 0;
2178
2179 xhci->er_ep_idx = 0;
2180 xhci->er_pcs = 1;
2181 xhci->er_full = 0;
2182 xhci->ev_buffer_put = 0;
2183 xhci->ev_buffer_get = 0;
2184
2185 xhci->mfindex_start = qemu_get_clock_ns(vm_clock);
2186 xhci_mfwrap_update(xhci);
2187 }
2188
2189 static uint32_t xhci_cap_read(XHCIState *xhci, uint32_t reg)
2190 {
2191 uint32_t ret;
2192
2193 switch (reg) {
2194 case 0x00: /* HCIVERSION, CAPLENGTH */
2195 ret = 0x01000000 | LEN_CAP;
2196 break;
2197 case 0x04: /* HCSPARAMS 1 */
2198 ret = (MAXPORTS<<24) | (MAXINTRS<<8) | MAXSLOTS;
2199 break;
2200 case 0x08: /* HCSPARAMS 2 */
2201 ret = 0x0000000f;
2202 break;
2203 case 0x0c: /* HCSPARAMS 3 */
2204 ret = 0x00000000;
2205 break;
2206 case 0x10: /* HCCPARAMS */
2207 if (sizeof(dma_addr_t) == 4) {
2208 ret = 0x00081000;
2209 } else {
2210 ret = 0x00081001;
2211 }
2212 break;
2213 case 0x14: /* DBOFF */
2214 ret = OFF_DOORBELL;
2215 break;
2216 case 0x18: /* RTSOFF */
2217 ret = OFF_RUNTIME;
2218 break;
2219
2220 /* extended capabilities */
2221 case 0x20: /* Supported Protocol:00 */
2222 ret = 0x02000402; /* USB 2.0 */
2223 break;
2224 case 0x24: /* Supported Protocol:04 */
2225 ret = 0x20425455; /* "USB " */
2226 break;
2227 case 0x28: /* Supported Protocol:08 */
2228 ret = 0x00000001 | (USB2_PORTS<<8);
2229 break;
2230 case 0x2c: /* Supported Protocol:0c */
2231 ret = 0x00000000; /* reserved */
2232 break;
2233 case 0x30: /* Supported Protocol:00 */
2234 ret = 0x03000002; /* USB 3.0 */
2235 break;
2236 case 0x34: /* Supported Protocol:04 */
2237 ret = 0x20425455; /* "USB " */
2238 break;
2239 case 0x38: /* Supported Protocol:08 */
2240 ret = 0x00000000 | (USB2_PORTS+1) | (USB3_PORTS<<8);
2241 break;
2242 case 0x3c: /* Supported Protocol:0c */
2243 ret = 0x00000000; /* reserved */
2244 break;
2245 default:
2246 fprintf(stderr, "xhci_cap_read: reg %d unimplemented\n", reg);
2247 ret = 0;
2248 }
2249
2250 trace_usb_xhci_cap_read(reg, ret);
2251 return ret;
2252 }
2253
2254 static uint32_t xhci_port_read(XHCIState *xhci, uint32_t reg)
2255 {
2256 uint32_t port = reg >> 4;
2257 uint32_t ret;
2258
2259 if (port >= MAXPORTS) {
2260 fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port);
2261 ret = 0;
2262 goto out;
2263 }
2264
2265 switch (reg & 0xf) {
2266 case 0x00: /* PORTSC */
2267 ret = xhci->ports[port].portsc;
2268 break;
2269 case 0x04: /* PORTPMSC */
2270 case 0x08: /* PORTLI */
2271 ret = 0;
2272 break;
2273 case 0x0c: /* reserved */
2274 default:
2275 fprintf(stderr, "xhci_port_read (port %d): reg 0x%x unimplemented\n",
2276 port, reg);
2277 ret = 0;
2278 }
2279
2280 out:
2281 trace_usb_xhci_port_read(port, reg & 0x0f, ret);
2282 return ret;
2283 }
2284
2285 static void xhci_port_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2286 {
2287 uint32_t port = reg >> 4;
2288 uint32_t portsc;
2289
2290 trace_usb_xhci_port_write(port, reg & 0x0f, val);
2291
2292 if (port >= MAXPORTS) {
2293 fprintf(stderr, "xhci_port_read: port %d out of bounds\n", port);
2294 return;
2295 }
2296
2297 switch (reg & 0xf) {
2298 case 0x00: /* PORTSC */
2299 portsc = xhci->ports[port].portsc;
2300 /* write-1-to-clear bits*/
2301 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC|
2302 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC));
2303 if (val & PORTSC_LWS) {
2304 /* overwrite PLS only when LWS=1 */
2305 portsc &= ~(PORTSC_PLS_MASK << PORTSC_PLS_SHIFT);
2306 portsc |= val & (PORTSC_PLS_MASK << PORTSC_PLS_SHIFT);
2307 }
2308 /* read/write bits */
2309 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE);
2310 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE));
2311 /* write-1-to-start bits */
2312 if (val & PORTSC_PR) {
2313 DPRINTF("xhci: port %d reset\n", port);
2314 usb_device_reset(xhci->ports[port].port.dev);
2315 portsc |= PORTSC_PRC | PORTSC_PED;
2316 }
2317 xhci->ports[port].portsc = portsc;
2318 break;
2319 case 0x04: /* PORTPMSC */
2320 case 0x08: /* PORTLI */
2321 default:
2322 fprintf(stderr, "xhci_port_write (port %d): reg 0x%x unimplemented\n",
2323 port, reg);
2324 }
2325 }
2326
2327 static uint32_t xhci_oper_read(XHCIState *xhci, uint32_t reg)
2328 {
2329 uint32_t ret;
2330
2331 if (reg >= 0x400) {
2332 return xhci_port_read(xhci, reg - 0x400);
2333 }
2334
2335 switch (reg) {
2336 case 0x00: /* USBCMD */
2337 ret = xhci->usbcmd;
2338 break;
2339 case 0x04: /* USBSTS */
2340 ret = xhci->usbsts;
2341 break;
2342 case 0x08: /* PAGESIZE */
2343 ret = 1; /* 4KiB */
2344 break;
2345 case 0x14: /* DNCTRL */
2346 ret = xhci->dnctrl;
2347 break;
2348 case 0x18: /* CRCR low */
2349 ret = xhci->crcr_low & ~0xe;
2350 break;
2351 case 0x1c: /* CRCR high */
2352 ret = xhci->crcr_high;
2353 break;
2354 case 0x30: /* DCBAAP low */
2355 ret = xhci->dcbaap_low;
2356 break;
2357 case 0x34: /* DCBAAP high */
2358 ret = xhci->dcbaap_high;
2359 break;
2360 case 0x38: /* CONFIG */
2361 ret = xhci->config;
2362 break;
2363 default:
2364 fprintf(stderr, "xhci_oper_read: reg 0x%x unimplemented\n", reg);
2365 ret = 0;
2366 }
2367
2368 trace_usb_xhci_oper_read(reg, ret);
2369 return ret;
2370 }
2371
2372 static void xhci_oper_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2373 {
2374 if (reg >= 0x400) {
2375 xhci_port_write(xhci, reg - 0x400, val);
2376 return;
2377 }
2378
2379 trace_usb_xhci_oper_write(reg, val);
2380
2381 switch (reg) {
2382 case 0x00: /* USBCMD */
2383 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {
2384 xhci_run(xhci);
2385 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) {
2386 xhci_stop(xhci);
2387 }
2388 xhci->usbcmd = val & 0xc0f;
2389 xhci_mfwrap_update(xhci);
2390 if (val & USBCMD_HCRST) {
2391 xhci_reset(&xhci->pci_dev.qdev);
2392 }
2393 xhci_irq_update(xhci);
2394 break;
2395
2396 case 0x04: /* USBSTS */
2397 /* these bits are write-1-to-clear */
2398 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
2399 xhci_irq_update(xhci);
2400 break;
2401
2402 case 0x14: /* DNCTRL */
2403 xhci->dnctrl = val & 0xffff;
2404 break;
2405 case 0x18: /* CRCR low */
2406 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
2407 break;
2408 case 0x1c: /* CRCR high */
2409 xhci->crcr_high = val;
2410 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) {
2411 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED};
2412 xhci->crcr_low &= ~CRCR_CRR;
2413 xhci_event(xhci, &event);
2414 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low);
2415 } else {
2416 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
2417 xhci_ring_init(xhci, &xhci->cmd_ring, base);
2418 }
2419 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS);
2420 break;
2421 case 0x30: /* DCBAAP low */
2422 xhci->dcbaap_low = val & 0xffffffc0;
2423 break;
2424 case 0x34: /* DCBAAP high */
2425 xhci->dcbaap_high = val;
2426 break;
2427 case 0x38: /* CONFIG */
2428 xhci->config = val & 0xff;
2429 break;
2430 default:
2431 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
2432 }
2433 }
2434
2435 static uint32_t xhci_runtime_read(XHCIState *xhci, uint32_t reg)
2436 {
2437 uint32_t ret;
2438
2439 switch (reg) {
2440 case 0x00: /* MFINDEX */
2441 ret = xhci_mfindex_get(xhci) & 0x3fff;
2442 break;
2443 case 0x20: /* IMAN */
2444 ret = xhci->iman;
2445 break;
2446 case 0x24: /* IMOD */
2447 ret = xhci->imod;
2448 break;
2449 case 0x28: /* ERSTSZ */
2450 ret = xhci->erstsz;
2451 break;
2452 case 0x30: /* ERSTBA low */
2453 ret = xhci->erstba_low;
2454 break;
2455 case 0x34: /* ERSTBA high */
2456 ret = xhci->erstba_high;
2457 break;
2458 case 0x38: /* ERDP low */
2459 ret = xhci->erdp_low;
2460 break;
2461 case 0x3c: /* ERDP high */
2462 ret = xhci->erdp_high;
2463 break;
2464 default:
2465 fprintf(stderr, "xhci_runtime_read: reg 0x%x unimplemented\n", reg);
2466 ret = 0;
2467 }
2468
2469 trace_usb_xhci_runtime_read(reg, ret);
2470 return ret;
2471 }
2472
2473 static void xhci_runtime_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2474 {
2475 trace_usb_xhci_runtime_read(reg, val);
2476
2477 switch (reg) {
2478 case 0x20: /* IMAN */
2479 if (val & IMAN_IP) {
2480 xhci->iman &= ~IMAN_IP;
2481 }
2482 xhci->iman &= ~IMAN_IE;
2483 xhci->iman |= val & IMAN_IE;
2484 xhci_irq_update(xhci);
2485 break;
2486 case 0x24: /* IMOD */
2487 xhci->imod = val;
2488 break;
2489 case 0x28: /* ERSTSZ */
2490 xhci->erstsz = val & 0xffff;
2491 break;
2492 case 0x30: /* ERSTBA low */
2493 /* XXX NEC driver bug: it doesn't align this to 64 bytes
2494 xhci->erstba_low = val & 0xffffffc0; */
2495 xhci->erstba_low = val & 0xfffffff0;
2496 break;
2497 case 0x34: /* ERSTBA high */
2498 xhci->erstba_high = val;
2499 xhci_er_reset(xhci);
2500 break;
2501 case 0x38: /* ERDP low */
2502 if (val & ERDP_EHB) {
2503 xhci->erdp_low &= ~ERDP_EHB;
2504 }
2505 xhci->erdp_low = (val & ~ERDP_EHB) | (xhci->erdp_low & ERDP_EHB);
2506 break;
2507 case 0x3c: /* ERDP high */
2508 xhci->erdp_high = val;
2509 xhci_events_update(xhci);
2510 break;
2511 default:
2512 fprintf(stderr, "xhci_oper_write: reg 0x%x unimplemented\n", reg);
2513 }
2514 }
2515
2516 static uint32_t xhci_doorbell_read(XHCIState *xhci, uint32_t reg)
2517 {
2518 /* doorbells always read as 0 */
2519 trace_usb_xhci_doorbell_read(reg, 0);
2520 return 0;
2521 }
2522
2523 static void xhci_doorbell_write(XHCIState *xhci, uint32_t reg, uint32_t val)
2524 {
2525 trace_usb_xhci_doorbell_write(reg, val);
2526
2527 if (!xhci_running(xhci)) {
2528 fprintf(stderr, "xhci: wrote doorbell while xHC stopped or paused\n");
2529 return;
2530 }
2531
2532 reg >>= 2;
2533
2534 if (reg == 0) {
2535 if (val == 0) {
2536 xhci_process_commands(xhci);
2537 } else {
2538 fprintf(stderr, "xhci: bad doorbell 0 write: 0x%x\n", val);
2539 }
2540 } else {
2541 if (reg > MAXSLOTS) {
2542 fprintf(stderr, "xhci: bad doorbell %d\n", reg);
2543 } else if (val > 31) {
2544 fprintf(stderr, "xhci: bad doorbell %d write: 0x%x\n", reg, val);
2545 } else {
2546 xhci_kick_ep(xhci, reg, val);
2547 }
2548 }
2549 }
2550
2551 static uint64_t xhci_mem_read(void *ptr, target_phys_addr_t addr,
2552 unsigned size)
2553 {
2554 XHCIState *xhci = ptr;
2555
2556 /* Only aligned reads are allowed on xHCI */
2557 if (addr & 3) {
2558 fprintf(stderr, "xhci_mem_read: Mis-aligned read\n");
2559 return 0;
2560 }
2561
2562 if (addr < LEN_CAP) {
2563 return xhci_cap_read(xhci, addr);
2564 } else if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) {
2565 return xhci_oper_read(xhci, addr - OFF_OPER);
2566 } else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) {
2567 return xhci_runtime_read(xhci, addr - OFF_RUNTIME);
2568 } else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) {
2569 return xhci_doorbell_read(xhci, addr - OFF_DOORBELL);
2570 } else {
2571 fprintf(stderr, "xhci_mem_read: Bad offset %x\n", (int)addr);
2572 return 0;
2573 }
2574 }
2575
2576 static void xhci_mem_write(void *ptr, target_phys_addr_t addr,
2577 uint64_t val, unsigned size)
2578 {
2579 XHCIState *xhci = ptr;
2580
2581 /* Only aligned writes are allowed on xHCI */
2582 if (addr & 3) {
2583 fprintf(stderr, "xhci_mem_write: Mis-aligned write\n");
2584 return;
2585 }
2586
2587 if (addr >= OFF_OPER && addr < (OFF_OPER + LEN_OPER)) {
2588 xhci_oper_write(xhci, addr - OFF_OPER, val);
2589 } else if (addr >= OFF_RUNTIME && addr < (OFF_RUNTIME + LEN_RUNTIME)) {
2590 xhci_runtime_write(xhci, addr - OFF_RUNTIME, val);
2591 } else if (addr >= OFF_DOORBELL && addr < (OFF_DOORBELL + LEN_DOORBELL)) {
2592 xhci_doorbell_write(xhci, addr - OFF_DOORBELL, val);
2593 } else {
2594 fprintf(stderr, "xhci_mem_write: Bad offset %x\n", (int)addr);
2595 }
2596 }
2597
2598 static const MemoryRegionOps xhci_mem_ops = {
2599 .read = xhci_mem_read,
2600 .write = xhci_mem_write,
2601 .valid.min_access_size = 4,
2602 .valid.max_access_size = 4,
2603 .endianness = DEVICE_LITTLE_ENDIAN,
2604 };
2605
2606 static void xhci_attach(USBPort *usbport)
2607 {
2608 XHCIState *xhci = usbport->opaque;
2609 XHCIPort *port = &xhci->ports[usbport->index];
2610
2611 xhci_update_port(xhci, port, 0);
2612 }
2613
2614 static void xhci_detach(USBPort *usbport)
2615 {
2616 XHCIState *xhci = usbport->opaque;
2617 XHCIPort *port = &xhci->ports[usbport->index];
2618
2619 xhci_update_port(xhci, port, 1);
2620 }
2621
2622 static void xhci_wakeup(USBPort *usbport)
2623 {
2624 XHCIState *xhci = usbport->opaque;
2625 XHCIPort *port = &xhci->ports[usbport->index];
2626 int nr = port->port.index + 1;
2627 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, nr << 24};
2628 uint32_t pls;
2629
2630 pls = (port->portsc >> PORTSC_PLS_SHIFT) & PORTSC_PLS_MASK;
2631 if (pls != 3) {
2632 return;
2633 }
2634 port->portsc |= 0xf << PORTSC_PLS_SHIFT;
2635 if (port->portsc & PORTSC_PLC) {
2636 return;
2637 }
2638 port->portsc |= PORTSC_PLC;
2639 xhci_event(xhci, &ev);
2640 }
2641
2642 static void xhci_complete(USBPort *port, USBPacket *packet)
2643 {
2644 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet);
2645
2646 xhci_complete_packet(xfer, packet->result);
2647 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid);
2648 }
2649
2650 static void xhci_child_detach(USBPort *port, USBDevice *child)
2651 {
2652 FIXME();
2653 }
2654
2655 static USBPortOps xhci_port_ops = {
2656 .attach = xhci_attach,
2657 .detach = xhci_detach,
2658 .wakeup = xhci_wakeup,
2659 .complete = xhci_complete,
2660 .child_detach = xhci_child_detach,
2661 };
2662
2663 static int xhci_find_slotid(XHCIState *xhci, USBDevice *dev)
2664 {
2665 XHCISlot *slot;
2666 int slotid;
2667
2668 for (slotid = 1; slotid <= MAXSLOTS; slotid++) {
2669 slot = &xhci->slots[slotid-1];
2670 if (slot->devaddr == dev->addr) {
2671 return slotid;
2672 }
2673 }
2674 return 0;
2675 }
2676
2677 static int xhci_find_epid(USBEndpoint *ep)
2678 {
2679 if (ep->nr == 0) {
2680 return 1;
2681 }
2682 if (ep->pid == USB_TOKEN_IN) {
2683 return ep->nr * 2 + 1;
2684 } else {
2685 return ep->nr * 2;
2686 }
2687 }
2688
2689 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep)
2690 {
2691 XHCIState *xhci = container_of(bus, XHCIState, bus);
2692 int slotid;
2693
2694 DPRINTF("%s\n", __func__);
2695 slotid = xhci_find_slotid(xhci, ep->dev);
2696 if (slotid == 0 || !xhci->slots[slotid-1].enabled) {
2697 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr);
2698 return;
2699 }
2700 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep));
2701 }
2702
2703 static USBBusOps xhci_bus_ops = {
2704 .wakeup_endpoint = xhci_wakeup_endpoint,
2705 };
2706
2707 static void usb_xhci_init(XHCIState *xhci, DeviceState *dev)
2708 {
2709 int i;
2710
2711 xhci->usbsts = USBSTS_HCH;
2712
2713 usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev);
2714
2715 for (i = 0; i < MAXPORTS; i++) {
2716 memset(&xhci->ports[i], 0, sizeof(xhci->ports[i]));
2717 usb_register_port(&xhci->bus, &xhci->ports[i].port, xhci, i,
2718 &xhci_port_ops,
2719 USB_SPEED_MASK_LOW |
2720 USB_SPEED_MASK_FULL |
2721 USB_SPEED_MASK_HIGH);
2722 }
2723 for (i = 0; i < MAXSLOTS; i++) {
2724 xhci->slots[i].enabled = 0;
2725 }
2726 }
2727
2728 static int usb_xhci_initfn(struct PCIDevice *dev)
2729 {
2730 int ret;
2731
2732 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev);
2733
2734 xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */
2735 xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
2736 xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10;
2737 xhci->pci_dev.config[0x60] = 0x30; /* release number */
2738
2739 usb_xhci_init(xhci, &dev->qdev);
2740
2741 xhci->mfwrap_timer = qemu_new_timer_ns(vm_clock, xhci_mfwrap_timer, xhci);
2742
2743 xhci->irq = xhci->pci_dev.irq[0];
2744
2745 memory_region_init_io(&xhci->mem, &xhci_mem_ops, xhci,
2746 "xhci", LEN_REGS);
2747 pci_register_bar(&xhci->pci_dev, 0,
2748 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
2749 &xhci->mem);
2750
2751 ret = pcie_cap_init(&xhci->pci_dev, 0xa0, PCI_EXP_TYPE_ENDPOINT, 0);
2752 assert(ret >= 0);
2753
2754 if (xhci->msi) {
2755 ret = msi_init(&xhci->pci_dev, 0x70, 1, true, false);
2756 assert(ret >= 0);
2757 }
2758
2759 return 0;
2760 }
2761
2762 static void xhci_write_config(PCIDevice *dev, uint32_t addr, uint32_t val,
2763 int len)
2764 {
2765 XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev);
2766
2767 pci_default_write_config(dev, addr, val, len);
2768 if (xhci->msi) {
2769 msi_write_config(dev, addr, val, len);
2770 }
2771 }
2772
2773 static const VMStateDescription vmstate_xhci = {
2774 .name = "xhci",
2775 .unmigratable = 1,
2776 };
2777
2778 static Property xhci_properties[] = {
2779 DEFINE_PROP_UINT32("msi", XHCIState, msi, 0),
2780 DEFINE_PROP_END_OF_LIST(),
2781 };
2782
2783 static void xhci_class_init(ObjectClass *klass, void *data)
2784 {
2785 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2786 DeviceClass *dc = DEVICE_CLASS(klass);
2787
2788 dc->vmsd = &vmstate_xhci;
2789 dc->props = xhci_properties;
2790 dc->reset = xhci_reset;
2791 k->init = usb_xhci_initfn;
2792 k->vendor_id = PCI_VENDOR_ID_NEC;
2793 k->device_id = PCI_DEVICE_ID_NEC_UPD720200;
2794 k->class_id = PCI_CLASS_SERIAL_USB;
2795 k->revision = 0x03;
2796 k->is_express = 1;
2797 k->config_write = xhci_write_config;
2798 }
2799
2800 static TypeInfo xhci_info = {
2801 .name = "nec-usb-xhci",
2802 .parent = TYPE_PCI_DEVICE,
2803 .instance_size = sizeof(XHCIState),
2804 .class_init = xhci_class_init,
2805 };
2806
2807 static void xhci_register_types(void)
2808 {
2809 type_register_static(&xhci_info);
2810 }
2811
2812 type_init(xhci_register_types)
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