]> git.proxmox.com Git - mirror_qemu.git/blob - hw/usb/hcd-xhci.c
projects / mirror_qemu.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging
[mirror_qemu.git] / hw / usb / hcd-xhci.c
1 /*
2 * USB xHCI controller emulation
3 *
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21 #include "hw/hw.h"
22 #include "qemu/timer.h"
23 #include "hw/usb.h"
24 #include "hw/pci/pci.h"
25 #include "hw/pci/msi.h"
26 #include "hw/pci/msix.h"
27 #include "trace.h"
28
29 //#define DEBUG_XHCI
30 //#define DEBUG_DATA
31
32 #ifdef DEBUG_XHCI
33 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
34 #else
35 #define DPRINTF(...) do {} while (0)
36 #endif
37 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \
38 __func__, __LINE__, _msg); abort(); } while (0)
39
40 #define MAXPORTS_2 15
41 #define MAXPORTS_3 15
42
43 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3)
44 #define MAXSLOTS 64
45 #define MAXINTRS 16
46
47 #define TD_QUEUE 24
48
49 /* Very pessimistic, let's hope it's enough for all cases */
50 #define EV_QUEUE (((3*TD_QUEUE)+16)*MAXSLOTS)
51 /* Do not deliver ER Full events. NEC's driver does some things not bound
52 * to the specs when it gets them */
53 #define ER_FULL_HACK
54
55 #define LEN_CAP 0x40
56 #define LEN_OPER (0x400 + 0x10 * MAXPORTS)
57 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20)
58 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
59
60 #define OFF_OPER LEN_CAP
61 #define OFF_RUNTIME 0x1000
62 #define OFF_DOORBELL 0x2000
63 #define OFF_MSIX_TABLE 0x3000
64 #define OFF_MSIX_PBA 0x3800
65 /* must be power of 2 */
66 #define LEN_REGS 0x4000
67
68 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
69 #error Increase OFF_RUNTIME
70 #endif
71 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
72 #error Increase OFF_DOORBELL
73 #endif
74 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
75 # error Increase LEN_REGS
76 #endif
77
78 /* bit definitions */
79 #define USBCMD_RS (1<<0)
80 #define USBCMD_HCRST (1<<1)
81 #define USBCMD_INTE (1<<2)
82 #define USBCMD_HSEE (1<<3)
83 #define USBCMD_LHCRST (1<<7)
84 #define USBCMD_CSS (1<<8)
85 #define USBCMD_CRS (1<<9)
86 #define USBCMD_EWE (1<<10)
87 #define USBCMD_EU3S (1<<11)
88
89 #define USBSTS_HCH (1<<0)
90 #define USBSTS_HSE (1<<2)
91 #define USBSTS_EINT (1<<3)
92 #define USBSTS_PCD (1<<4)
93 #define USBSTS_SSS (1<<8)
94 #define USBSTS_RSS (1<<9)
95 #define USBSTS_SRE (1<<10)
96 #define USBSTS_CNR (1<<11)
97 #define USBSTS_HCE (1<<12)
98
99
100 #define PORTSC_CCS (1<<0)
101 #define PORTSC_PED (1<<1)
102 #define PORTSC_OCA (1<<3)
103 #define PORTSC_PR (1<<4)
104 #define PORTSC_PLS_SHIFT 5
105 #define PORTSC_PLS_MASK 0xf
106 #define PORTSC_PP (1<<9)
107 #define PORTSC_SPEED_SHIFT 10
108 #define PORTSC_SPEED_MASK 0xf
109 #define PORTSC_SPEED_FULL (1<<10)
110 #define PORTSC_SPEED_LOW (2<<10)
111 #define PORTSC_SPEED_HIGH (3<<10)
112 #define PORTSC_SPEED_SUPER (4<<10)
113 #define PORTSC_PIC_SHIFT 14
114 #define PORTSC_PIC_MASK 0x3
115 #define PORTSC_LWS (1<<16)
116 #define PORTSC_CSC (1<<17)
117 #define PORTSC_PEC (1<<18)
118 #define PORTSC_WRC (1<<19)
119 #define PORTSC_OCC (1<<20)
120 #define PORTSC_PRC (1<<21)
121 #define PORTSC_PLC (1<<22)
122 #define PORTSC_CEC (1<<23)
123 #define PORTSC_CAS (1<<24)
124 #define PORTSC_WCE (1<<25)
125 #define PORTSC_WDE (1<<26)
126 #define PORTSC_WOE (1<<27)
127 #define PORTSC_DR (1<<30)
128 #define PORTSC_WPR (1<<31)
129
130 #define CRCR_RCS (1<<0)
131 #define CRCR_CS (1<<1)
132 #define CRCR_CA (1<<2)
133 #define CRCR_CRR (1<<3)
134
135 #define IMAN_IP (1<<0)
136 #define IMAN_IE (1<<1)
137
138 #define ERDP_EHB (1<<3)
139
140 #define TRB_SIZE 16
141 typedef struct XHCITRB {
142 uint64_t parameter;
143 uint32_t status;
144 uint32_t control;
145 dma_addr_t addr;
146 bool ccs;
147 } XHCITRB;
148
149 enum {
150 PLS_U0 = 0,
151 PLS_U1 = 1,
152 PLS_U2 = 2,
153 PLS_U3 = 3,
154 PLS_DISABLED = 4,
155 PLS_RX_DETECT = 5,
156 PLS_INACTIVE = 6,
157 PLS_POLLING = 7,
158 PLS_RECOVERY = 8,
159 PLS_HOT_RESET = 9,
160 PLS_COMPILANCE_MODE = 10,
161 PLS_TEST_MODE = 11,
162 PLS_RESUME = 15,
163 };
164
165 typedef enum TRBType {
166 TRB_RESERVED = 0,
167 TR_NORMAL,
168 TR_SETUP,
169 TR_DATA,
170 TR_STATUS,
171 TR_ISOCH,
172 TR_LINK,
173 TR_EVDATA,
174 TR_NOOP,
175 CR_ENABLE_SLOT,
176 CR_DISABLE_SLOT,
177 CR_ADDRESS_DEVICE,
178 CR_CONFIGURE_ENDPOINT,
179 CR_EVALUATE_CONTEXT,
180 CR_RESET_ENDPOINT,
181 CR_STOP_ENDPOINT,
182 CR_SET_TR_DEQUEUE,
183 CR_RESET_DEVICE,
184 CR_FORCE_EVENT,
185 CR_NEGOTIATE_BW,
186 CR_SET_LATENCY_TOLERANCE,
187 CR_GET_PORT_BANDWIDTH,
188 CR_FORCE_HEADER,
189 CR_NOOP,
190 ER_TRANSFER = 32,
191 ER_COMMAND_COMPLETE,
192 ER_PORT_STATUS_CHANGE,
193 ER_BANDWIDTH_REQUEST,
194 ER_DOORBELL,
195 ER_HOST_CONTROLLER,
196 ER_DEVICE_NOTIFICATION,
197 ER_MFINDEX_WRAP,
198 /* vendor specific bits */
199 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48,
200 CR_VENDOR_NEC_FIRMWARE_REVISION = 49,
201 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50,
202 } TRBType;
203
204 #define CR_LINK TR_LINK
205
206 typedef enum TRBCCode {
207 CC_INVALID = 0,
208 CC_SUCCESS,
209 CC_DATA_BUFFER_ERROR,
210 CC_BABBLE_DETECTED,
211 CC_USB_TRANSACTION_ERROR,
212 CC_TRB_ERROR,
213 CC_STALL_ERROR,
214 CC_RESOURCE_ERROR,
215 CC_BANDWIDTH_ERROR,
216 CC_NO_SLOTS_ERROR,
217 CC_INVALID_STREAM_TYPE_ERROR,
218 CC_SLOT_NOT_ENABLED_ERROR,
219 CC_EP_NOT_ENABLED_ERROR,
220 CC_SHORT_PACKET,
221 CC_RING_UNDERRUN,
222 CC_RING_OVERRUN,
223 CC_VF_ER_FULL,
224 CC_PARAMETER_ERROR,
225 CC_BANDWIDTH_OVERRUN,
226 CC_CONTEXT_STATE_ERROR,
227 CC_NO_PING_RESPONSE_ERROR,
228 CC_EVENT_RING_FULL_ERROR,
229 CC_INCOMPATIBLE_DEVICE_ERROR,
230 CC_MISSED_SERVICE_ERROR,
231 CC_COMMAND_RING_STOPPED,
232 CC_COMMAND_ABORTED,
233 CC_STOPPED,
234 CC_STOPPED_LENGTH_INVALID,
235 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29,
236 CC_ISOCH_BUFFER_OVERRUN = 31,
237 CC_EVENT_LOST_ERROR,
238 CC_UNDEFINED_ERROR,
239 CC_INVALID_STREAM_ID_ERROR,
240 CC_SECONDARY_BANDWIDTH_ERROR,
241 CC_SPLIT_TRANSACTION_ERROR
242 } TRBCCode;
243
244 #define TRB_C (1<<0)
245 #define TRB_TYPE_SHIFT 10
246 #define TRB_TYPE_MASK 0x3f
247 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
248
249 #define TRB_EV_ED (1<<2)
250
251 #define TRB_TR_ENT (1<<1)
252 #define TRB_TR_ISP (1<<2)
253 #define TRB_TR_NS (1<<3)
254 #define TRB_TR_CH (1<<4)
255 #define TRB_TR_IOC (1<<5)
256 #define TRB_TR_IDT (1<<6)
257 #define TRB_TR_TBC_SHIFT 7
258 #define TRB_TR_TBC_MASK 0x3
259 #define TRB_TR_BEI (1<<9)
260 #define TRB_TR_TLBPC_SHIFT 16
261 #define TRB_TR_TLBPC_MASK 0xf
262 #define TRB_TR_FRAMEID_SHIFT 20
263 #define TRB_TR_FRAMEID_MASK 0x7ff
264 #define TRB_TR_SIA (1<<31)
265
266 #define TRB_TR_DIR (1<<16)
267
268 #define TRB_CR_SLOTID_SHIFT 24
269 #define TRB_CR_SLOTID_MASK 0xff
270 #define TRB_CR_EPID_SHIFT 16
271 #define TRB_CR_EPID_MASK 0x1f
272
273 #define TRB_CR_BSR (1<<9)
274 #define TRB_CR_DC (1<<9)
275
276 #define TRB_LK_TC (1<<1)
277
278 #define TRB_INTR_SHIFT 22
279 #define TRB_INTR_MASK 0x3ff
280 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
281
282 #define EP_TYPE_MASK 0x7
283 #define EP_TYPE_SHIFT 3
284
285 #define EP_STATE_MASK 0x7
286 #define EP_DISABLED (0<<0)
287 #define EP_RUNNING (1<<0)
288 #define EP_HALTED (2<<0)
289 #define EP_STOPPED (3<<0)
290 #define EP_ERROR (4<<0)
291
292 #define SLOT_STATE_MASK 0x1f
293 #define SLOT_STATE_SHIFT 27
294 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
295 #define SLOT_ENABLED 0
296 #define SLOT_DEFAULT 1
297 #define SLOT_ADDRESSED 2
298 #define SLOT_CONFIGURED 3
299
300 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
301 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
302
303 typedef struct XHCIState XHCIState;
304 typedef struct XHCIStreamContext XHCIStreamContext;
305 typedef struct XHCIEPContext XHCIEPContext;
306
307 #define get_field(data, field) \
308 (((data) >> field##_SHIFT) & field##_MASK)
309
310 #define set_field(data, newval, field) do { \
311 uint32_t val = *data; \
312 val &= ~(field##_MASK << field##_SHIFT); \
313 val |= ((newval) & field##_MASK) << field##_SHIFT; \
314 *data = val; \
315 } while (0)
316
317 typedef enum EPType {
318 ET_INVALID = 0,
319 ET_ISO_OUT,
320 ET_BULK_OUT,
321 ET_INTR_OUT,
322 ET_CONTROL,
323 ET_ISO_IN,
324 ET_BULK_IN,
325 ET_INTR_IN,
326 } EPType;
327
328 typedef struct XHCIRing {
329 dma_addr_t dequeue;
330 bool ccs;
331 } XHCIRing;
332
333 typedef struct XHCIPort {
334 XHCIState *xhci;
335 uint32_t portsc;
336 uint32_t portnr;
337 USBPort *uport;
338 uint32_t speedmask;
339 char name[16];
340 MemoryRegion mem;
341 } XHCIPort;
342
343 typedef struct XHCITransfer {
344 XHCIState *xhci;
345 USBPacket packet;
346 QEMUSGList sgl;
347 bool running_async;
348 bool running_retry;
349 bool complete;
350 bool int_req;
351 unsigned int iso_pkts;
352 unsigned int slotid;
353 unsigned int epid;
354 unsigned int streamid;
355 bool in_xfer;
356 bool iso_xfer;
357 bool timed_xfer;
358
359 unsigned int trb_count;
360 unsigned int trb_alloced;
361 XHCITRB *trbs;
362
363 TRBCCode status;
364
365 unsigned int pkts;
366 unsigned int pktsize;
367 unsigned int cur_pkt;
368
369 uint64_t mfindex_kick;
370 } XHCITransfer;
371
372 struct XHCIStreamContext {
373 dma_addr_t pctx;
374 unsigned int sct;
375 XHCIRing ring;
376 };
377
378 struct XHCIEPContext {
379 XHCIState *xhci;
380 unsigned int slotid;
381 unsigned int epid;
382
383 XHCIRing ring;
384 unsigned int next_xfer;
385 unsigned int comp_xfer;
386 XHCITransfer transfers[TD_QUEUE];
387 XHCITransfer *retry;
388 EPType type;
389 dma_addr_t pctx;
390 unsigned int max_psize;
391 uint32_t state;
392
393 /* streams */
394 unsigned int max_pstreams;
395 bool lsa;
396 unsigned int nr_pstreams;
397 XHCIStreamContext *pstreams;
398
399 /* iso xfer scheduling */
400 unsigned int interval;
401 int64_t mfindex_last;
402 QEMUTimer *kick_timer;
403 };
404
405 typedef struct XHCISlot {
406 bool enabled;
407 bool addressed;
408 dma_addr_t ctx;
409 USBPort *uport;
410 XHCIEPContext * eps[31];
411 } XHCISlot;
412
413 typedef struct XHCIEvent {
414 TRBType type;
415 TRBCCode ccode;
416 uint64_t ptr;
417 uint32_t length;
418 uint32_t flags;
419 uint8_t slotid;
420 uint8_t epid;
421 } XHCIEvent;
422
423 typedef struct XHCIInterrupter {
424 uint32_t iman;
425 uint32_t imod;
426 uint32_t erstsz;
427 uint32_t erstba_low;
428 uint32_t erstba_high;
429 uint32_t erdp_low;
430 uint32_t erdp_high;
431
432 bool msix_used, er_pcs, er_full;
433
434 dma_addr_t er_start;
435 uint32_t er_size;
436 unsigned int er_ep_idx;
437
438 XHCIEvent ev_buffer[EV_QUEUE];
439 unsigned int ev_buffer_put;
440 unsigned int ev_buffer_get;
441
442 } XHCIInterrupter;
443
444 struct XHCIState {
445 /*< private >*/
446 PCIDevice parent_obj;
447 /*< public >*/
448
449 USBBus bus;
450 MemoryRegion mem;
451 MemoryRegion mem_cap;
452 MemoryRegion mem_oper;
453 MemoryRegion mem_runtime;
454 MemoryRegion mem_doorbell;
455
456 /* properties */
457 uint32_t numports_2;
458 uint32_t numports_3;
459 uint32_t numintrs;
460 uint32_t numslots;
461 uint32_t flags;
462 uint32_t max_pstreams_mask;
463
464 /* Operational Registers */
465 uint32_t usbcmd;
466 uint32_t usbsts;
467 uint32_t dnctrl;
468 uint32_t crcr_low;
469 uint32_t crcr_high;
470 uint32_t dcbaap_low;
471 uint32_t dcbaap_high;
472 uint32_t config;
473
474 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)];
475 XHCIPort ports[MAXPORTS];
476 XHCISlot slots[MAXSLOTS];
477 uint32_t numports;
478
479 /* Runtime Registers */
480 int64_t mfindex_start;
481 QEMUTimer *mfwrap_timer;
482 XHCIInterrupter intr[MAXINTRS];
483
484 XHCIRing cmd_ring;
485 };
486
487 #define TYPE_XHCI "nec-usb-xhci"
488
489 #define XHCI(obj) \
490 OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI)
491
492 typedef struct XHCIEvRingSeg {
493 uint32_t addr_low;
494 uint32_t addr_high;
495 uint32_t size;
496 uint32_t rsvd;
497 } XHCIEvRingSeg;
498
499 enum xhci_flags {
500 XHCI_FLAG_USE_MSI = 1,
501 XHCI_FLAG_USE_MSI_X,
502 XHCI_FLAG_SS_FIRST,
503 XHCI_FLAG_FORCE_PCIE_ENDCAP,
504 XHCI_FLAG_ENABLE_STREAMS,
505 };
506
507 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
508 unsigned int epid, unsigned int streamid);
509 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
510 unsigned int epid);
511 static void xhci_xfer_report(XHCITransfer *xfer);
512 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v);
513 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v);
514 static USBEndpoint *xhci_epid_to_usbep(XHCIState *xhci,
515 unsigned int slotid, unsigned int epid);
516
517 static const char *TRBType_names[] = {
518 [TRB_RESERVED] = "TRB_RESERVED",
519 [TR_NORMAL] = "TR_NORMAL",
520 [TR_SETUP] = "TR_SETUP",
521 [TR_DATA] = "TR_DATA",
522 [TR_STATUS] = "TR_STATUS",
523 [TR_ISOCH] = "TR_ISOCH",
524 [TR_LINK] = "TR_LINK",
525 [TR_EVDATA] = "TR_EVDATA",
526 [TR_NOOP] = "TR_NOOP",
527 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT",
528 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT",
529 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE",
530 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT",
531 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT",
532 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT",
533 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT",
534 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE",
535 [CR_RESET_DEVICE] = "CR_RESET_DEVICE",
536 [CR_FORCE_EVENT] = "CR_FORCE_EVENT",
537 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW",
538 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE",
539 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH",
540 [CR_FORCE_HEADER] = "CR_FORCE_HEADER",
541 [CR_NOOP] = "CR_NOOP",
542 [ER_TRANSFER] = "ER_TRANSFER",
543 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE",
544 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE",
545 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST",
546 [ER_DOORBELL] = "ER_DOORBELL",
547 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER",
548 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION",
549 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP",
550 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
551 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
552 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
553 };
554
555 static const char *TRBCCode_names[] = {
556 [CC_INVALID] = "CC_INVALID",
557 [CC_SUCCESS] = "CC_SUCCESS",
558 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR",
559 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED",
560 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR",
561 [CC_TRB_ERROR] = "CC_TRB_ERROR",
562 [CC_STALL_ERROR] = "CC_STALL_ERROR",
563 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR",
564 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR",
565 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR",
566 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR",
567 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR",
568 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR",
569 [CC_SHORT_PACKET] = "CC_SHORT_PACKET",
570 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN",
571 [CC_RING_OVERRUN] = "CC_RING_OVERRUN",
572 [CC_VF_ER_FULL] = "CC_VF_ER_FULL",
573 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR",
574 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN",
575 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR",
576 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR",
577 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR",
578 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR",
579 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR",
580 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED",
581 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED",
582 [CC_STOPPED] = "CC_STOPPED",
583 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID",
584 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR]
585 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
586 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN",
587 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR",
588 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR",
589 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR",
590 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR",
591 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR",
592 };
593
594 static const char *ep_state_names[] = {
595 [EP_DISABLED] = "disabled",
596 [EP_RUNNING] = "running",
597 [EP_HALTED] = "halted",
598 [EP_STOPPED] = "stopped",
599 [EP_ERROR] = "error",
600 };
601
602 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen)
603 {
604 if (index >= llen || list[index] == NULL) {
605 return "???";
606 }
607 return list[index];
608 }
609
610 static const char *trb_name(XHCITRB *trb)
611 {
612 return lookup_name(TRB_TYPE(*trb), TRBType_names,
613 ARRAY_SIZE(TRBType_names));
614 }
615
616 static const char *event_name(XHCIEvent *event)
617 {
618 return lookup_name(event->ccode, TRBCCode_names,
619 ARRAY_SIZE(TRBCCode_names));
620 }
621
622 static const char *ep_state_name(uint32_t state)
623 {
624 return lookup_name(state, ep_state_names,
625 ARRAY_SIZE(ep_state_names));
626 }
627
628 static bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit)
629 {
630 return xhci->flags & (1 << bit);
631 }
632
633 static uint64_t xhci_mfindex_get(XHCIState *xhci)
634 {
635 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
636 return (now - xhci->mfindex_start) / 125000;
637 }
638
639 static void xhci_mfwrap_update(XHCIState *xhci)
640 {
641 const uint32_t bits = USBCMD_RS | USBCMD_EWE;
642 uint32_t mfindex, left;
643 int64_t now;
644
645 if ((xhci->usbcmd & bits) == bits) {
646 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
647 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff;
648 left = 0x4000 - mfindex;
649 timer_mod(xhci->mfwrap_timer, now + left * 125000);
650 } else {
651 timer_del(xhci->mfwrap_timer);
652 }
653 }
654
655 static void xhci_mfwrap_timer(void *opaque)
656 {
657 XHCIState *xhci = opaque;
658 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS };
659
660 xhci_event(xhci, &wrap, 0);
661 xhci_mfwrap_update(xhci);
662 }
663
664 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high)
665 {
666 if (sizeof(dma_addr_t) == 4) {
667 return low;
668 } else {
669 return low | (((dma_addr_t)high << 16) << 16);
670 }
671 }
672
673 static inline dma_addr_t xhci_mask64(uint64_t addr)
674 {
675 if (sizeof(dma_addr_t) == 4) {
676 return addr & 0xffffffff;
677 } else {
678 return addr;
679 }
680 }
681
682 static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr,
683 uint32_t *buf, size_t len)
684 {
685 int i;
686
687 assert((len % sizeof(uint32_t)) == 0);
688
689 pci_dma_read(PCI_DEVICE(xhci), addr, buf, len);
690
691 for (i = 0; i < (len / sizeof(uint32_t)); i++) {
692 buf[i] = le32_to_cpu(buf[i]);
693 }
694 }
695
696 static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr,
697 uint32_t *buf, size_t len)
698 {
699 int i;
700 uint32_t tmp[len / sizeof(uint32_t)];
701
702 assert((len % sizeof(uint32_t)) == 0);
703
704 for (i = 0; i < (len / sizeof(uint32_t)); i++) {
705 tmp[i] = cpu_to_le32(buf[i]);
706 }
707 pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len);
708 }
709
710 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
711 {
712 int index;
713
714 if (!uport->dev) {
715 return NULL;
716 }
717 switch (uport->dev->speed) {
718 case USB_SPEED_LOW:
719 case USB_SPEED_FULL:
720 case USB_SPEED_HIGH:
721 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
722 index = uport->index + xhci->numports_3;
723 } else {
724 index = uport->index;
725 }
726 break;
727 case USB_SPEED_SUPER:
728 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
729 index = uport->index;
730 } else {
731 index = uport->index + xhci->numports_2;
732 }
733 break;
734 default:
735 return NULL;
736 }
737 return &xhci->ports[index];
738 }
739
740 static void xhci_intx_update(XHCIState *xhci)
741 {
742 PCIDevice *pci_dev = PCI_DEVICE(xhci);
743 int level = 0;
744
745 if (msix_enabled(pci_dev) ||
746 msi_enabled(pci_dev)) {
747 return;
748 }
749
750 if (xhci->intr[0].iman & IMAN_IP &&
751 xhci->intr[0].iman & IMAN_IE &&
752 xhci->usbcmd & USBCMD_INTE) {
753 level = 1;
754 }
755
756 trace_usb_xhci_irq_intx(level);
757 pci_set_irq(pci_dev, level);
758 }
759
760 static void xhci_msix_update(XHCIState *xhci, int v)
761 {
762 PCIDevice *pci_dev = PCI_DEVICE(xhci);
763 bool enabled;
764
765 if (!msix_enabled(pci_dev)) {
766 return;
767 }
768
769 enabled = xhci->intr[v].iman & IMAN_IE;
770 if (enabled == xhci->intr[v].msix_used) {
771 return;
772 }
773
774 if (enabled) {
775 trace_usb_xhci_irq_msix_use(v);
776 msix_vector_use(pci_dev, v);
777 xhci->intr[v].msix_used = true;
778 } else {
779 trace_usb_xhci_irq_msix_unuse(v);
780 msix_vector_unuse(pci_dev, v);
781 xhci->intr[v].msix_used = false;
782 }
783 }
784
785 static void xhci_intr_raise(XHCIState *xhci, int v)
786 {
787 PCIDevice *pci_dev = PCI_DEVICE(xhci);
788
789 xhci->intr[v].erdp_low |= ERDP_EHB;
790 xhci->intr[v].iman |= IMAN_IP;
791 xhci->usbsts |= USBSTS_EINT;
792
793 if (!(xhci->intr[v].iman & IMAN_IE)) {
794 return;
795 }
796
797 if (!(xhci->usbcmd & USBCMD_INTE)) {
798 return;
799 }
800
801 if (msix_enabled(pci_dev)) {
802 trace_usb_xhci_irq_msix(v);
803 msix_notify(pci_dev, v);
804 return;
805 }
806
807 if (msi_enabled(pci_dev)) {
808 trace_usb_xhci_irq_msi(v);
809 msi_notify(pci_dev, v);
810 return;
811 }
812
813 if (v == 0) {
814 trace_usb_xhci_irq_intx(1);
815 pci_irq_assert(pci_dev);
816 }
817 }
818
819 static inline int xhci_running(XHCIState *xhci)
820 {
821 return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full;
822 }
823
824 static void xhci_die(XHCIState *xhci)
825 {
826 xhci->usbsts |= USBSTS_HCE;
827 DPRINTF("xhci: asserted controller error\n");
828 }
829
830 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
831 {
832 PCIDevice *pci_dev = PCI_DEVICE(xhci);
833 XHCIInterrupter *intr = &xhci->intr[v];
834 XHCITRB ev_trb;
835 dma_addr_t addr;
836
837 ev_trb.parameter = cpu_to_le64(event->ptr);
838 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
839 ev_trb.control = (event->slotid << 24) | (event->epid << 16) |
840 event->flags | (event->type << TRB_TYPE_SHIFT);
841 if (intr->er_pcs) {
842 ev_trb.control |= TRB_C;
843 }
844 ev_trb.control = cpu_to_le32(ev_trb.control);
845
846 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb),
847 event_name(event), ev_trb.parameter,
848 ev_trb.status, ev_trb.control);
849
850 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx;
851 pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE);
852
853 intr->er_ep_idx++;
854 if (intr->er_ep_idx >= intr->er_size) {
855 intr->er_ep_idx = 0;
856 intr->er_pcs = !intr->er_pcs;
857 }
858 }
859
860 static void xhci_events_update(XHCIState *xhci, int v)
861 {
862 XHCIInterrupter *intr = &xhci->intr[v];
863 dma_addr_t erdp;
864 unsigned int dp_idx;
865 bool do_irq = 0;
866
867 if (xhci->usbsts & USBSTS_HCH) {
868 return;
869 }
870
871 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
872 if (erdp < intr->er_start ||
873 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {
874 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
875 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n",
876 v, intr->er_start, intr->er_size);
877 xhci_die(xhci);
878 return;
879 }
880 dp_idx = (erdp - intr->er_start) / TRB_SIZE;
881 assert(dp_idx < intr->er_size);
882
883 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
884 * deadlocks when the ER is full. Hack it by holding off events until
885 * the driver decides to free at least half of the ring */
886 if (intr->er_full) {
887 int er_free = dp_idx - intr->er_ep_idx;
888 if (er_free <= 0) {
889 er_free += intr->er_size;
890 }
891 if (er_free < (intr->er_size/2)) {
892 DPRINTF("xhci_events_update(): event ring still "
893 "more than half full (hack)\n");
894 return;
895 }
896 }
897
898 while (intr->ev_buffer_put != intr->ev_buffer_get) {
899 assert(intr->er_full);
900 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) {
901 DPRINTF("xhci_events_update(): event ring full again\n");
902 #ifndef ER_FULL_HACK
903 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
904 xhci_write_event(xhci, &full, v);
905 #endif
906 do_irq = 1;
907 break;
908 }
909 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get];
910 xhci_write_event(xhci, event, v);
911 intr->ev_buffer_get++;
912 do_irq = 1;
913 if (intr->ev_buffer_get == EV_QUEUE) {
914 intr->ev_buffer_get = 0;
915 }
916 }
917
918 if (do_irq) {
919 xhci_intr_raise(xhci, v);
920 }
921
922 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) {
923 DPRINTF("xhci_events_update(): event ring no longer full\n");
924 intr->er_full = 0;
925 }
926 }
927
928 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v)
929 {
930 XHCIInterrupter *intr;
931 dma_addr_t erdp;
932 unsigned int dp_idx;
933
934 if (v >= xhci->numintrs) {
935 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs);
936 return;
937 }
938 intr = &xhci->intr[v];
939
940 if (intr->er_full) {
941 DPRINTF("xhci_event(): ER full, queueing\n");
942 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) {
943 DPRINTF("xhci: event queue full, dropping event!\n");
944 return;
945 }
946 intr->ev_buffer[intr->ev_buffer_put++] = *event;
947 if (intr->ev_buffer_put == EV_QUEUE) {
948 intr->ev_buffer_put = 0;
949 }
950 return;
951 }
952
953 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
954 if (erdp < intr->er_start ||
955 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {
956 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
957 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n",
958 v, intr->er_start, intr->er_size);
959 xhci_die(xhci);
960 return;
961 }
962
963 dp_idx = (erdp - intr->er_start) / TRB_SIZE;
964 assert(dp_idx < intr->er_size);
965
966 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) {
967 DPRINTF("xhci_event(): ER full, queueing\n");
968 #ifndef ER_FULL_HACK
969 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
970 xhci_write_event(xhci, &full);
971 #endif
972 intr->er_full = 1;
973 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) {
974 DPRINTF("xhci: event queue full, dropping event!\n");
975 return;
976 }
977 intr->ev_buffer[intr->ev_buffer_put++] = *event;
978 if (intr->ev_buffer_put == EV_QUEUE) {
979 intr->ev_buffer_put = 0;
980 }
981 } else {
982 xhci_write_event(xhci, event, v);
983 }
984
985 xhci_intr_raise(xhci, v);
986 }
987
988 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
989 dma_addr_t base)
990 {
991 ring->dequeue = base;
992 ring->ccs = 1;
993 }
994
995 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
996 dma_addr_t *addr)
997 {
998 PCIDevice *pci_dev = PCI_DEVICE(xhci);
999
1000 while (1) {
1001 TRBType type;
1002 pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE);
1003 trb->addr = ring->dequeue;
1004 trb->ccs = ring->ccs;
1005 le64_to_cpus(&trb->parameter);
1006 le32_to_cpus(&trb->status);
1007 le32_to_cpus(&trb->control);
1008
1009 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb),
1010 trb->parameter, trb->status, trb->control);
1011
1012 if ((trb->control & TRB_C) != ring->ccs) {
1013 return 0;
1014 }
1015
1016 type = TRB_TYPE(*trb);
1017
1018 if (type != TR_LINK) {
1019 if (addr) {
1020 *addr = ring->dequeue;
1021 }
1022 ring->dequeue += TRB_SIZE;
1023 return type;
1024 } else {
1025 ring->dequeue = xhci_mask64(trb->parameter);
1026 if (trb->control & TRB_LK_TC) {
1027 ring->ccs = !ring->ccs;
1028 }
1029 }
1030 }
1031 }
1032
1033 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
1034 {
1035 PCIDevice *pci_dev = PCI_DEVICE(xhci);
1036 XHCITRB trb;
1037 int length = 0;
1038 dma_addr_t dequeue = ring->dequeue;
1039 bool ccs = ring->ccs;
1040 /* hack to bundle together the two/three TDs that make a setup transfer */
1041 bool control_td_set = 0;
1042
1043 while (1) {
1044 TRBType type;
1045 pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE);
1046 le64_to_cpus(&trb.parameter);
1047 le32_to_cpus(&trb.status);
1048 le32_to_cpus(&trb.control);
1049
1050 if ((trb.control & TRB_C) != ccs) {
1051 return -length;
1052 }
1053
1054 type = TRB_TYPE(trb);
1055
1056 if (type == TR_LINK) {
1057 dequeue = xhci_mask64(trb.parameter);
1058 if (trb.control & TRB_LK_TC) {
1059 ccs = !ccs;
1060 }
1061 continue;
1062 }
1063
1064 length += 1;
1065 dequeue += TRB_SIZE;
1066
1067 if (type == TR_SETUP) {
1068 control_td_set = 1;
1069 } else if (type == TR_STATUS) {
1070 control_td_set = 0;
1071 }
1072
1073 if (!control_td_set && !(trb.control & TRB_TR_CH)) {
1074 return length;
1075 }
1076 }
1077 }
1078
1079 static void xhci_er_reset(XHCIState *xhci, int v)
1080 {
1081 XHCIInterrupter *intr = &xhci->intr[v];
1082 XHCIEvRingSeg seg;
1083
1084 if (intr->erstsz == 0) {
1085 /* disabled */
1086 intr->er_start = 0;
1087 intr->er_size = 0;
1088 return;
1089 }
1090 /* cache the (sole) event ring segment location */
1091 if (intr->erstsz != 1) {
1092 DPRINTF("xhci: invalid value for ERSTSZ: %d\n", intr->erstsz);
1093 xhci_die(xhci);
1094 return;
1095 }
1096 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high);
1097 pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg));
1098 le32_to_cpus(&seg.addr_low);
1099 le32_to_cpus(&seg.addr_high);
1100 le32_to_cpus(&seg.size);
1101 if (seg.size < 16 || seg.size > 4096) {
1102 DPRINTF("xhci: invalid value for segment size: %d\n", seg.size);
1103 xhci_die(xhci);
1104 return;
1105 }
1106 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high);
1107 intr->er_size = seg.size;
1108
1109 intr->er_ep_idx = 0;
1110 intr->er_pcs = 1;
1111 intr->er_full = 0;
1112
1113 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n",
1114 v, intr->er_start, intr->er_size);
1115 }
1116
1117 static void xhci_run(XHCIState *xhci)
1118 {
1119 trace_usb_xhci_run();
1120 xhci->usbsts &= ~USBSTS_HCH;
1121 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1122 }
1123
1124 static void xhci_stop(XHCIState *xhci)
1125 {
1126 trace_usb_xhci_stop();
1127 xhci->usbsts |= USBSTS_HCH;
1128 xhci->crcr_low &= ~CRCR_CRR;
1129 }
1130
1131 static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count,
1132 dma_addr_t base)
1133 {
1134 XHCIStreamContext *stctx;
1135 unsigned int i;
1136
1137 stctx = g_new0(XHCIStreamContext, count);
1138 for (i = 0; i < count; i++) {
1139 stctx[i].pctx = base + i * 16;
1140 stctx[i].sct = -1;
1141 }
1142 return stctx;
1143 }
1144
1145 static void xhci_reset_streams(XHCIEPContext *epctx)
1146 {
1147 unsigned int i;
1148
1149 for (i = 0; i < epctx->nr_pstreams; i++) {
1150 epctx->pstreams[i].sct = -1;
1151 }
1152 }
1153
1154 static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base)
1155 {
1156 assert(epctx->pstreams == NULL);
1157 epctx->nr_pstreams = 2 << epctx->max_pstreams;
1158 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base);
1159 }
1160
1161 static void xhci_free_streams(XHCIEPContext *epctx)
1162 {
1163 assert(epctx->pstreams != NULL);
1164
1165 g_free(epctx->pstreams);
1166 epctx->pstreams = NULL;
1167 epctx->nr_pstreams = 0;
1168 }
1169
1170 static int xhci_epmask_to_eps_with_streams(XHCIState *xhci,
1171 unsigned int slotid,
1172 uint32_t epmask,
1173 XHCIEPContext **epctxs,
1174 USBEndpoint **eps)
1175 {
1176 XHCISlot *slot;
1177 XHCIEPContext *epctx;
1178 USBEndpoint *ep;
1179 int i, j;
1180
1181 assert(slotid >= 1 && slotid <= xhci->numslots);
1182
1183 slot = &xhci->slots[slotid - 1];
1184
1185 for (i = 2, j = 0; i <= 31; i++) {
1186 if (!(epmask & (1u << i))) {
1187 continue;
1188 }
1189
1190 epctx = slot->eps[i - 1];
1191 ep = xhci_epid_to_usbep(xhci, slotid, i);
1192 if (!epctx || !epctx->nr_pstreams || !ep) {
1193 continue;
1194 }
1195
1196 if (epctxs) {
1197 epctxs[j] = epctx;
1198 }
1199 eps[j++] = ep;
1200 }
1201 return j;
1202 }
1203
1204 static void xhci_free_device_streams(XHCIState *xhci, unsigned int slotid,
1205 uint32_t epmask)
1206 {
1207 USBEndpoint *eps[30];
1208 int nr_eps;
1209
1210 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, NULL, eps);
1211 if (nr_eps) {
1212 usb_device_free_streams(eps[0]->dev, eps, nr_eps);
1213 }
1214 }
1215
1216 static TRBCCode xhci_alloc_device_streams(XHCIState *xhci, unsigned int slotid,
1217 uint32_t epmask)
1218 {
1219 XHCIEPContext *epctxs[30];
1220 USBEndpoint *eps[30];
1221 int i, r, nr_eps, req_nr_streams, dev_max_streams;
1222
1223 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, epctxs,
1224 eps);
1225 if (nr_eps == 0) {
1226 return CC_SUCCESS;
1227 }
1228
1229 req_nr_streams = epctxs[0]->nr_pstreams;
1230 dev_max_streams = eps[0]->max_streams;
1231
1232 for (i = 1; i < nr_eps; i++) {
1233 /*
1234 * HdG: I don't expect these to ever trigger, but if they do we need
1235 * to come up with another solution, ie group identical endpoints
1236 * together and make an usb_device_alloc_streams call per group.
1237 */
1238 if (epctxs[i]->nr_pstreams != req_nr_streams) {
1239 FIXME("guest streams config not identical for all eps");
1240 return CC_RESOURCE_ERROR;
1241 }
1242 if (eps[i]->max_streams != dev_max_streams) {
1243 FIXME("device streams config not identical for all eps");
1244 return CC_RESOURCE_ERROR;
1245 }
1246 }
1247
1248 /*
1249 * max-streams in both the device descriptor and in the controller is a
1250 * power of 2. But stream id 0 is reserved, so if a device can do up to 4
1251 * streams the guest will ask for 5 rounded up to the next power of 2 which
1252 * becomes 8. For emulated devices usb_device_alloc_streams is a nop.
1253 *
1254 * For redirected devices however this is an issue, as there we must ask
1255 * the real xhci controller to alloc streams, and the host driver for the
1256 * real xhci controller will likely disallow allocating more streams then
1257 * the device can handle.
1258 *
1259 * So we limit the requested nr_streams to the maximum number the device
1260 * can handle.
1261 */
1262 if (req_nr_streams > dev_max_streams) {
1263 req_nr_streams = dev_max_streams;
1264 }
1265
1266 r = usb_device_alloc_streams(eps[0]->dev, eps, nr_eps, req_nr_streams);
1267 if (r != 0) {
1268 DPRINTF("xhci: alloc streams failed\n");
1269 return CC_RESOURCE_ERROR;
1270 }
1271
1272 return CC_SUCCESS;
1273 }
1274
1275 static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx,
1276 unsigned int streamid,
1277 uint32_t *cc_error)
1278 {
1279 XHCIStreamContext *sctx;
1280 dma_addr_t base;
1281 uint32_t ctx[2], sct;
1282
1283 assert(streamid != 0);
1284 if (epctx->lsa) {
1285 if (streamid >= epctx->nr_pstreams) {
1286 *cc_error = CC_INVALID_STREAM_ID_ERROR;
1287 return NULL;
1288 }
1289 sctx = epctx->pstreams + streamid;
1290 } else {
1291 FIXME("secondary streams not implemented yet");
1292 }
1293
1294 if (sctx->sct == -1) {
1295 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx));
1296 sct = (ctx[0] >> 1) & 0x07;
1297 if (epctx->lsa && sct != 1) {
1298 *cc_error = CC_INVALID_STREAM_TYPE_ERROR;
1299 return NULL;
1300 }
1301 sctx->sct = sct;
1302 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]);
1303 xhci_ring_init(epctx->xhci, &sctx->ring, base);
1304 }
1305 return sctx;
1306 }
1307
1308 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx,
1309 XHCIStreamContext *sctx, uint32_t state)
1310 {
1311 XHCIRing *ring = NULL;
1312 uint32_t ctx[5];
1313 uint32_t ctx2[2];
1314
1315 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1316 ctx[0] &= ~EP_STATE_MASK;
1317 ctx[0] |= state;
1318
1319 /* update ring dequeue ptr */
1320 if (epctx->nr_pstreams) {
1321 if (sctx != NULL) {
1322 ring = &sctx->ring;
1323 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1324 ctx2[0] &= 0xe;
1325 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs;
1326 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16;
1327 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1328 }
1329 } else {
1330 ring = &epctx->ring;
1331 }
1332 if (ring) {
1333 ctx[2] = ring->dequeue | ring->ccs;
1334 ctx[3] = (ring->dequeue >> 16) >> 16;
1335
1336 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n",
1337 epctx->pctx, state, ctx[3], ctx[2]);
1338 }
1339
1340 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1341 if (epctx->state != state) {
1342 trace_usb_xhci_ep_state(epctx->slotid, epctx->epid,
1343 ep_state_name(epctx->state),
1344 ep_state_name(state));
1345 }
1346 epctx->state = state;
1347 }
1348
1349 static void xhci_ep_kick_timer(void *opaque)
1350 {
1351 XHCIEPContext *epctx = opaque;
1352 xhci_kick_ep(epctx->xhci, epctx->slotid, epctx->epid, 0);
1353 }
1354
1355 static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci,
1356 unsigned int slotid,
1357 unsigned int epid)
1358 {
1359 XHCIEPContext *epctx;
1360 int i;
1361
1362 epctx = g_new0(XHCIEPContext, 1);
1363 epctx->xhci = xhci;
1364 epctx->slotid = slotid;
1365 epctx->epid = epid;
1366
1367 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) {
1368 epctx->transfers[i].xhci = xhci;
1369 epctx->transfers[i].slotid = slotid;
1370 epctx->transfers[i].epid = epid;
1371 usb_packet_init(&epctx->transfers[i].packet);
1372 }
1373 epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx);
1374
1375 return epctx;
1376 }
1377
1378 static void xhci_init_epctx(XHCIEPContext *epctx,
1379 dma_addr_t pctx, uint32_t *ctx)
1380 {
1381 dma_addr_t dequeue;
1382
1383 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]);
1384
1385 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK;
1386 epctx->pctx = pctx;
1387 epctx->max_psize = ctx[1]>>16;
1388 epctx->max_psize *= 1+((ctx[1]>>8)&0xff);
1389 epctx->max_pstreams = (ctx[0] >> 10) & epctx->xhci->max_pstreams_mask;
1390 epctx->lsa = (ctx[0] >> 15) & 1;
1391 if (epctx->max_pstreams) {
1392 xhci_alloc_streams(epctx, dequeue);
1393 } else {
1394 xhci_ring_init(epctx->xhci, &epctx->ring, dequeue);
1395 epctx->ring.ccs = ctx[2] & 1;
1396 }
1397
1398 epctx->interval = 1 << ((ctx[0] >> 16) & 0xff);
1399 }
1400
1401 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid,
1402 unsigned int epid, dma_addr_t pctx,
1403 uint32_t *ctx)
1404 {
1405 XHCISlot *slot;
1406 XHCIEPContext *epctx;
1407
1408 trace_usb_xhci_ep_enable(slotid, epid);
1409 assert(slotid >= 1 && slotid <= xhci->numslots);
1410 assert(epid >= 1 && epid <= 31);
1411
1412 slot = &xhci->slots[slotid-1];
1413 if (slot->eps[epid-1]) {
1414 xhci_disable_ep(xhci, slotid, epid);
1415 }
1416
1417 epctx = xhci_alloc_epctx(xhci, slotid, epid);
1418 slot->eps[epid-1] = epctx;
1419 xhci_init_epctx(epctx, pctx, ctx);
1420
1421 DPRINTF("xhci: endpoint %d.%d type is %d, max transaction (burst) "
1422 "size is %d\n", epid/2, epid%2, epctx->type, epctx->max_psize);
1423
1424 epctx->mfindex_last = 0;
1425
1426 epctx->state = EP_RUNNING;
1427 ctx[0] &= ~EP_STATE_MASK;
1428 ctx[0] |= EP_RUNNING;
1429
1430 return CC_SUCCESS;
1431 }
1432
1433 static int xhci_ep_nuke_one_xfer(XHCITransfer *t, TRBCCode report)
1434 {
1435 int killed = 0;
1436
1437 if (report && (t->running_async || t->running_retry)) {
1438 t->status = report;
1439 xhci_xfer_report(t);
1440 }
1441
1442 if (t->running_async) {
1443 usb_cancel_packet(&t->packet);
1444 t->running_async = 0;
1445 killed = 1;
1446 }
1447 if (t->running_retry) {
1448 XHCIEPContext *epctx = t->xhci->slots[t->slotid-1].eps[t->epid-1];
1449 if (epctx) {
1450 epctx->retry = NULL;
1451 timer_del(epctx->kick_timer);
1452 }
1453 t->running_retry = 0;
1454 killed = 1;
1455 }
1456 if (t->trbs) {
1457 g_free(t->trbs);
1458 }
1459
1460 t->trbs = NULL;
1461 t->trb_count = t->trb_alloced = 0;
1462
1463 return killed;
1464 }
1465
1466 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid,
1467 unsigned int epid, TRBCCode report)
1468 {
1469 XHCISlot *slot;
1470 XHCIEPContext *epctx;
1471 int i, xferi, killed = 0;
1472 USBEndpoint *ep = NULL;
1473 assert(slotid >= 1 && slotid <= xhci->numslots);
1474 assert(epid >= 1 && epid <= 31);
1475
1476 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid);
1477
1478 slot = &xhci->slots[slotid-1];
1479
1480 if (!slot->eps[epid-1]) {
1481 return 0;
1482 }
1483
1484 epctx = slot->eps[epid-1];
1485
1486 xferi = epctx->next_xfer;
1487 for (i = 0; i < TD_QUEUE; i++) {
1488 killed += xhci_ep_nuke_one_xfer(&epctx->transfers[xferi], report);
1489 if (killed) {
1490 report = 0; /* Only report once */
1491 }
1492 epctx->transfers[xferi].packet.ep = NULL;
1493 xferi = (xferi + 1) % TD_QUEUE;
1494 }
1495
1496 ep = xhci_epid_to_usbep(xhci, slotid, epid);
1497 if (ep) {
1498 usb_device_ep_stopped(ep->dev, ep);
1499 }
1500 return killed;
1501 }
1502
1503 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
1504 unsigned int epid)
1505 {
1506 XHCISlot *slot;
1507 XHCIEPContext *epctx;
1508 int i;
1509
1510 trace_usb_xhci_ep_disable(slotid, epid);
1511 assert(slotid >= 1 && slotid <= xhci->numslots);
1512 assert(epid >= 1 && epid <= 31);
1513
1514 slot = &xhci->slots[slotid-1];
1515
1516 if (!slot->eps[epid-1]) {
1517 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid);
1518 return CC_SUCCESS;
1519 }
1520
1521 xhci_ep_nuke_xfers(xhci, slotid, epid, 0);
1522
1523 epctx = slot->eps[epid-1];
1524
1525 if (epctx->nr_pstreams) {
1526 xhci_free_streams(epctx);
1527 }
1528
1529 for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) {
1530 usb_packet_cleanup(&epctx->transfers[i].packet);
1531 }
1532
1533 xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED);
1534
1535 timer_free(epctx->kick_timer);
1536 g_free(epctx);
1537 slot->eps[epid-1] = NULL;
1538
1539 return CC_SUCCESS;
1540 }
1541
1542 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid,
1543 unsigned int epid)
1544 {
1545 XHCISlot *slot;
1546 XHCIEPContext *epctx;
1547
1548 trace_usb_xhci_ep_stop(slotid, epid);
1549 assert(slotid >= 1 && slotid <= xhci->numslots);
1550
1551 if (epid < 1 || epid > 31) {
1552 DPRINTF("xhci: bad ep %d\n", epid);
1553 return CC_TRB_ERROR;
1554 }
1555
1556 slot = &xhci->slots[slotid-1];
1557
1558 if (!slot->eps[epid-1]) {
1559 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1560 return CC_EP_NOT_ENABLED_ERROR;
1561 }
1562
1563 if (xhci_ep_nuke_xfers(xhci, slotid, epid, CC_STOPPED) > 0) {
1564 DPRINTF("xhci: FIXME: endpoint stopped w/ xfers running, "
1565 "data might be lost\n");
1566 }
1567
1568 epctx = slot->eps[epid-1];
1569
1570 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1571
1572 if (epctx->nr_pstreams) {
1573 xhci_reset_streams(epctx);
1574 }
1575
1576 return CC_SUCCESS;
1577 }
1578
1579 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid,
1580 unsigned int epid)
1581 {
1582 XHCISlot *slot;
1583 XHCIEPContext *epctx;
1584
1585 trace_usb_xhci_ep_reset(slotid, epid);
1586 assert(slotid >= 1 && slotid <= xhci->numslots);
1587
1588 if (epid < 1 || epid > 31) {
1589 DPRINTF("xhci: bad ep %d\n", epid);
1590 return CC_TRB_ERROR;
1591 }
1592
1593 slot = &xhci->slots[slotid-1];
1594
1595 if (!slot->eps[epid-1]) {
1596 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1597 return CC_EP_NOT_ENABLED_ERROR;
1598 }
1599
1600 epctx = slot->eps[epid-1];
1601
1602 if (epctx->state != EP_HALTED) {
1603 DPRINTF("xhci: reset EP while EP %d not halted (%d)\n",
1604 epid, epctx->state);
1605 return CC_CONTEXT_STATE_ERROR;
1606 }
1607
1608 if (xhci_ep_nuke_xfers(xhci, slotid, epid, 0) > 0) {
1609 DPRINTF("xhci: FIXME: endpoint reset w/ xfers running, "
1610 "data might be lost\n");
1611 }
1612
1613 if (!xhci->slots[slotid-1].uport ||
1614 !xhci->slots[slotid-1].uport->dev ||
1615 !xhci->slots[slotid-1].uport->dev->attached) {
1616 return CC_USB_TRANSACTION_ERROR;
1617 }
1618
1619 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1620
1621 if (epctx->nr_pstreams) {
1622 xhci_reset_streams(epctx);
1623 }
1624
1625 return CC_SUCCESS;
1626 }
1627
1628 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid,
1629 unsigned int epid, unsigned int streamid,
1630 uint64_t pdequeue)
1631 {
1632 XHCISlot *slot;
1633 XHCIEPContext *epctx;
1634 XHCIStreamContext *sctx;
1635 dma_addr_t dequeue;
1636
1637 assert(slotid >= 1 && slotid <= xhci->numslots);
1638
1639 if (epid < 1 || epid > 31) {
1640 DPRINTF("xhci: bad ep %d\n", epid);
1641 return CC_TRB_ERROR;
1642 }
1643
1644 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue);
1645 dequeue = xhci_mask64(pdequeue);
1646
1647 slot = &xhci->slots[slotid-1];
1648
1649 if (!slot->eps[epid-1]) {
1650 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1651 return CC_EP_NOT_ENABLED_ERROR;
1652 }
1653
1654 epctx = slot->eps[epid-1];
1655
1656 if (epctx->state != EP_STOPPED) {
1657 DPRINTF("xhci: set EP dequeue pointer while EP %d not stopped\n", epid);
1658 return CC_CONTEXT_STATE_ERROR;
1659 }
1660
1661 if (epctx->nr_pstreams) {
1662 uint32_t err;
1663 sctx = xhci_find_stream(epctx, streamid, &err);
1664 if (sctx == NULL) {
1665 return err;
1666 }
1667 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf);
1668 sctx->ring.ccs = dequeue & 1;
1669 } else {
1670 sctx = NULL;
1671 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
1672 epctx->ring.ccs = dequeue & 1;
1673 }
1674
1675 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED);
1676
1677 return CC_SUCCESS;
1678 }
1679
1680 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer)
1681 {
1682 XHCIState *xhci = xfer->xhci;
1683 int i;
1684
1685 xfer->int_req = false;
1686 pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count);
1687 for (i = 0; i < xfer->trb_count; i++) {
1688 XHCITRB *trb = &xfer->trbs[i];
1689 dma_addr_t addr;
1690 unsigned int chunk = 0;
1691
1692 if (trb->control & TRB_TR_IOC) {
1693 xfer->int_req = true;
1694 }
1695
1696 switch (TRB_TYPE(*trb)) {
1697 case TR_DATA:
1698 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) {
1699 DPRINTF("xhci: data direction mismatch for TR_DATA\n");
1700 goto err;
1701 }
1702 /* fallthrough */
1703 case TR_NORMAL:
1704 case TR_ISOCH:
1705 addr = xhci_mask64(trb->parameter);
1706 chunk = trb->status & 0x1ffff;
1707 if (trb->control & TRB_TR_IDT) {
1708 if (chunk > 8 || in_xfer) {
1709 DPRINTF("xhci: invalid immediate data TRB\n");
1710 goto err;
1711 }
1712 qemu_sglist_add(&xfer->sgl, trb->addr, chunk);
1713 } else {
1714 qemu_sglist_add(&xfer->sgl, addr, chunk);
1715 }
1716 break;
1717 }
1718 }
1719
1720 return 0;
1721
1722 err:
1723 qemu_sglist_destroy(&xfer->sgl);
1724 xhci_die(xhci);
1725 return -1;
1726 }
1727
1728 static void xhci_xfer_unmap(XHCITransfer *xfer)
1729 {
1730 usb_packet_unmap(&xfer->packet, &xfer->sgl);
1731 qemu_sglist_destroy(&xfer->sgl);
1732 }
1733
1734 static void xhci_xfer_report(XHCITransfer *xfer)
1735 {
1736 uint32_t edtla = 0;
1737 unsigned int left;
1738 bool reported = 0;
1739 bool shortpkt = 0;
1740 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS};
1741 XHCIState *xhci = xfer->xhci;
1742 int i;
1743
1744 left = xfer->packet.actual_length;
1745
1746 for (i = 0; i < xfer->trb_count; i++) {
1747 XHCITRB *trb = &xfer->trbs[i];
1748 unsigned int chunk = 0;
1749
1750 switch (TRB_TYPE(*trb)) {
1751 case TR_DATA:
1752 case TR_NORMAL:
1753 case TR_ISOCH:
1754 chunk = trb->status & 0x1ffff;
1755 if (chunk > left) {
1756 chunk = left;
1757 if (xfer->status == CC_SUCCESS) {
1758 shortpkt = 1;
1759 }
1760 }
1761 left -= chunk;
1762 edtla += chunk;
1763 break;
1764 case TR_STATUS:
1765 reported = 0;
1766 shortpkt = 0;
1767 break;
1768 }
1769
1770 if (!reported && ((trb->control & TRB_TR_IOC) ||
1771 (shortpkt && (trb->control & TRB_TR_ISP)) ||
1772 (xfer->status != CC_SUCCESS && left == 0))) {
1773 event.slotid = xfer->slotid;
1774 event.epid = xfer->epid;
1775 event.length = (trb->status & 0x1ffff) - chunk;
1776 event.flags = 0;
1777 event.ptr = trb->addr;
1778 if (xfer->status == CC_SUCCESS) {
1779 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS;
1780 } else {
1781 event.ccode = xfer->status;
1782 }
1783 if (TRB_TYPE(*trb) == TR_EVDATA) {
1784 event.ptr = trb->parameter;
1785 event.flags |= TRB_EV_ED;
1786 event.length = edtla & 0xffffff;
1787 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length);
1788 edtla = 0;
1789 }
1790 xhci_event(xhci, &event, TRB_INTR(*trb));
1791 reported = 1;
1792 if (xfer->status != CC_SUCCESS) {
1793 return;
1794 }
1795 }
1796
1797 switch (TRB_TYPE(*trb)) {
1798 case TR_SETUP:
1799 reported = 0;
1800 shortpkt = 0;
1801 break;
1802 }
1803
1804 }
1805 }
1806
1807 static void xhci_stall_ep(XHCITransfer *xfer)
1808 {
1809 XHCIState *xhci = xfer->xhci;
1810 XHCISlot *slot = &xhci->slots[xfer->slotid-1];
1811 XHCIEPContext *epctx = slot->eps[xfer->epid-1];
1812 uint32_t err;
1813 XHCIStreamContext *sctx;
1814
1815 if (epctx->nr_pstreams) {
1816 sctx = xhci_find_stream(epctx, xfer->streamid, &err);
1817 if (sctx == NULL) {
1818 return;
1819 }
1820 sctx->ring.dequeue = xfer->trbs[0].addr;
1821 sctx->ring.ccs = xfer->trbs[0].ccs;
1822 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED);
1823 } else {
1824 epctx->ring.dequeue = xfer->trbs[0].addr;
1825 epctx->ring.ccs = xfer->trbs[0].ccs;
1826 xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED);
1827 }
1828 }
1829
1830 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer,
1831 XHCIEPContext *epctx);
1832
1833 static int xhci_setup_packet(XHCITransfer *xfer)
1834 {
1835 XHCIState *xhci = xfer->xhci;
1836 USBEndpoint *ep;
1837 int dir;
1838
1839 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT;
1840
1841 if (xfer->packet.ep) {
1842 ep = xfer->packet.ep;
1843 } else {
1844 ep = xhci_epid_to_usbep(xhci, xfer->slotid, xfer->epid);
1845 if (!ep) {
1846 DPRINTF("xhci: slot %d has no device\n",
1847 xfer->slotid);
1848 return -1;
1849 }
1850 }
1851
1852 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */
1853 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid,
1854 xfer->trbs[0].addr, false, xfer->int_req);
1855 usb_packet_map(&xfer->packet, &xfer->sgl);
1856 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1857 xfer->packet.pid, ep->dev->addr, ep->nr);
1858 return 0;
1859 }
1860
1861 static int xhci_complete_packet(XHCITransfer *xfer)
1862 {
1863 if (xfer->packet.status == USB_RET_ASYNC) {
1864 trace_usb_xhci_xfer_async(xfer);
1865 xfer->running_async = 1;
1866 xfer->running_retry = 0;
1867 xfer->complete = 0;
1868 return 0;
1869 } else if (xfer->packet.status == USB_RET_NAK) {
1870 trace_usb_xhci_xfer_nak(xfer);
1871 xfer->running_async = 0;
1872 xfer->running_retry = 1;
1873 xfer->complete = 0;
1874 return 0;
1875 } else {
1876 xfer->running_async = 0;
1877 xfer->running_retry = 0;
1878 xfer->complete = 1;
1879 xhci_xfer_unmap(xfer);
1880 }
1881
1882 if (xfer->packet.status == USB_RET_SUCCESS) {
1883 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length);
1884 xfer->status = CC_SUCCESS;
1885 xhci_xfer_report(xfer);
1886 return 0;
1887 }
1888
1889 /* error */
1890 trace_usb_xhci_xfer_error(xfer, xfer->packet.status);
1891 switch (xfer->packet.status) {
1892 case USB_RET_NODEV:
1893 case USB_RET_IOERROR:
1894 xfer->status = CC_USB_TRANSACTION_ERROR;
1895 xhci_xfer_report(xfer);
1896 xhci_stall_ep(xfer);
1897 break;
1898 case USB_RET_STALL:
1899 xfer->status = CC_STALL_ERROR;
1900 xhci_xfer_report(xfer);
1901 xhci_stall_ep(xfer);
1902 break;
1903 case USB_RET_BABBLE:
1904 xfer->status = CC_BABBLE_DETECTED;
1905 xhci_xfer_report(xfer);
1906 xhci_stall_ep(xfer);
1907 break;
1908 default:
1909 DPRINTF("%s: FIXME: status = %d\n", __func__,
1910 xfer->packet.status);
1911 FIXME("unhandled USB_RET_*");
1912 }
1913 return 0;
1914 }
1915
1916 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer)
1917 {
1918 XHCITRB *trb_setup, *trb_status;
1919 uint8_t bmRequestType;
1920
1921 trb_setup = &xfer->trbs[0];
1922 trb_status = &xfer->trbs[xfer->trb_count-1];
1923
1924 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid);
1925
1926 /* at most one Event Data TRB allowed after STATUS */
1927 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) {
1928 trb_status--;
1929 }
1930
1931 /* do some sanity checks */
1932 if (TRB_TYPE(*trb_setup) != TR_SETUP) {
1933 DPRINTF("xhci: ep0 first TD not SETUP: %d\n",
1934 TRB_TYPE(*trb_setup));
1935 return -1;
1936 }
1937 if (TRB_TYPE(*trb_status) != TR_STATUS) {
1938 DPRINTF("xhci: ep0 last TD not STATUS: %d\n",
1939 TRB_TYPE(*trb_status));
1940 return -1;
1941 }
1942 if (!(trb_setup->control & TRB_TR_IDT)) {
1943 DPRINTF("xhci: Setup TRB doesn't have IDT set\n");
1944 return -1;
1945 }
1946 if ((trb_setup->status & 0x1ffff) != 8) {
1947 DPRINTF("xhci: Setup TRB has bad length (%d)\n",
1948 (trb_setup->status & 0x1ffff));
1949 return -1;
1950 }
1951
1952 bmRequestType = trb_setup->parameter;
1953
1954 xfer->in_xfer = bmRequestType & USB_DIR_IN;
1955 xfer->iso_xfer = false;
1956 xfer->timed_xfer = false;
1957
1958 if (xhci_setup_packet(xfer) < 0) {
1959 return -1;
1960 }
1961 xfer->packet.parameter = trb_setup->parameter;
1962
1963 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
1964
1965 xhci_complete_packet(xfer);
1966 if (!xfer->running_async && !xfer->running_retry) {
1967 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, 0);
1968 }
1969 return 0;
1970 }
1971
1972 static void xhci_calc_intr_kick(XHCIState *xhci, XHCITransfer *xfer,
1973 XHCIEPContext *epctx, uint64_t mfindex)
1974 {
1975 uint64_t asap = ((mfindex + epctx->interval - 1) &
1976 ~(epctx->interval-1));
1977 uint64_t kick = epctx->mfindex_last + epctx->interval;
1978
1979 assert(epctx->interval != 0);
1980 xfer->mfindex_kick = MAX(asap, kick);
1981 }
1982
1983 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
1984 XHCIEPContext *epctx, uint64_t mfindex)
1985 {
1986 if (xfer->trbs[0].control & TRB_TR_SIA) {
1987 uint64_t asap = ((mfindex + epctx->interval - 1) &
1988 ~(epctx->interval-1));
1989 if (asap >= epctx->mfindex_last &&
1990 asap <= epctx->mfindex_last + epctx->interval * 4) {
1991 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval;
1992 } else {
1993 xfer->mfindex_kick = asap;
1994 }
1995 } else {
1996 xfer->mfindex_kick = ((xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT)
1997 & TRB_TR_FRAMEID_MASK) << 3;
1998 xfer->mfindex_kick |= mfindex & ~0x3fff;
1999 if (xfer->mfindex_kick + 0x100 < mfindex) {
2000 xfer->mfindex_kick += 0x4000;
2001 }
2002 }
2003 }
2004
2005 static void xhci_check_intr_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
2006 XHCIEPContext *epctx, uint64_t mfindex)
2007 {
2008 if (xfer->mfindex_kick > mfindex) {
2009 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
2010 (xfer->mfindex_kick - mfindex) * 125000);
2011 xfer->running_retry = 1;
2012 } else {
2013 epctx->mfindex_last = xfer->mfindex_kick;
2014 timer_del(epctx->kick_timer);
2015 xfer->running_retry = 0;
2016 }
2017 }
2018
2019
2020 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
2021 {
2022 uint64_t mfindex;
2023
2024 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid);
2025
2026 xfer->in_xfer = epctx->type>>2;
2027
2028 switch(epctx->type) {
2029 case ET_INTR_OUT:
2030 case ET_INTR_IN:
2031 xfer->pkts = 0;
2032 xfer->iso_xfer = false;
2033 xfer->timed_xfer = true;
2034 mfindex = xhci_mfindex_get(xhci);
2035 xhci_calc_intr_kick(xhci, xfer, epctx, mfindex);
2036 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
2037 if (xfer->running_retry) {
2038 return -1;
2039 }
2040 break;
2041 case ET_BULK_OUT:
2042 case ET_BULK_IN:
2043 xfer->pkts = 0;
2044 xfer->iso_xfer = false;
2045 xfer->timed_xfer = false;
2046 break;
2047 case ET_ISO_OUT:
2048 case ET_ISO_IN:
2049 xfer->pkts = 1;
2050 xfer->iso_xfer = true;
2051 xfer->timed_xfer = true;
2052 mfindex = xhci_mfindex_get(xhci);
2053 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex);
2054 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
2055 if (xfer->running_retry) {
2056 return -1;
2057 }
2058 break;
2059 default:
2060 trace_usb_xhci_unimplemented("endpoint type", epctx->type);
2061 return -1;
2062 }
2063
2064 if (xhci_setup_packet(xfer) < 0) {
2065 return -1;
2066 }
2067 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
2068
2069 xhci_complete_packet(xfer);
2070 if (!xfer->running_async && !xfer->running_retry) {
2071 xhci_kick_ep(xhci, xfer->slotid, xfer->epid, xfer->streamid);
2072 }
2073 return 0;
2074 }
2075
2076 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
2077 {
2078 trace_usb_xhci_xfer_start(xfer, xfer->slotid, xfer->epid, xfer->streamid);
2079 return xhci_submit(xhci, xfer, epctx);
2080 }
2081
2082 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
2083 unsigned int epid, unsigned int streamid)
2084 {
2085 XHCIStreamContext *stctx;
2086 XHCIEPContext *epctx;
2087 XHCIRing *ring;
2088 USBEndpoint *ep = NULL;
2089 uint64_t mfindex;
2090 int length;
2091 int i;
2092
2093 trace_usb_xhci_ep_kick(slotid, epid, streamid);
2094 assert(slotid >= 1 && slotid <= xhci->numslots);
2095 assert(epid >= 1 && epid <= 31);
2096
2097 if (!xhci->slots[slotid-1].enabled) {
2098 DPRINTF("xhci: xhci_kick_ep for disabled slot %d\n", slotid);
2099 return;
2100 }
2101 epctx = xhci->slots[slotid-1].eps[epid-1];
2102 if (!epctx) {
2103 DPRINTF("xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
2104 epid, slotid);
2105 return;
2106 }
2107
2108 /* If the device has been detached, but the guest has not noticed this
2109 yet the 2 above checks will succeed, but we must NOT continue */
2110 if (!xhci->slots[slotid - 1].uport ||
2111 !xhci->slots[slotid - 1].uport->dev ||
2112 !xhci->slots[slotid - 1].uport->dev->attached) {
2113 return;
2114 }
2115
2116 if (epctx->retry) {
2117 XHCITransfer *xfer = epctx->retry;
2118
2119 trace_usb_xhci_xfer_retry(xfer);
2120 assert(xfer->running_retry);
2121 if (xfer->timed_xfer) {
2122 /* time to kick the transfer? */
2123 mfindex = xhci_mfindex_get(xhci);
2124 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
2125 if (xfer->running_retry) {
2126 return;
2127 }
2128 xfer->timed_xfer = 0;
2129 xfer->running_retry = 1;
2130 }
2131 if (xfer->iso_xfer) {
2132 /* retry iso transfer */
2133 if (xhci_setup_packet(xfer) < 0) {
2134 return;
2135 }
2136 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
2137 assert(xfer->packet.status != USB_RET_NAK);
2138 xhci_complete_packet(xfer);
2139 } else {
2140 /* retry nak'ed transfer */
2141 if (xhci_setup_packet(xfer) < 0) {
2142 return;
2143 }
2144 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
2145 if (xfer->packet.status == USB_RET_NAK) {
2146 return;
2147 }
2148 xhci_complete_packet(xfer);
2149 }
2150 assert(!xfer->running_retry);
2151 epctx->retry = NULL;
2152 }
2153
2154 if (epctx->state == EP_HALTED) {
2155 DPRINTF("xhci: ep halted, not running schedule\n");
2156 return;
2157 }
2158
2159
2160 if (epctx->nr_pstreams) {
2161 uint32_t err;
2162 stctx = xhci_find_stream(epctx, streamid, &err);
2163 if (stctx == NULL) {
2164 return;
2165 }
2166 ring = &stctx->ring;
2167 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING);
2168 } else {
2169 ring = &epctx->ring;
2170 streamid = 0;
2171 xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING);
2172 }
2173 assert(ring->dequeue != 0);
2174
2175 while (1) {
2176 XHCITransfer *xfer = &epctx->transfers[epctx->next_xfer];
2177 if (xfer->running_async || xfer->running_retry) {
2178 break;
2179 }
2180 length = xhci_ring_chain_length(xhci, ring);
2181 if (length < 0) {
2182 break;
2183 } else if (length == 0) {
2184 break;
2185 }
2186 if (xfer->trbs && xfer->trb_alloced < length) {
2187 xfer->trb_count = 0;
2188 xfer->trb_alloced = 0;
2189 g_free(xfer->trbs);
2190 xfer->trbs = NULL;
2191 }
2192 if (!xfer->trbs) {
2193 xfer->trbs = g_malloc(sizeof(XHCITRB) * length);
2194 xfer->trb_alloced = length;
2195 }
2196 xfer->trb_count = length;
2197
2198 for (i = 0; i < length; i++) {
2199 assert(xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL));
2200 }
2201 xfer->streamid = streamid;
2202
2203 if (epid == 1) {
2204 if (xhci_fire_ctl_transfer(xhci, xfer) >= 0) {
2205 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
2206 ep = xfer->packet.ep;
2207 } else {
2208 DPRINTF("xhci: error firing CTL transfer\n");
2209 }
2210 } else {
2211 if (xhci_fire_transfer(xhci, xfer, epctx) >= 0) {
2212 epctx->next_xfer = (epctx->next_xfer + 1) % TD_QUEUE;
2213 } else {
2214 if (!xfer->timed_xfer) {
2215 DPRINTF("xhci: error firing data transfer\n");
2216 }
2217 }
2218 }
2219
2220 if (epctx->state == EP_HALTED) {
2221 break;
2222 }
2223 if (xfer->running_retry) {
2224 DPRINTF("xhci: xfer nacked, stopping schedule\n");
2225 epctx->retry = xfer;
2226 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
2227 epctx->interval * 125000);
2228 break;
2229 }
2230 }
2231
2232 ep = xhci_epid_to_usbep(xhci, slotid, epid);
2233 if (ep) {
2234 usb_device_flush_ep_queue(ep->dev, ep);
2235 }
2236 }
2237
2238 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid)
2239 {
2240 trace_usb_xhci_slot_enable(slotid);
2241 assert(slotid >= 1 && slotid <= xhci->numslots);
2242 xhci->slots[slotid-1].enabled = 1;
2243 xhci->slots[slotid-1].uport = NULL;
2244 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31);
2245
2246 return CC_SUCCESS;
2247 }
2248
2249 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid)
2250 {
2251 int i;
2252
2253 trace_usb_xhci_slot_disable(slotid);
2254 assert(slotid >= 1 && slotid <= xhci->numslots);
2255
2256 for (i = 1; i <= 31; i++) {
2257 if (xhci->slots[slotid-1].eps[i-1]) {
2258 xhci_disable_ep(xhci, slotid, i);
2259 }
2260 }
2261
2262 xhci->slots[slotid-1].enabled = 0;
2263 xhci->slots[slotid-1].addressed = 0;
2264 xhci->slots[slotid-1].uport = NULL;
2265 return CC_SUCCESS;
2266 }
2267
2268 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx)
2269 {
2270 USBPort *uport;
2271 char path[32];
2272 int i, pos, port;
2273
2274 port = (slot_ctx[1]>>16) & 0xFF;
2275 if (port < 1 || port > xhci->numports) {
2276 return NULL;
2277 }
2278 port = xhci->ports[port-1].uport->index+1;
2279 pos = snprintf(path, sizeof(path), "%d", port);
2280 for (i = 0; i < 5; i++) {
2281 port = (slot_ctx[0] >> 4*i) & 0x0f;
2282 if (!port) {
2283 break;
2284 }
2285 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port);
2286 }
2287
2288 QTAILQ_FOREACH(uport, &xhci->bus.used, next) {
2289 if (strcmp(uport->path, path) == 0) {
2290 return uport;
2291 }
2292 }
2293 return NULL;
2294 }
2295
2296 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
2297 uint64_t pictx, bool bsr)
2298 {
2299 XHCISlot *slot;
2300 USBPort *uport;
2301 USBDevice *dev;
2302 dma_addr_t ictx, octx, dcbaap;
2303 uint64_t poctx;
2304 uint32_t ictl_ctx[2];
2305 uint32_t slot_ctx[4];
2306 uint32_t ep0_ctx[5];
2307 int i;
2308 TRBCCode res;
2309
2310 assert(slotid >= 1 && slotid <= xhci->numslots);
2311
2312 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
2313 poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid);
2314 ictx = xhci_mask64(pictx);
2315 octx = xhci_mask64(poctx);
2316
2317 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2318 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2319
2320 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2321
2322 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) {
2323 DPRINTF("xhci: invalid input context control %08x %08x\n",
2324 ictl_ctx[0], ictl_ctx[1]);
2325 return CC_TRB_ERROR;
2326 }
2327
2328 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx));
2329 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx));
2330
2331 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2332 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2333
2334 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2335 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2336
2337 uport = xhci_lookup_uport(xhci, slot_ctx);
2338 if (uport == NULL) {
2339 DPRINTF("xhci: port not found\n");
2340 return CC_TRB_ERROR;
2341 }
2342 trace_usb_xhci_slot_address(slotid, uport->path);
2343
2344 dev = uport->dev;
2345 if (!dev || !dev->attached) {
2346 DPRINTF("xhci: port %s not connected\n", uport->path);
2347 return CC_USB_TRANSACTION_ERROR;
2348 }
2349
2350 for (i = 0; i < xhci->numslots; i++) {
2351 if (i == slotid-1) {
2352 continue;
2353 }
2354 if (xhci->slots[i].uport == uport) {
2355 DPRINTF("xhci: port %s already assigned to slot %d\n",
2356 uport->path, i+1);
2357 return CC_TRB_ERROR;
2358 }
2359 }
2360
2361 slot = &xhci->slots[slotid-1];
2362 slot->uport = uport;
2363 slot->ctx = octx;
2364
2365 if (bsr) {
2366 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT;
2367 } else {
2368 USBPacket p;
2369 uint8_t buf[1];
2370
2371 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid;
2372 usb_device_reset(dev);
2373 memset(&p, 0, sizeof(p));
2374 usb_packet_addbuf(&p, buf, sizeof(buf));
2375 usb_packet_setup(&p, USB_TOKEN_OUT,
2376 usb_ep_get(dev, USB_TOKEN_OUT, 0), 0,
2377 0, false, false);
2378 usb_device_handle_control(dev, &p,
2379 DeviceOutRequest | USB_REQ_SET_ADDRESS,
2380 slotid, 0, 0, NULL);
2381 assert(p.status != USB_RET_ASYNC);
2382 }
2383
2384 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx);
2385
2386 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2387 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2388 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2389 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2390
2391 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2392 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2393
2394 xhci->slots[slotid-1].addressed = 1;
2395 return res;
2396 }
2397
2398
2399 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid,
2400 uint64_t pictx, bool dc)
2401 {
2402 dma_addr_t ictx, octx;
2403 uint32_t ictl_ctx[2];
2404 uint32_t slot_ctx[4];
2405 uint32_t islot_ctx[4];
2406 uint32_t ep_ctx[5];
2407 int i;
2408 TRBCCode res;
2409
2410 trace_usb_xhci_slot_configure(slotid);
2411 assert(slotid >= 1 && slotid <= xhci->numslots);
2412
2413 ictx = xhci_mask64(pictx);
2414 octx = xhci->slots[slotid-1].ctx;
2415
2416 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2417 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2418
2419 if (dc) {
2420 for (i = 2; i <= 31; i++) {
2421 if (xhci->slots[slotid-1].eps[i-1]) {
2422 xhci_disable_ep(xhci, slotid, i);
2423 }
2424 }
2425
2426 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2427 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2428 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT;
2429 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2430 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2431 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2432
2433 return CC_SUCCESS;
2434 }
2435
2436 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2437
2438 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) {
2439 DPRINTF("xhci: invalid input context control %08x %08x\n",
2440 ictl_ctx[0], ictl_ctx[1]);
2441 return CC_TRB_ERROR;
2442 }
2443
2444 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2445 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2446
2447 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) {
2448 DPRINTF("xhci: invalid slot state %08x\n", slot_ctx[3]);
2449 return CC_CONTEXT_STATE_ERROR;
2450 }
2451
2452 xhci_free_device_streams(xhci, slotid, ictl_ctx[0] | ictl_ctx[1]);
2453
2454 for (i = 2; i <= 31; i++) {
2455 if (ictl_ctx[0] & (1<<i)) {
2456 xhci_disable_ep(xhci, slotid, i);
2457 }
2458 if (ictl_ctx[1] & (1<<i)) {
2459 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx));
2460 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
2461 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2462 ep_ctx[3], ep_ctx[4]);
2463 xhci_disable_ep(xhci, slotid, i);
2464 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
2465 if (res != CC_SUCCESS) {
2466 return res;
2467 }
2468 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
2469 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2470 ep_ctx[3], ep_ctx[4]);
2471 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx));
2472 }
2473 }
2474
2475 res = xhci_alloc_device_streams(xhci, slotid, ictl_ctx[1]);
2476 if (res != CC_SUCCESS) {
2477 for (i = 2; i <= 31; i++) {
2478 if (ictl_ctx[1] & (1u << i)) {
2479 xhci_disable_ep(xhci, slotid, i);
2480 }
2481 }
2482 return res;
2483 }
2484
2485 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2486 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT;
2487 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT);
2488 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK <<
2489 SLOT_CONTEXT_ENTRIES_SHIFT);
2490 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2491 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2492
2493 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2494
2495 return CC_SUCCESS;
2496 }
2497
2498
2499 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid,
2500 uint64_t pictx)
2501 {
2502 dma_addr_t ictx, octx;
2503 uint32_t ictl_ctx[2];
2504 uint32_t iep0_ctx[5];
2505 uint32_t ep0_ctx[5];
2506 uint32_t islot_ctx[4];
2507 uint32_t slot_ctx[4];
2508
2509 trace_usb_xhci_slot_evaluate(slotid);
2510 assert(slotid >= 1 && slotid <= xhci->numslots);
2511
2512 ictx = xhci_mask64(pictx);
2513 octx = xhci->slots[slotid-1].ctx;
2514
2515 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2516 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2517
2518 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2519
2520 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) {
2521 DPRINTF("xhci: invalid input context control %08x %08x\n",
2522 ictl_ctx[0], ictl_ctx[1]);
2523 return CC_TRB_ERROR;
2524 }
2525
2526 if (ictl_ctx[1] & 0x1) {
2527 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2528
2529 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2530 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]);
2531
2532 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2533
2534 slot_ctx[1] &= ~0xFFFF; /* max exit latency */
2535 slot_ctx[1] |= islot_ctx[1] & 0xFFFF;
2536 slot_ctx[2] &= ~0xFF00000; /* interrupter target */
2537 slot_ctx[2] |= islot_ctx[2] & 0xFF000000;
2538
2539 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2540 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2541
2542 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2543 }
2544
2545 if (ictl_ctx[1] & 0x2) {
2546 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx));
2547
2548 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2549 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2],
2550 iep0_ctx[3], iep0_ctx[4]);
2551
2552 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2553
2554 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/
2555 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000;
2556
2557 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2558 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2559
2560 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2561 }
2562
2563 return CC_SUCCESS;
2564 }
2565
2566 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid)
2567 {
2568 uint32_t slot_ctx[4];
2569 dma_addr_t octx;
2570 int i;
2571
2572 trace_usb_xhci_slot_reset(slotid);
2573 assert(slotid >= 1 && slotid <= xhci->numslots);
2574
2575 octx = xhci->slots[slotid-1].ctx;
2576
2577 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2578
2579 for (i = 2; i <= 31; i++) {
2580 if (xhci->slots[slotid-1].eps[i-1]) {
2581 xhci_disable_ep(xhci, slotid, i);
2582 }
2583 }
2584
2585 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2586 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2587 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT;
2588 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2589 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2590 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2591
2592 return CC_SUCCESS;
2593 }
2594
2595 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb)
2596 {
2597 unsigned int slotid;
2598 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK;
2599 if (slotid < 1 || slotid > xhci->numslots) {
2600 DPRINTF("xhci: bad slot id %d\n", slotid);
2601 event->ccode = CC_TRB_ERROR;
2602 return 0;
2603 } else if (!xhci->slots[slotid-1].enabled) {
2604 DPRINTF("xhci: slot id %d not enabled\n", slotid);
2605 event->ccode = CC_SLOT_NOT_ENABLED_ERROR;
2606 return 0;
2607 }
2608 return slotid;
2609 }
2610
2611 /* cleanup slot state on usb device detach */
2612 static void xhci_detach_slot(XHCIState *xhci, USBPort *uport)
2613 {
2614 int slot, ep;
2615
2616 for (slot = 0; slot < xhci->numslots; slot++) {
2617 if (xhci->slots[slot].uport == uport) {
2618 break;
2619 }
2620 }
2621 if (slot == xhci->numslots) {
2622 return;
2623 }
2624
2625 for (ep = 0; ep < 31; ep++) {
2626 if (xhci->slots[slot].eps[ep]) {
2627 xhci_ep_nuke_xfers(xhci, slot + 1, ep + 1, 0);
2628 }
2629 }
2630 xhci->slots[slot].uport = NULL;
2631 }
2632
2633 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
2634 {
2635 dma_addr_t ctx;
2636 uint8_t bw_ctx[xhci->numports+1];
2637
2638 DPRINTF("xhci_get_port_bandwidth()\n");
2639
2640 ctx = xhci_mask64(pctx);
2641
2642 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx);
2643
2644 /* TODO: actually implement real values here */
2645 bw_ctx[0] = 0;
2646 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */
2647 pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx));
2648
2649 return CC_SUCCESS;
2650 }
2651
2652 static uint32_t rotl(uint32_t v, unsigned count)
2653 {
2654 count &= 31;
2655 return (v << count) | (v >> (32 - count));
2656 }
2657
2658
2659 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
2660 {
2661 uint32_t val;
2662 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F));
2663 val += rotl(lo + 0x49434878, hi & 0x1F);
2664 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F);
2665 return ~val;
2666 }
2667
2668 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr)
2669 {
2670 PCIDevice *pci_dev = PCI_DEVICE(xhci);
2671 uint32_t buf[8];
2672 uint32_t obuf[8];
2673 dma_addr_t paddr = xhci_mask64(addr);
2674
2675 pci_dma_read(pci_dev, paddr, &buf, 32);
2676
2677 memcpy(obuf, buf, sizeof(obuf));
2678
2679 if ((buf[0] & 0xff) == 2) {
2680 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3];
2681 obuf[0] |= (buf[2] * buf[3]) & 0xff;
2682 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3];
2683 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3];
2684 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3];
2685 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3];
2686 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3];
2687 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956;
2688 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593;
2689 }
2690
2691 pci_dma_write(pci_dev, paddr, &obuf, 32);
2692 }
2693
2694 static void xhci_process_commands(XHCIState *xhci)
2695 {
2696 XHCITRB trb;
2697 TRBType type;
2698 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS};
2699 dma_addr_t addr;
2700 unsigned int i, slotid = 0;
2701
2702 DPRINTF("xhci_process_commands()\n");
2703 if (!xhci_running(xhci)) {
2704 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2705 return;
2706 }
2707
2708 xhci->crcr_low |= CRCR_CRR;
2709
2710 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {
2711 event.ptr = addr;
2712 switch (type) {
2713 case CR_ENABLE_SLOT:
2714 for (i = 0; i < xhci->numslots; i++) {
2715 if (!xhci->slots[i].enabled) {
2716 break;
2717 }
2718 }
2719 if (i >= xhci->numslots) {
2720 DPRINTF("xhci: no device slots available\n");
2721 event.ccode = CC_NO_SLOTS_ERROR;
2722 } else {
2723 slotid = i+1;
2724 event.ccode = xhci_enable_slot(xhci, slotid);
2725 }
2726 break;
2727 case CR_DISABLE_SLOT:
2728 slotid = xhci_get_slot(xhci, &event, &trb);
2729 if (slotid) {
2730 event.ccode = xhci_disable_slot(xhci, slotid);
2731 }
2732 break;
2733 case CR_ADDRESS_DEVICE:
2734 slotid = xhci_get_slot(xhci, &event, &trb);
2735 if (slotid) {
2736 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter,
2737 trb.control & TRB_CR_BSR);
2738 }
2739 break;
2740 case CR_CONFIGURE_ENDPOINT:
2741 slotid = xhci_get_slot(xhci, &event, &trb);
2742 if (slotid) {
2743 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter,
2744 trb.control & TRB_CR_DC);
2745 }
2746 break;
2747 case CR_EVALUATE_CONTEXT:
2748 slotid = xhci_get_slot(xhci, &event, &trb);
2749 if (slotid) {
2750 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter);
2751 }
2752 break;
2753 case CR_STOP_ENDPOINT:
2754 slotid = xhci_get_slot(xhci, &event, &trb);
2755 if (slotid) {
2756 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2757 & TRB_CR_EPID_MASK;
2758 event.ccode = xhci_stop_ep(xhci, slotid, epid);
2759 }
2760 break;
2761 case CR_RESET_ENDPOINT:
2762 slotid = xhci_get_slot(xhci, &event, &trb);
2763 if (slotid) {
2764 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2765 & TRB_CR_EPID_MASK;
2766 event.ccode = xhci_reset_ep(xhci, slotid, epid);
2767 }
2768 break;
2769 case CR_SET_TR_DEQUEUE:
2770 slotid = xhci_get_slot(xhci, &event, &trb);
2771 if (slotid) {
2772 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2773 & TRB_CR_EPID_MASK;
2774 unsigned int streamid = (trb.status >> 16) & 0xffff;
2775 event.ccode = xhci_set_ep_dequeue(xhci, slotid,
2776 epid, streamid,
2777 trb.parameter);
2778 }
2779 break;
2780 case CR_RESET_DEVICE:
2781 slotid = xhci_get_slot(xhci, &event, &trb);
2782 if (slotid) {
2783 event.ccode = xhci_reset_slot(xhci, slotid);
2784 }
2785 break;
2786 case CR_GET_PORT_BANDWIDTH:
2787 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter);
2788 break;
2789 case CR_VENDOR_VIA_CHALLENGE_RESPONSE:
2790 xhci_via_challenge(xhci, trb.parameter);
2791 break;
2792 case CR_VENDOR_NEC_FIRMWARE_REVISION:
2793 event.type = 48; /* NEC reply */
2794 event.length = 0x3025;
2795 break;
2796 case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
2797 {
2798 uint32_t chi = trb.parameter >> 32;
2799 uint32_t clo = trb.parameter;
2800 uint32_t val = xhci_nec_challenge(chi, clo);
2801 event.length = val & 0xFFFF;
2802 event.epid = val >> 16;
2803 slotid = val >> 24;
2804 event.type = 48; /* NEC reply */
2805 }
2806 break;
2807 default:
2808 trace_usb_xhci_unimplemented("command", type);
2809 event.ccode = CC_TRB_ERROR;
2810 break;
2811 }
2812 event.slotid = slotid;
2813 xhci_event(xhci, &event, 0);
2814 }
2815 }
2816
2817 static bool xhci_port_have_device(XHCIPort *port)
2818 {
2819 if (!port->uport->dev || !port->uport->dev->attached) {
2820 return false; /* no device present */
2821 }
2822 if (!((1 << port->uport->dev->speed) & port->speedmask)) {
2823 return false; /* speed mismatch */
2824 }
2825 return true;
2826 }
2827
2828 static void xhci_port_notify(XHCIPort *port, uint32_t bits)
2829 {
2830 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS,
2831 port->portnr << 24 };
2832
2833 if ((port->portsc & bits) == bits) {
2834 return;
2835 }
2836 trace_usb_xhci_port_notify(port->portnr, bits);
2837 port->portsc |= bits;
2838 if (!xhci_running(port->xhci)) {
2839 return;
2840 }
2841 xhci_event(port->xhci, &ev, 0);
2842 }
2843
2844 static void xhci_port_update(XHCIPort *port, int is_detach)
2845 {
2846 uint32_t pls = PLS_RX_DETECT;
2847
2848 port->portsc = PORTSC_PP;
2849 if (!is_detach && xhci_port_have_device(port)) {
2850 port->portsc |= PORTSC_CCS;
2851 switch (port->uport->dev->speed) {
2852 case USB_SPEED_LOW:
2853 port->portsc |= PORTSC_SPEED_LOW;
2854 pls = PLS_POLLING;
2855 break;
2856 case USB_SPEED_FULL:
2857 port->portsc |= PORTSC_SPEED_FULL;
2858 pls = PLS_POLLING;
2859 break;
2860 case USB_SPEED_HIGH:
2861 port->portsc |= PORTSC_SPEED_HIGH;
2862 pls = PLS_POLLING;
2863 break;
2864 case USB_SPEED_SUPER:
2865 port->portsc |= PORTSC_SPEED_SUPER;
2866 port->portsc |= PORTSC_PED;
2867 pls = PLS_U0;
2868 break;
2869 }
2870 }
2871 set_field(&port->portsc, pls, PORTSC_PLS);
2872 trace_usb_xhci_port_link(port->portnr, pls);
2873 xhci_port_notify(port, PORTSC_CSC);
2874 }
2875
2876 static void xhci_port_reset(XHCIPort *port, bool warm_reset)
2877 {
2878 trace_usb_xhci_port_reset(port->portnr, warm_reset);
2879
2880 if (!xhci_port_have_device(port)) {
2881 return;
2882 }
2883
2884 usb_device_reset(port->uport->dev);
2885
2886 switch (port->uport->dev->speed) {
2887 case USB_SPEED_SUPER:
2888 if (warm_reset) {
2889 port->portsc |= PORTSC_WRC;
2890 }
2891 /* fall through */
2892 case USB_SPEED_LOW:
2893 case USB_SPEED_FULL:
2894 case USB_SPEED_HIGH:
2895 set_field(&port->portsc, PLS_U0, PORTSC_PLS);
2896 trace_usb_xhci_port_link(port->portnr, PLS_U0);
2897 port->portsc |= PORTSC_PED;
2898 break;
2899 }
2900
2901 port->portsc &= ~PORTSC_PR;
2902 xhci_port_notify(port, PORTSC_PRC);
2903 }
2904
2905 static void xhci_reset(DeviceState *dev)
2906 {
2907 XHCIState *xhci = XHCI(dev);
2908 int i;
2909
2910 trace_usb_xhci_reset();
2911 if (!(xhci->usbsts & USBSTS_HCH)) {
2912 DPRINTF("xhci: reset while running!\n");
2913 }
2914
2915 xhci->usbcmd = 0;
2916 xhci->usbsts = USBSTS_HCH;
2917 xhci->dnctrl = 0;
2918 xhci->crcr_low = 0;
2919 xhci->crcr_high = 0;
2920 xhci->dcbaap_low = 0;
2921 xhci->dcbaap_high = 0;
2922 xhci->config = 0;
2923
2924 for (i = 0; i < xhci->numslots; i++) {
2925 xhci_disable_slot(xhci, i+1);
2926 }
2927
2928 for (i = 0; i < xhci->numports; i++) {
2929 xhci_port_update(xhci->ports + i, 0);
2930 }
2931
2932 for (i = 0; i < xhci->numintrs; i++) {
2933 xhci->intr[i].iman = 0;
2934 xhci->intr[i].imod = 0;
2935 xhci->intr[i].erstsz = 0;
2936 xhci->intr[i].erstba_low = 0;
2937 xhci->intr[i].erstba_high = 0;
2938 xhci->intr[i].erdp_low = 0;
2939 xhci->intr[i].erdp_high = 0;
2940 xhci->intr[i].msix_used = 0;
2941
2942 xhci->intr[i].er_ep_idx = 0;
2943 xhci->intr[i].er_pcs = 1;
2944 xhci->intr[i].er_full = 0;
2945 xhci->intr[i].ev_buffer_put = 0;
2946 xhci->intr[i].ev_buffer_get = 0;
2947 }
2948
2949 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
2950 xhci_mfwrap_update(xhci);
2951 }
2952
2953 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size)
2954 {
2955 XHCIState *xhci = ptr;
2956 uint32_t ret;
2957
2958 switch (reg) {
2959 case 0x00: /* HCIVERSION, CAPLENGTH */
2960 ret = 0x01000000 | LEN_CAP;
2961 break;
2962 case 0x04: /* HCSPARAMS 1 */
2963 ret = ((xhci->numports_2+xhci->numports_3)<<24)
2964 | (xhci->numintrs<<8) | xhci->numslots;
2965 break;
2966 case 0x08: /* HCSPARAMS 2 */
2967 ret = 0x0000000f;
2968 break;
2969 case 0x0c: /* HCSPARAMS 3 */
2970 ret = 0x00000000;
2971 break;
2972 case 0x10: /* HCCPARAMS */
2973 if (sizeof(dma_addr_t) == 4) {
2974 ret = 0x00080000 | (xhci->max_pstreams_mask << 12);
2975 } else {
2976 ret = 0x00080001 | (xhci->max_pstreams_mask << 12);
2977 }
2978 break;
2979 case 0x14: /* DBOFF */
2980 ret = OFF_DOORBELL;
2981 break;
2982 case 0x18: /* RTSOFF */
2983 ret = OFF_RUNTIME;
2984 break;
2985
2986 /* extended capabilities */
2987 case 0x20: /* Supported Protocol:00 */
2988 ret = 0x02000402; /* USB 2.0 */
2989 break;
2990 case 0x24: /* Supported Protocol:04 */
2991 ret = 0x20425355; /* "USB " */
2992 break;
2993 case 0x28: /* Supported Protocol:08 */
2994 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
2995 ret = (xhci->numports_2<<8) | (xhci->numports_3+1);
2996 } else {
2997 ret = (xhci->numports_2<<8) | 1;
2998 }
2999 break;
3000 case 0x2c: /* Supported Protocol:0c */
3001 ret = 0x00000000; /* reserved */
3002 break;
3003 case 0x30: /* Supported Protocol:00 */
3004 ret = 0x03000002; /* USB 3.0 */
3005 break;
3006 case 0x34: /* Supported Protocol:04 */
3007 ret = 0x20425355; /* "USB " */
3008 break;
3009 case 0x38: /* Supported Protocol:08 */
3010 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
3011 ret = (xhci->numports_3<<8) | 1;
3012 } else {
3013 ret = (xhci->numports_3<<8) | (xhci->numports_2+1);
3014 }
3015 break;
3016 case 0x3c: /* Supported Protocol:0c */
3017 ret = 0x00000000; /* reserved */
3018 break;
3019 default:
3020 trace_usb_xhci_unimplemented("cap read", reg);
3021 ret = 0;
3022 }
3023
3024 trace_usb_xhci_cap_read(reg, ret);
3025 return ret;
3026 }
3027
3028 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size)
3029 {
3030 XHCIPort *port = ptr;
3031 uint32_t ret;
3032
3033 switch (reg) {
3034 case 0x00: /* PORTSC */
3035 ret = port->portsc;
3036 break;
3037 case 0x04: /* PORTPMSC */
3038 case 0x08: /* PORTLI */
3039 ret = 0;
3040 break;
3041 case 0x0c: /* reserved */
3042 default:
3043 trace_usb_xhci_unimplemented("port read", reg);
3044 ret = 0;
3045 }
3046
3047 trace_usb_xhci_port_read(port->portnr, reg, ret);
3048 return ret;
3049 }
3050
3051 static void xhci_port_write(void *ptr, hwaddr reg,
3052 uint64_t val, unsigned size)
3053 {
3054 XHCIPort *port = ptr;
3055 uint32_t portsc, notify;
3056
3057 trace_usb_xhci_port_write(port->portnr, reg, val);
3058
3059 switch (reg) {
3060 case 0x00: /* PORTSC */
3061 /* write-1-to-start bits */
3062 if (val & PORTSC_WPR) {
3063 xhci_port_reset(port, true);
3064 break;
3065 }
3066 if (val & PORTSC_PR) {
3067 xhci_port_reset(port, false);
3068 break;
3069 }
3070
3071 portsc = port->portsc;
3072 notify = 0;
3073 /* write-1-to-clear bits*/
3074 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC|
3075 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC));
3076 if (val & PORTSC_LWS) {
3077 /* overwrite PLS only when LWS=1 */
3078 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS);
3079 uint32_t new_pls = get_field(val, PORTSC_PLS);
3080 switch (new_pls) {
3081 case PLS_U0:
3082 if (old_pls != PLS_U0) {
3083 set_field(&portsc, new_pls, PORTSC_PLS);
3084 trace_usb_xhci_port_link(port->portnr, new_pls);
3085 notify = PORTSC_PLC;
3086 }
3087 break;
3088 case PLS_U3:
3089 if (old_pls < PLS_U3) {
3090 set_field(&portsc, new_pls, PORTSC_PLS);
3091 trace_usb_xhci_port_link(port->portnr, new_pls);
3092 }
3093 break;
3094 case PLS_RESUME:
3095 /* windows does this for some reason, don't spam stderr */
3096 break;
3097 default:
3098 DPRINTF("%s: ignore pls write (old %d, new %d)\n",
3099 __func__, old_pls, new_pls);
3100 break;
3101 }
3102 }
3103 /* read/write bits */
3104 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE);
3105 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE));
3106 port->portsc = portsc;
3107 if (notify) {
3108 xhci_port_notify(port, notify);
3109 }
3110 break;
3111 case 0x04: /* PORTPMSC */
3112 case 0x08: /* PORTLI */
3113 default:
3114 trace_usb_xhci_unimplemented("port write", reg);
3115 }
3116 }
3117
3118 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size)
3119 {
3120 XHCIState *xhci = ptr;
3121 uint32_t ret;
3122
3123 switch (reg) {
3124 case 0x00: /* USBCMD */
3125 ret = xhci->usbcmd;
3126 break;
3127 case 0x04: /* USBSTS */
3128 ret = xhci->usbsts;
3129 break;
3130 case 0x08: /* PAGESIZE */
3131 ret = 1; /* 4KiB */
3132 break;
3133 case 0x14: /* DNCTRL */
3134 ret = xhci->dnctrl;
3135 break;
3136 case 0x18: /* CRCR low */
3137 ret = xhci->crcr_low & ~0xe;
3138 break;
3139 case 0x1c: /* CRCR high */
3140 ret = xhci->crcr_high;
3141 break;
3142 case 0x30: /* DCBAAP low */
3143 ret = xhci->dcbaap_low;
3144 break;
3145 case 0x34: /* DCBAAP high */
3146 ret = xhci->dcbaap_high;
3147 break;
3148 case 0x38: /* CONFIG */
3149 ret = xhci->config;
3150 break;
3151 default:
3152 trace_usb_xhci_unimplemented("oper read", reg);
3153 ret = 0;
3154 }
3155
3156 trace_usb_xhci_oper_read(reg, ret);
3157 return ret;
3158 }
3159
3160 static void xhci_oper_write(void *ptr, hwaddr reg,
3161 uint64_t val, unsigned size)
3162 {
3163 XHCIState *xhci = ptr;
3164 DeviceState *d = DEVICE(ptr);
3165
3166 trace_usb_xhci_oper_write(reg, val);
3167
3168 switch (reg) {
3169 case 0x00: /* USBCMD */
3170 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {
3171 xhci_run(xhci);
3172 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) {
3173 xhci_stop(xhci);
3174 }
3175 if (val & USBCMD_CSS) {
3176 /* save state */
3177 xhci->usbsts &= ~USBSTS_SRE;
3178 }
3179 if (val & USBCMD_CRS) {
3180 /* restore state */
3181 xhci->usbsts |= USBSTS_SRE;
3182 }
3183 xhci->usbcmd = val & 0xc0f;
3184 xhci_mfwrap_update(xhci);
3185 if (val & USBCMD_HCRST) {
3186 xhci_reset(d);
3187 }
3188 xhci_intx_update(xhci);
3189 break;
3190
3191 case 0x04: /* USBSTS */
3192 /* these bits are write-1-to-clear */
3193 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
3194 xhci_intx_update(xhci);
3195 break;
3196
3197 case 0x14: /* DNCTRL */
3198 xhci->dnctrl = val & 0xffff;
3199 break;
3200 case 0x18: /* CRCR low */
3201 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
3202 break;
3203 case 0x1c: /* CRCR high */
3204 xhci->crcr_high = val;
3205 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) {
3206 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED};
3207 xhci->crcr_low &= ~CRCR_CRR;
3208 xhci_event(xhci, &event, 0);
3209 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low);
3210 } else {
3211 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
3212 xhci_ring_init(xhci, &xhci->cmd_ring, base);
3213 }
3214 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS);
3215 break;
3216 case 0x30: /* DCBAAP low */
3217 xhci->dcbaap_low = val & 0xffffffc0;
3218 break;
3219 case 0x34: /* DCBAAP high */
3220 xhci->dcbaap_high = val;
3221 break;
3222 case 0x38: /* CONFIG */
3223 xhci->config = val & 0xff;
3224 break;
3225 default:
3226 trace_usb_xhci_unimplemented("oper write", reg);
3227 }
3228 }
3229
3230 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg,
3231 unsigned size)
3232 {
3233 XHCIState *xhci = ptr;
3234 uint32_t ret = 0;
3235
3236 if (reg < 0x20) {
3237 switch (reg) {
3238 case 0x00: /* MFINDEX */
3239 ret = xhci_mfindex_get(xhci) & 0x3fff;
3240 break;
3241 default:
3242 trace_usb_xhci_unimplemented("runtime read", reg);
3243 break;
3244 }
3245 } else {
3246 int v = (reg - 0x20) / 0x20;
3247 XHCIInterrupter *intr = &xhci->intr[v];
3248 switch (reg & 0x1f) {
3249 case 0x00: /* IMAN */
3250 ret = intr->iman;
3251 break;
3252 case 0x04: /* IMOD */
3253 ret = intr->imod;
3254 break;
3255 case 0x08: /* ERSTSZ */
3256 ret = intr->erstsz;
3257 break;
3258 case 0x10: /* ERSTBA low */
3259 ret = intr->erstba_low;
3260 break;
3261 case 0x14: /* ERSTBA high */
3262 ret = intr->erstba_high;
3263 break;
3264 case 0x18: /* ERDP low */
3265 ret = intr->erdp_low;
3266 break;
3267 case 0x1c: /* ERDP high */
3268 ret = intr->erdp_high;
3269 break;
3270 }
3271 }
3272
3273 trace_usb_xhci_runtime_read(reg, ret);
3274 return ret;
3275 }
3276
3277 static void xhci_runtime_write(void *ptr, hwaddr reg,
3278 uint64_t val, unsigned size)
3279 {
3280 XHCIState *xhci = ptr;
3281 int v = (reg - 0x20) / 0x20;
3282 XHCIInterrupter *intr = &xhci->intr[v];
3283 trace_usb_xhci_runtime_write(reg, val);
3284
3285 if (reg < 0x20) {
3286 trace_usb_xhci_unimplemented("runtime write", reg);
3287 return;
3288 }
3289
3290 switch (reg & 0x1f) {
3291 case 0x00: /* IMAN */
3292 if (val & IMAN_IP) {
3293 intr->iman &= ~IMAN_IP;
3294 }
3295 intr->iman &= ~IMAN_IE;
3296 intr->iman |= val & IMAN_IE;
3297 if (v == 0) {
3298 xhci_intx_update(xhci);
3299 }
3300 xhci_msix_update(xhci, v);
3301 break;
3302 case 0x04: /* IMOD */
3303 intr->imod = val;
3304 break;
3305 case 0x08: /* ERSTSZ */
3306 intr->erstsz = val & 0xffff;
3307 break;
3308 case 0x10: /* ERSTBA low */
3309 /* XXX NEC driver bug: it doesn't align this to 64 bytes
3310 intr->erstba_low = val & 0xffffffc0; */
3311 intr->erstba_low = val & 0xfffffff0;
3312 break;
3313 case 0x14: /* ERSTBA high */
3314 intr->erstba_high = val;
3315 xhci_er_reset(xhci, v);
3316 break;
3317 case 0x18: /* ERDP low */
3318 if (val & ERDP_EHB) {
3319 intr->erdp_low &= ~ERDP_EHB;
3320 }
3321 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB);
3322 break;
3323 case 0x1c: /* ERDP high */
3324 intr->erdp_high = val;
3325 xhci_events_update(xhci, v);
3326 break;
3327 default:
3328 trace_usb_xhci_unimplemented("oper write", reg);
3329 }
3330 }
3331
3332 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg,
3333 unsigned size)
3334 {
3335 /* doorbells always read as 0 */
3336 trace_usb_xhci_doorbell_read(reg, 0);
3337 return 0;
3338 }
3339
3340 static void xhci_doorbell_write(void *ptr, hwaddr reg,
3341 uint64_t val, unsigned size)
3342 {
3343 XHCIState *xhci = ptr;
3344 unsigned int epid, streamid;
3345
3346 trace_usb_xhci_doorbell_write(reg, val);
3347
3348 if (!xhci_running(xhci)) {
3349 DPRINTF("xhci: wrote doorbell while xHC stopped or paused\n");
3350 return;
3351 }
3352
3353 reg >>= 2;
3354
3355 if (reg == 0) {
3356 if (val == 0) {
3357 xhci_process_commands(xhci);
3358 } else {
3359 DPRINTF("xhci: bad doorbell 0 write: 0x%x\n",
3360 (uint32_t)val);
3361 }
3362 } else {
3363 epid = val & 0xff;
3364 streamid = (val >> 16) & 0xffff;
3365 if (reg > xhci->numslots) {
3366 DPRINTF("xhci: bad doorbell %d\n", (int)reg);
3367 } else if (epid > 31) {
3368 DPRINTF("xhci: bad doorbell %d write: 0x%x\n",
3369 (int)reg, (uint32_t)val);
3370 } else {
3371 xhci_kick_ep(xhci, reg, epid, streamid);
3372 }
3373 }
3374 }
3375
3376 static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val,
3377 unsigned width)
3378 {
3379 /* nothing */
3380 }
3381
3382 static const MemoryRegionOps xhci_cap_ops = {
3383 .read = xhci_cap_read,
3384 .write = xhci_cap_write,
3385 .valid.min_access_size = 1,
3386 .valid.max_access_size = 4,
3387 .impl.min_access_size = 4,
3388 .impl.max_access_size = 4,
3389 .endianness = DEVICE_LITTLE_ENDIAN,
3390 };
3391
3392 static const MemoryRegionOps xhci_oper_ops = {
3393 .read = xhci_oper_read,
3394 .write = xhci_oper_write,
3395 .valid.min_access_size = 4,
3396 .valid.max_access_size = 4,
3397 .endianness = DEVICE_LITTLE_ENDIAN,
3398 };
3399
3400 static const MemoryRegionOps xhci_port_ops = {
3401 .read = xhci_port_read,
3402 .write = xhci_port_write,
3403 .valid.min_access_size = 4,
3404 .valid.max_access_size = 4,
3405 .endianness = DEVICE_LITTLE_ENDIAN,
3406 };
3407
3408 static const MemoryRegionOps xhci_runtime_ops = {
3409 .read = xhci_runtime_read,
3410 .write = xhci_runtime_write,
3411 .valid.min_access_size = 4,
3412 .valid.max_access_size = 4,
3413 .endianness = DEVICE_LITTLE_ENDIAN,
3414 };
3415
3416 static const MemoryRegionOps xhci_doorbell_ops = {
3417 .read = xhci_doorbell_read,
3418 .write = xhci_doorbell_write,
3419 .valid.min_access_size = 4,
3420 .valid.max_access_size = 4,
3421 .endianness = DEVICE_LITTLE_ENDIAN,
3422 };
3423
3424 static void xhci_attach(USBPort *usbport)
3425 {
3426 XHCIState *xhci = usbport->opaque;
3427 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3428
3429 xhci_port_update(port, 0);
3430 }
3431
3432 static void xhci_detach(USBPort *usbport)
3433 {
3434 XHCIState *xhci = usbport->opaque;
3435 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3436
3437 xhci_detach_slot(xhci, usbport);
3438 xhci_port_update(port, 1);
3439 }
3440
3441 static void xhci_wakeup(USBPort *usbport)
3442 {
3443 XHCIState *xhci = usbport->opaque;
3444 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3445
3446 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) {
3447 return;
3448 }
3449 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS);
3450 xhci_port_notify(port, PORTSC_PLC);
3451 }
3452
3453 static void xhci_complete(USBPort *port, USBPacket *packet)
3454 {
3455 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet);
3456
3457 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
3458 xhci_ep_nuke_one_xfer(xfer, 0);
3459 return;
3460 }
3461 xhci_complete_packet(xfer);
3462 xhci_kick_ep(xfer->xhci, xfer->slotid, xfer->epid, xfer->streamid);
3463 }
3464
3465 static void xhci_child_detach(USBPort *uport, USBDevice *child)
3466 {
3467 USBBus *bus = usb_bus_from_device(child);
3468 XHCIState *xhci = container_of(bus, XHCIState, bus);
3469
3470 xhci_detach_slot(xhci, child->port);
3471 }
3472
3473 static USBPortOps xhci_uport_ops = {
3474 .attach = xhci_attach,
3475 .detach = xhci_detach,
3476 .wakeup = xhci_wakeup,
3477 .complete = xhci_complete,
3478 .child_detach = xhci_child_detach,
3479 };
3480
3481 static int xhci_find_epid(USBEndpoint *ep)
3482 {
3483 if (ep->nr == 0) {
3484 return 1;
3485 }
3486 if (ep->pid == USB_TOKEN_IN) {
3487 return ep->nr * 2 + 1;
3488 } else {
3489 return ep->nr * 2;
3490 }
3491 }
3492
3493 static USBEndpoint *xhci_epid_to_usbep(XHCIState *xhci,
3494 unsigned int slotid, unsigned int epid)
3495 {
3496 assert(slotid >= 1 && slotid <= xhci->numslots);
3497
3498 if (!xhci->slots[slotid - 1].uport) {
3499 return NULL;
3500 }
3501
3502 return usb_ep_get(xhci->slots[slotid - 1].uport->dev,
3503 (epid & 1) ? USB_TOKEN_IN : USB_TOKEN_OUT, epid >> 1);
3504 }
3505
3506 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep,
3507 unsigned int stream)
3508 {
3509 XHCIState *xhci = container_of(bus, XHCIState, bus);
3510 int slotid;
3511
3512 DPRINTF("%s\n", __func__);
3513 slotid = ep->dev->addr;
3514 if (slotid == 0 || !xhci->slots[slotid-1].enabled) {
3515 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr);
3516 return;
3517 }
3518 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream);
3519 }
3520
3521 static USBBusOps xhci_bus_ops = {
3522 .wakeup_endpoint = xhci_wakeup_endpoint,
3523 };
3524
3525 static void usb_xhci_init(XHCIState *xhci)
3526 {
3527 DeviceState *dev = DEVICE(xhci);
3528 XHCIPort *port;
3529 int i, usbports, speedmask;
3530
3531 xhci->usbsts = USBSTS_HCH;
3532
3533 if (xhci->numports_2 > MAXPORTS_2) {
3534 xhci->numports_2 = MAXPORTS_2;
3535 }
3536 if (xhci->numports_3 > MAXPORTS_3) {
3537 xhci->numports_3 = MAXPORTS_3;
3538 }
3539 usbports = MAX(xhci->numports_2, xhci->numports_3);
3540 xhci->numports = xhci->numports_2 + xhci->numports_3;
3541
3542 usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, dev);
3543
3544 for (i = 0; i < usbports; i++) {
3545 speedmask = 0;
3546 if (i < xhci->numports_2) {
3547 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
3548 port = &xhci->ports[i + xhci->numports_3];
3549 port->portnr = i + 1 + xhci->numports_3;
3550 } else {
3551 port = &xhci->ports[i];
3552 port->portnr = i + 1;
3553 }
3554 port->uport = &xhci->uports[i];
3555 port->speedmask =
3556 USB_SPEED_MASK_LOW |
3557 USB_SPEED_MASK_FULL |
3558 USB_SPEED_MASK_HIGH;
3559 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1);
3560 speedmask |= port->speedmask;
3561 }
3562 if (i < xhci->numports_3) {
3563 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
3564 port = &xhci->ports[i];
3565 port->portnr = i + 1;
3566 } else {
3567 port = &xhci->ports[i + xhci->numports_2];
3568 port->portnr = i + 1 + xhci->numports_2;
3569 }
3570 port->uport = &xhci->uports[i];
3571 port->speedmask = USB_SPEED_MASK_SUPER;
3572 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1);
3573 speedmask |= port->speedmask;
3574 }
3575 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i,
3576 &xhci_uport_ops, speedmask);
3577 }
3578 }
3579
3580 static void usb_xhci_realize(struct PCIDevice *dev, Error **errp)
3581 {
3582 int i, ret;
3583
3584 XHCIState *xhci = XHCI(dev);
3585
3586 dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */
3587 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
3588 dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
3589 dev->config[0x60] = 0x30; /* release number */
3590
3591 usb_xhci_init(xhci);
3592
3593 if (xhci->numintrs > MAXINTRS) {
3594 xhci->numintrs = MAXINTRS;
3595 }
3596 while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */
3597 xhci->numintrs++;
3598 }
3599 if (xhci->numintrs < 1) {
3600 xhci->numintrs = 1;
3601 }
3602 if (xhci->numslots > MAXSLOTS) {
3603 xhci->numslots = MAXSLOTS;
3604 }
3605 if (xhci->numslots < 1) {
3606 xhci->numslots = 1;
3607 }
3608 if (xhci_get_flag(xhci, XHCI_FLAG_ENABLE_STREAMS)) {
3609 xhci->max_pstreams_mask = 7; /* == 256 primary streams */
3610 } else {
3611 xhci->max_pstreams_mask = 0;
3612 }
3613
3614 xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci);
3615
3616 memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS);
3617 memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci,
3618 "capabilities", LEN_CAP);
3619 memory_region_init_io(&xhci->mem_oper, OBJECT(xhci), &xhci_oper_ops, xhci,
3620 "operational", 0x400);
3621 memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci), &xhci_runtime_ops, xhci,
3622 "runtime", LEN_RUNTIME);
3623 memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci), &xhci_doorbell_ops, xhci,
3624 "doorbell", LEN_DOORBELL);
3625
3626 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap);
3627 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper);
3628 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime);
3629 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell);
3630
3631 for (i = 0; i < xhci->numports; i++) {
3632 XHCIPort *port = &xhci->ports[i];
3633 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i;
3634 port->xhci = xhci;
3635 memory_region_init_io(&port->mem, OBJECT(xhci), &xhci_port_ops, port,
3636 port->name, 0x10);
3637 memory_region_add_subregion(&xhci->mem, offset, &port->mem);
3638 }
3639
3640 pci_register_bar(dev, 0,
3641 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
3642 &xhci->mem);
3643
3644 if (pci_bus_is_express(dev->bus) ||
3645 xhci_get_flag(xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) {
3646 ret = pcie_endpoint_cap_init(dev, 0xa0);
3647 assert(ret >= 0);
3648 }
3649
3650 if (xhci_get_flag(xhci, XHCI_FLAG_USE_MSI)) {
3651 msi_init(dev, 0x70, xhci->numintrs, true, false);
3652 }
3653 if (xhci_get_flag(xhci, XHCI_FLAG_USE_MSI_X)) {
3654 msix_init(dev, xhci->numintrs,
3655 &xhci->mem, 0, OFF_MSIX_TABLE,
3656 &xhci->mem, 0, OFF_MSIX_PBA,
3657 0x90);
3658 }
3659 }
3660
3661 static void usb_xhci_exit(PCIDevice *dev)
3662 {
3663 int i;
3664 XHCIState *xhci = XHCI(dev);
3665
3666 trace_usb_xhci_exit();
3667
3668 for (i = 0; i < xhci->numslots; i++) {
3669 xhci_disable_slot(xhci, i + 1);
3670 }
3671
3672 if (xhci->mfwrap_timer) {
3673 timer_del(xhci->mfwrap_timer);
3674 timer_free(xhci->mfwrap_timer);
3675 xhci->mfwrap_timer = NULL;
3676 }
3677
3678 memory_region_del_subregion(&xhci->mem, &xhci->mem_cap);
3679 memory_region_del_subregion(&xhci->mem, &xhci->mem_oper);
3680 memory_region_del_subregion(&xhci->mem, &xhci->mem_runtime);
3681 memory_region_del_subregion(&xhci->mem, &xhci->mem_doorbell);
3682
3683 for (i = 0; i < xhci->numports; i++) {
3684 XHCIPort *port = &xhci->ports[i];
3685 memory_region_del_subregion(&xhci->mem, &port->mem);
3686 }
3687
3688 /* destroy msix memory region */
3689 if (dev->msix_table && dev->msix_pba
3690 && dev->msix_entry_used) {
3691 memory_region_del_subregion(&xhci->mem, &dev->msix_table_mmio);
3692 memory_region_del_subregion(&xhci->mem, &dev->msix_pba_mmio);
3693 }
3694
3695 usb_bus_release(&xhci->bus);
3696 }
3697
3698 static int usb_xhci_post_load(void *opaque, int version_id)
3699 {
3700 XHCIState *xhci = opaque;
3701 PCIDevice *pci_dev = PCI_DEVICE(xhci);
3702 XHCISlot *slot;
3703 XHCIEPContext *epctx;
3704 dma_addr_t dcbaap, pctx;
3705 uint32_t slot_ctx[4];
3706 uint32_t ep_ctx[5];
3707 int slotid, epid, state, intr;
3708
3709 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
3710
3711 for (slotid = 1; slotid <= xhci->numslots; slotid++) {
3712 slot = &xhci->slots[slotid-1];
3713 if (!slot->addressed) {
3714 continue;
3715 }
3716 slot->ctx =
3717 xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid));
3718 xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx));
3719 slot->uport = xhci_lookup_uport(xhci, slot_ctx);
3720 if (!slot->uport) {
3721 /* should not happen, but may trigger on guest bugs */
3722 slot->enabled = 0;
3723 slot->addressed = 0;
3724 continue;
3725 }
3726 assert(slot->uport && slot->uport->dev);
3727
3728 for (epid = 1; epid <= 31; epid++) {
3729 pctx = slot->ctx + 32 * epid;
3730 xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx));
3731 state = ep_ctx[0] & EP_STATE_MASK;
3732 if (state == EP_DISABLED) {
3733 continue;
3734 }
3735 epctx = xhci_alloc_epctx(xhci, slotid, epid);
3736 slot->eps[epid-1] = epctx;
3737 xhci_init_epctx(epctx, pctx, ep_ctx);
3738 epctx->state = state;
3739 if (state == EP_RUNNING) {
3740 /* kick endpoint after vmload is finished */
3741 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
3742 }
3743 }
3744 }
3745
3746 for (intr = 0; intr < xhci->numintrs; intr++) {
3747 if (xhci->intr[intr].msix_used) {
3748 msix_vector_use(pci_dev, intr);
3749 } else {
3750 msix_vector_unuse(pci_dev, intr);
3751 }
3752 }
3753
3754 return 0;
3755 }
3756
3757 static const VMStateDescription vmstate_xhci_ring = {
3758 .name = "xhci-ring",
3759 .version_id = 1,
3760 .fields = (VMStateField[]) {
3761 VMSTATE_UINT64(dequeue, XHCIRing),
3762 VMSTATE_BOOL(ccs, XHCIRing),
3763 VMSTATE_END_OF_LIST()
3764 }
3765 };
3766
3767 static const VMStateDescription vmstate_xhci_port = {
3768 .name = "xhci-port",
3769 .version_id = 1,
3770 .fields = (VMStateField[]) {
3771 VMSTATE_UINT32(portsc, XHCIPort),
3772 VMSTATE_END_OF_LIST()
3773 }
3774 };
3775
3776 static const VMStateDescription vmstate_xhci_slot = {
3777 .name = "xhci-slot",
3778 .version_id = 1,
3779 .fields = (VMStateField[]) {
3780 VMSTATE_BOOL(enabled, XHCISlot),
3781 VMSTATE_BOOL(addressed, XHCISlot),
3782 VMSTATE_END_OF_LIST()
3783 }
3784 };
3785
3786 static const VMStateDescription vmstate_xhci_event = {
3787 .name = "xhci-event",
3788 .version_id = 1,
3789 .fields = (VMStateField[]) {
3790 VMSTATE_UINT32(type, XHCIEvent),
3791 VMSTATE_UINT32(ccode, XHCIEvent),
3792 VMSTATE_UINT64(ptr, XHCIEvent),
3793 VMSTATE_UINT32(length, XHCIEvent),
3794 VMSTATE_UINT32(flags, XHCIEvent),
3795 VMSTATE_UINT8(slotid, XHCIEvent),
3796 VMSTATE_UINT8(epid, XHCIEvent),
3797 VMSTATE_END_OF_LIST()
3798 }
3799 };
3800
3801 static bool xhci_er_full(void *opaque, int version_id)
3802 {
3803 struct XHCIInterrupter *intr = opaque;
3804 return intr->er_full;
3805 }
3806
3807 static const VMStateDescription vmstate_xhci_intr = {
3808 .name = "xhci-intr",
3809 .version_id = 1,
3810 .fields = (VMStateField[]) {
3811 /* registers */
3812 VMSTATE_UINT32(iman, XHCIInterrupter),
3813 VMSTATE_UINT32(imod, XHCIInterrupter),
3814 VMSTATE_UINT32(erstsz, XHCIInterrupter),
3815 VMSTATE_UINT32(erstba_low, XHCIInterrupter),
3816 VMSTATE_UINT32(erstba_high, XHCIInterrupter),
3817 VMSTATE_UINT32(erdp_low, XHCIInterrupter),
3818 VMSTATE_UINT32(erdp_high, XHCIInterrupter),
3819
3820 /* state */
3821 VMSTATE_BOOL(msix_used, XHCIInterrupter),
3822 VMSTATE_BOOL(er_pcs, XHCIInterrupter),
3823 VMSTATE_UINT64(er_start, XHCIInterrupter),
3824 VMSTATE_UINT32(er_size, XHCIInterrupter),
3825 VMSTATE_UINT32(er_ep_idx, XHCIInterrupter),
3826
3827 /* event queue (used if ring is full) */
3828 VMSTATE_BOOL(er_full, XHCIInterrupter),
3829 VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full),
3830 VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full),
3831 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE,
3832 xhci_er_full, 1,
3833 vmstate_xhci_event, XHCIEvent),
3834
3835 VMSTATE_END_OF_LIST()
3836 }
3837 };
3838
3839 static const VMStateDescription vmstate_xhci = {
3840 .name = "xhci",
3841 .version_id = 1,
3842 .post_load = usb_xhci_post_load,
3843 .fields = (VMStateField[]) {
3844 VMSTATE_PCIE_DEVICE(parent_obj, XHCIState),
3845 VMSTATE_MSIX(parent_obj, XHCIState),
3846
3847 VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1,
3848 vmstate_xhci_port, XHCIPort),
3849 VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1,
3850 vmstate_xhci_slot, XHCISlot),
3851 VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1,
3852 vmstate_xhci_intr, XHCIInterrupter),
3853
3854 /* Operational Registers */
3855 VMSTATE_UINT32(usbcmd, XHCIState),
3856 VMSTATE_UINT32(usbsts, XHCIState),
3857 VMSTATE_UINT32(dnctrl, XHCIState),
3858 VMSTATE_UINT32(crcr_low, XHCIState),
3859 VMSTATE_UINT32(crcr_high, XHCIState),
3860 VMSTATE_UINT32(dcbaap_low, XHCIState),
3861 VMSTATE_UINT32(dcbaap_high, XHCIState),
3862 VMSTATE_UINT32(config, XHCIState),
3863
3864 /* Runtime Registers & state */
3865 VMSTATE_INT64(mfindex_start, XHCIState),
3866 VMSTATE_TIMER_PTR(mfwrap_timer, XHCIState),
3867 VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing),
3868
3869 VMSTATE_END_OF_LIST()
3870 }
3871 };
3872
3873 static Property xhci_properties[] = {
3874 DEFINE_PROP_BIT("msi", XHCIState, flags, XHCI_FLAG_USE_MSI, true),
3875 DEFINE_PROP_BIT("msix", XHCIState, flags, XHCI_FLAG_USE_MSI_X, true),
3876 DEFINE_PROP_BIT("superspeed-ports-first",
3877 XHCIState, flags, XHCI_FLAG_SS_FIRST, true),
3878 DEFINE_PROP_BIT("force-pcie-endcap", XHCIState, flags,
3879 XHCI_FLAG_FORCE_PCIE_ENDCAP, false),
3880 DEFINE_PROP_BIT("streams", XHCIState, flags,
3881 XHCI_FLAG_ENABLE_STREAMS, true),
3882 DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS),
3883 DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS),
3884 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4),
3885 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4),
3886 DEFINE_PROP_END_OF_LIST(),
3887 };
3888
3889 static void xhci_class_init(ObjectClass *klass, void *data)
3890 {
3891 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3892 DeviceClass *dc = DEVICE_CLASS(klass);
3893
3894 dc->vmsd = &vmstate_xhci;
3895 dc->props = xhci_properties;
3896 dc->reset = xhci_reset;
3897 set_bit(DEVICE_CATEGORY_USB, dc->categories);
3898 k->realize = usb_xhci_realize;
3899 k->exit = usb_xhci_exit;
3900 k->vendor_id = PCI_VENDOR_ID_NEC;
3901 k->device_id = PCI_DEVICE_ID_NEC_UPD720200;
3902 k->class_id = PCI_CLASS_SERIAL_USB;
3903 k->revision = 0x03;
3904 k->is_express = 1;
3905 }
3906
3907 static const TypeInfo xhci_info = {
3908 .name = TYPE_XHCI,
3909 .parent = TYPE_PCI_DEVICE,
3910 .instance_size = sizeof(XHCIState),
3911 .class_init = xhci_class_init,
3912 };
3913
3914 static void xhci_register_types(void)
3915 {
3916 type_register_static(&xhci_info);
3917 }
3918
3919 type_init(xhci_register_types)
QEMU mirror