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xhci: drop XHCITransfer->{slotid,epid}
[mirror_qemu.git] / hw / usb / hcd-xhci.c
1 /*
2 * USB xHCI controller emulation
3 *
4 * Copyright (c) 2011 Securiforest
5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com>
6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0
7 *
8 * This library is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU Lesser General Public
10 * License as published by the Free Software Foundation; either
11 * version 2 of the License, or (at your option) any later version.
12 *
13 * This library is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * Lesser General Public License for more details.
17 *
18 * You should have received a copy of the GNU Lesser General Public
19 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
20 */
21 #include "qemu/osdep.h"
22 #include "hw/hw.h"
23 #include "qemu/timer.h"
24 #include "qemu/queue.h"
25 #include "hw/usb.h"
26 #include "hw/pci/pci.h"
27 #include "hw/pci/msi.h"
28 #include "hw/pci/msix.h"
29 #include "trace.h"
30 #include "qapi/error.h"
31
32 //#define DEBUG_XHCI
33 //#define DEBUG_DATA
34
35 #ifdef DEBUG_XHCI
36 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__)
37 #else
38 #define DPRINTF(...) do {} while (0)
39 #endif
40 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \
41 __func__, __LINE__, _msg); abort(); } while (0)
42
43 #define MAXPORTS_2 15
44 #define MAXPORTS_3 15
45
46 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3)
47 #define MAXSLOTS 64
48 #define MAXINTRS 16
49
50 /* Very pessimistic, let's hope it's enough for all cases */
51 #define EV_QUEUE (((3 * 24) + 16) * MAXSLOTS)
52 /* Do not deliver ER Full events. NEC's driver does some things not bound
53 * to the specs when it gets them */
54 #define ER_FULL_HACK
55
56 #define TRB_LINK_LIMIT 4
57
58 #define LEN_CAP 0x40
59 #define LEN_OPER (0x400 + 0x10 * MAXPORTS)
60 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20)
61 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20)
62
63 #define OFF_OPER LEN_CAP
64 #define OFF_RUNTIME 0x1000
65 #define OFF_DOORBELL 0x2000
66 #define OFF_MSIX_TABLE 0x3000
67 #define OFF_MSIX_PBA 0x3800
68 /* must be power of 2 */
69 #define LEN_REGS 0x4000
70
71 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME
72 #error Increase OFF_RUNTIME
73 #endif
74 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL
75 #error Increase OFF_DOORBELL
76 #endif
77 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS
78 # error Increase LEN_REGS
79 #endif
80
81 /* bit definitions */
82 #define USBCMD_RS (1<<0)
83 #define USBCMD_HCRST (1<<1)
84 #define USBCMD_INTE (1<<2)
85 #define USBCMD_HSEE (1<<3)
86 #define USBCMD_LHCRST (1<<7)
87 #define USBCMD_CSS (1<<8)
88 #define USBCMD_CRS (1<<9)
89 #define USBCMD_EWE (1<<10)
90 #define USBCMD_EU3S (1<<11)
91
92 #define USBSTS_HCH (1<<0)
93 #define USBSTS_HSE (1<<2)
94 #define USBSTS_EINT (1<<3)
95 #define USBSTS_PCD (1<<4)
96 #define USBSTS_SSS (1<<8)
97 #define USBSTS_RSS (1<<9)
98 #define USBSTS_SRE (1<<10)
99 #define USBSTS_CNR (1<<11)
100 #define USBSTS_HCE (1<<12)
101
102
103 #define PORTSC_CCS (1<<0)
104 #define PORTSC_PED (1<<1)
105 #define PORTSC_OCA (1<<3)
106 #define PORTSC_PR (1<<4)
107 #define PORTSC_PLS_SHIFT 5
108 #define PORTSC_PLS_MASK 0xf
109 #define PORTSC_PP (1<<9)
110 #define PORTSC_SPEED_SHIFT 10
111 #define PORTSC_SPEED_MASK 0xf
112 #define PORTSC_SPEED_FULL (1<<10)
113 #define PORTSC_SPEED_LOW (2<<10)
114 #define PORTSC_SPEED_HIGH (3<<10)
115 #define PORTSC_SPEED_SUPER (4<<10)
116 #define PORTSC_PIC_SHIFT 14
117 #define PORTSC_PIC_MASK 0x3
118 #define PORTSC_LWS (1<<16)
119 #define PORTSC_CSC (1<<17)
120 #define PORTSC_PEC (1<<18)
121 #define PORTSC_WRC (1<<19)
122 #define PORTSC_OCC (1<<20)
123 #define PORTSC_PRC (1<<21)
124 #define PORTSC_PLC (1<<22)
125 #define PORTSC_CEC (1<<23)
126 #define PORTSC_CAS (1<<24)
127 #define PORTSC_WCE (1<<25)
128 #define PORTSC_WDE (1<<26)
129 #define PORTSC_WOE (1<<27)
130 #define PORTSC_DR (1<<30)
131 #define PORTSC_WPR (1<<31)
132
133 #define CRCR_RCS (1<<0)
134 #define CRCR_CS (1<<1)
135 #define CRCR_CA (1<<2)
136 #define CRCR_CRR (1<<3)
137
138 #define IMAN_IP (1<<0)
139 #define IMAN_IE (1<<1)
140
141 #define ERDP_EHB (1<<3)
142
143 #define TRB_SIZE 16
144 typedef struct XHCITRB {
145 uint64_t parameter;
146 uint32_t status;
147 uint32_t control;
148 dma_addr_t addr;
149 bool ccs;
150 } XHCITRB;
151
152 enum {
153 PLS_U0 = 0,
154 PLS_U1 = 1,
155 PLS_U2 = 2,
156 PLS_U3 = 3,
157 PLS_DISABLED = 4,
158 PLS_RX_DETECT = 5,
159 PLS_INACTIVE = 6,
160 PLS_POLLING = 7,
161 PLS_RECOVERY = 8,
162 PLS_HOT_RESET = 9,
163 PLS_COMPILANCE_MODE = 10,
164 PLS_TEST_MODE = 11,
165 PLS_RESUME = 15,
166 };
167
168 typedef enum TRBType {
169 TRB_RESERVED = 0,
170 TR_NORMAL,
171 TR_SETUP,
172 TR_DATA,
173 TR_STATUS,
174 TR_ISOCH,
175 TR_LINK,
176 TR_EVDATA,
177 TR_NOOP,
178 CR_ENABLE_SLOT,
179 CR_DISABLE_SLOT,
180 CR_ADDRESS_DEVICE,
181 CR_CONFIGURE_ENDPOINT,
182 CR_EVALUATE_CONTEXT,
183 CR_RESET_ENDPOINT,
184 CR_STOP_ENDPOINT,
185 CR_SET_TR_DEQUEUE,
186 CR_RESET_DEVICE,
187 CR_FORCE_EVENT,
188 CR_NEGOTIATE_BW,
189 CR_SET_LATENCY_TOLERANCE,
190 CR_GET_PORT_BANDWIDTH,
191 CR_FORCE_HEADER,
192 CR_NOOP,
193 ER_TRANSFER = 32,
194 ER_COMMAND_COMPLETE,
195 ER_PORT_STATUS_CHANGE,
196 ER_BANDWIDTH_REQUEST,
197 ER_DOORBELL,
198 ER_HOST_CONTROLLER,
199 ER_DEVICE_NOTIFICATION,
200 ER_MFINDEX_WRAP,
201 /* vendor specific bits */
202 CR_VENDOR_VIA_CHALLENGE_RESPONSE = 48,
203 CR_VENDOR_NEC_FIRMWARE_REVISION = 49,
204 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50,
205 } TRBType;
206
207 #define CR_LINK TR_LINK
208
209 typedef enum TRBCCode {
210 CC_INVALID = 0,
211 CC_SUCCESS,
212 CC_DATA_BUFFER_ERROR,
213 CC_BABBLE_DETECTED,
214 CC_USB_TRANSACTION_ERROR,
215 CC_TRB_ERROR,
216 CC_STALL_ERROR,
217 CC_RESOURCE_ERROR,
218 CC_BANDWIDTH_ERROR,
219 CC_NO_SLOTS_ERROR,
220 CC_INVALID_STREAM_TYPE_ERROR,
221 CC_SLOT_NOT_ENABLED_ERROR,
222 CC_EP_NOT_ENABLED_ERROR,
223 CC_SHORT_PACKET,
224 CC_RING_UNDERRUN,
225 CC_RING_OVERRUN,
226 CC_VF_ER_FULL,
227 CC_PARAMETER_ERROR,
228 CC_BANDWIDTH_OVERRUN,
229 CC_CONTEXT_STATE_ERROR,
230 CC_NO_PING_RESPONSE_ERROR,
231 CC_EVENT_RING_FULL_ERROR,
232 CC_INCOMPATIBLE_DEVICE_ERROR,
233 CC_MISSED_SERVICE_ERROR,
234 CC_COMMAND_RING_STOPPED,
235 CC_COMMAND_ABORTED,
236 CC_STOPPED,
237 CC_STOPPED_LENGTH_INVALID,
238 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29,
239 CC_ISOCH_BUFFER_OVERRUN = 31,
240 CC_EVENT_LOST_ERROR,
241 CC_UNDEFINED_ERROR,
242 CC_INVALID_STREAM_ID_ERROR,
243 CC_SECONDARY_BANDWIDTH_ERROR,
244 CC_SPLIT_TRANSACTION_ERROR
245 } TRBCCode;
246
247 #define TRB_C (1<<0)
248 #define TRB_TYPE_SHIFT 10
249 #define TRB_TYPE_MASK 0x3f
250 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK)
251
252 #define TRB_EV_ED (1<<2)
253
254 #define TRB_TR_ENT (1<<1)
255 #define TRB_TR_ISP (1<<2)
256 #define TRB_TR_NS (1<<3)
257 #define TRB_TR_CH (1<<4)
258 #define TRB_TR_IOC (1<<5)
259 #define TRB_TR_IDT (1<<6)
260 #define TRB_TR_TBC_SHIFT 7
261 #define TRB_TR_TBC_MASK 0x3
262 #define TRB_TR_BEI (1<<9)
263 #define TRB_TR_TLBPC_SHIFT 16
264 #define TRB_TR_TLBPC_MASK 0xf
265 #define TRB_TR_FRAMEID_SHIFT 20
266 #define TRB_TR_FRAMEID_MASK 0x7ff
267 #define TRB_TR_SIA (1<<31)
268
269 #define TRB_TR_DIR (1<<16)
270
271 #define TRB_CR_SLOTID_SHIFT 24
272 #define TRB_CR_SLOTID_MASK 0xff
273 #define TRB_CR_EPID_SHIFT 16
274 #define TRB_CR_EPID_MASK 0x1f
275
276 #define TRB_CR_BSR (1<<9)
277 #define TRB_CR_DC (1<<9)
278
279 #define TRB_LK_TC (1<<1)
280
281 #define TRB_INTR_SHIFT 22
282 #define TRB_INTR_MASK 0x3ff
283 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK)
284
285 #define EP_TYPE_MASK 0x7
286 #define EP_TYPE_SHIFT 3
287
288 #define EP_STATE_MASK 0x7
289 #define EP_DISABLED (0<<0)
290 #define EP_RUNNING (1<<0)
291 #define EP_HALTED (2<<0)
292 #define EP_STOPPED (3<<0)
293 #define EP_ERROR (4<<0)
294
295 #define SLOT_STATE_MASK 0x1f
296 #define SLOT_STATE_SHIFT 27
297 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK)
298 #define SLOT_ENABLED 0
299 #define SLOT_DEFAULT 1
300 #define SLOT_ADDRESSED 2
301 #define SLOT_CONFIGURED 3
302
303 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f
304 #define SLOT_CONTEXT_ENTRIES_SHIFT 27
305
306 typedef struct XHCIState XHCIState;
307 typedef struct XHCIStreamContext XHCIStreamContext;
308 typedef struct XHCIEPContext XHCIEPContext;
309
310 #define get_field(data, field) \
311 (((data) >> field##_SHIFT) & field##_MASK)
312
313 #define set_field(data, newval, field) do { \
314 uint32_t val = *data; \
315 val &= ~(field##_MASK << field##_SHIFT); \
316 val |= ((newval) & field##_MASK) << field##_SHIFT; \
317 *data = val; \
318 } while (0)
319
320 typedef enum EPType {
321 ET_INVALID = 0,
322 ET_ISO_OUT,
323 ET_BULK_OUT,
324 ET_INTR_OUT,
325 ET_CONTROL,
326 ET_ISO_IN,
327 ET_BULK_IN,
328 ET_INTR_IN,
329 } EPType;
330
331 typedef struct XHCIRing {
332 dma_addr_t dequeue;
333 bool ccs;
334 } XHCIRing;
335
336 typedef struct XHCIPort {
337 XHCIState *xhci;
338 uint32_t portsc;
339 uint32_t portnr;
340 USBPort *uport;
341 uint32_t speedmask;
342 char name[16];
343 MemoryRegion mem;
344 } XHCIPort;
345
346 typedef struct XHCITransfer {
347 XHCIEPContext *epctx;
348 USBPacket packet;
349 QEMUSGList sgl;
350 bool running_async;
351 bool running_retry;
352 bool complete;
353 bool int_req;
354 unsigned int iso_pkts;
355 unsigned int streamid;
356 bool in_xfer;
357 bool iso_xfer;
358 bool timed_xfer;
359
360 unsigned int trb_count;
361 XHCITRB *trbs;
362
363 TRBCCode status;
364
365 unsigned int pkts;
366 unsigned int pktsize;
367 unsigned int cur_pkt;
368
369 uint64_t mfindex_kick;
370
371 QTAILQ_ENTRY(XHCITransfer) next;
372 } XHCITransfer;
373
374 struct XHCIStreamContext {
375 dma_addr_t pctx;
376 unsigned int sct;
377 XHCIRing ring;
378 };
379
380 struct XHCIEPContext {
381 XHCIState *xhci;
382 unsigned int slotid;
383 unsigned int epid;
384
385 XHCIRing ring;
386 uint32_t xfer_count;
387 QTAILQ_HEAD(, XHCITransfer) transfers;
388 XHCITransfer *retry;
389 EPType type;
390 dma_addr_t pctx;
391 unsigned int max_psize;
392 uint32_t state;
393
394 /* streams */
395 unsigned int max_pstreams;
396 bool lsa;
397 unsigned int nr_pstreams;
398 XHCIStreamContext *pstreams;
399
400 /* iso xfer scheduling */
401 unsigned int interval;
402 int64_t mfindex_last;
403 QEMUTimer *kick_timer;
404 };
405
406 typedef struct XHCISlot {
407 bool enabled;
408 bool addressed;
409 dma_addr_t ctx;
410 USBPort *uport;
411 XHCIEPContext * eps[31];
412 } XHCISlot;
413
414 typedef struct XHCIEvent {
415 TRBType type;
416 TRBCCode ccode;
417 uint64_t ptr;
418 uint32_t length;
419 uint32_t flags;
420 uint8_t slotid;
421 uint8_t epid;
422 } XHCIEvent;
423
424 typedef struct XHCIInterrupter {
425 uint32_t iman;
426 uint32_t imod;
427 uint32_t erstsz;
428 uint32_t erstba_low;
429 uint32_t erstba_high;
430 uint32_t erdp_low;
431 uint32_t erdp_high;
432
433 bool msix_used, er_pcs, er_full;
434
435 dma_addr_t er_start;
436 uint32_t er_size;
437 unsigned int er_ep_idx;
438
439 XHCIEvent ev_buffer[EV_QUEUE];
440 unsigned int ev_buffer_put;
441 unsigned int ev_buffer_get;
442
443 } XHCIInterrupter;
444
445 struct XHCIState {
446 /*< private >*/
447 PCIDevice parent_obj;
448 /*< public >*/
449
450 USBBus bus;
451 MemoryRegion mem;
452 MemoryRegion mem_cap;
453 MemoryRegion mem_oper;
454 MemoryRegion mem_runtime;
455 MemoryRegion mem_doorbell;
456
457 /* properties */
458 uint32_t numports_2;
459 uint32_t numports_3;
460 uint32_t numintrs;
461 uint32_t numslots;
462 uint32_t flags;
463 uint32_t max_pstreams_mask;
464 OnOffAuto msi;
465 OnOffAuto msix;
466
467 /* Operational Registers */
468 uint32_t usbcmd;
469 uint32_t usbsts;
470 uint32_t dnctrl;
471 uint32_t crcr_low;
472 uint32_t crcr_high;
473 uint32_t dcbaap_low;
474 uint32_t dcbaap_high;
475 uint32_t config;
476
477 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)];
478 XHCIPort ports[MAXPORTS];
479 XHCISlot slots[MAXSLOTS];
480 uint32_t numports;
481
482 /* Runtime Registers */
483 int64_t mfindex_start;
484 QEMUTimer *mfwrap_timer;
485 XHCIInterrupter intr[MAXINTRS];
486
487 XHCIRing cmd_ring;
488 };
489
490 #define TYPE_XHCI "nec-usb-xhci"
491
492 #define XHCI(obj) \
493 OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI)
494
495 typedef struct XHCIEvRingSeg {
496 uint32_t addr_low;
497 uint32_t addr_high;
498 uint32_t size;
499 uint32_t rsvd;
500 } XHCIEvRingSeg;
501
502 enum xhci_flags {
503 XHCI_FLAG_SS_FIRST = 1,
504 XHCI_FLAG_FORCE_PCIE_ENDCAP,
505 XHCI_FLAG_ENABLE_STREAMS,
506 };
507
508 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
509 unsigned int epid, unsigned int streamid);
510 static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid);
511 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
512 unsigned int epid);
513 static void xhci_xfer_report(XHCITransfer *xfer);
514 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v);
515 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v);
516 static USBEndpoint *xhci_epid_to_usbep(XHCIState *xhci,
517 unsigned int slotid, unsigned int epid);
518
519 static const char *TRBType_names[] = {
520 [TRB_RESERVED] = "TRB_RESERVED",
521 [TR_NORMAL] = "TR_NORMAL",
522 [TR_SETUP] = "TR_SETUP",
523 [TR_DATA] = "TR_DATA",
524 [TR_STATUS] = "TR_STATUS",
525 [TR_ISOCH] = "TR_ISOCH",
526 [TR_LINK] = "TR_LINK",
527 [TR_EVDATA] = "TR_EVDATA",
528 [TR_NOOP] = "TR_NOOP",
529 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT",
530 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT",
531 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE",
532 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT",
533 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT",
534 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT",
535 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT",
536 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE",
537 [CR_RESET_DEVICE] = "CR_RESET_DEVICE",
538 [CR_FORCE_EVENT] = "CR_FORCE_EVENT",
539 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW",
540 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE",
541 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH",
542 [CR_FORCE_HEADER] = "CR_FORCE_HEADER",
543 [CR_NOOP] = "CR_NOOP",
544 [ER_TRANSFER] = "ER_TRANSFER",
545 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE",
546 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE",
547 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST",
548 [ER_DOORBELL] = "ER_DOORBELL",
549 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER",
550 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION",
551 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP",
552 [CR_VENDOR_VIA_CHALLENGE_RESPONSE] = "CR_VENDOR_VIA_CHALLENGE_RESPONSE",
553 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION",
554 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE",
555 };
556
557 static const char *TRBCCode_names[] = {
558 [CC_INVALID] = "CC_INVALID",
559 [CC_SUCCESS] = "CC_SUCCESS",
560 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR",
561 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED",
562 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR",
563 [CC_TRB_ERROR] = "CC_TRB_ERROR",
564 [CC_STALL_ERROR] = "CC_STALL_ERROR",
565 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR",
566 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR",
567 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR",
568 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR",
569 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR",
570 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR",
571 [CC_SHORT_PACKET] = "CC_SHORT_PACKET",
572 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN",
573 [CC_RING_OVERRUN] = "CC_RING_OVERRUN",
574 [CC_VF_ER_FULL] = "CC_VF_ER_FULL",
575 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR",
576 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN",
577 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR",
578 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR",
579 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR",
580 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR",
581 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR",
582 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED",
583 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED",
584 [CC_STOPPED] = "CC_STOPPED",
585 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID",
586 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR]
587 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR",
588 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN",
589 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR",
590 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR",
591 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR",
592 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR",
593 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR",
594 };
595
596 static const char *ep_state_names[] = {
597 [EP_DISABLED] = "disabled",
598 [EP_RUNNING] = "running",
599 [EP_HALTED] = "halted",
600 [EP_STOPPED] = "stopped",
601 [EP_ERROR] = "error",
602 };
603
604 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen)
605 {
606 if (index >= llen || list[index] == NULL) {
607 return "???";
608 }
609 return list[index];
610 }
611
612 static const char *trb_name(XHCITRB *trb)
613 {
614 return lookup_name(TRB_TYPE(*trb), TRBType_names,
615 ARRAY_SIZE(TRBType_names));
616 }
617
618 static const char *event_name(XHCIEvent *event)
619 {
620 return lookup_name(event->ccode, TRBCCode_names,
621 ARRAY_SIZE(TRBCCode_names));
622 }
623
624 static const char *ep_state_name(uint32_t state)
625 {
626 return lookup_name(state, ep_state_names,
627 ARRAY_SIZE(ep_state_names));
628 }
629
630 static bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit)
631 {
632 return xhci->flags & (1 << bit);
633 }
634
635 static uint64_t xhci_mfindex_get(XHCIState *xhci)
636 {
637 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
638 return (now - xhci->mfindex_start) / 125000;
639 }
640
641 static void xhci_mfwrap_update(XHCIState *xhci)
642 {
643 const uint32_t bits = USBCMD_RS | USBCMD_EWE;
644 uint32_t mfindex, left;
645 int64_t now;
646
647 if ((xhci->usbcmd & bits) == bits) {
648 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
649 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff;
650 left = 0x4000 - mfindex;
651 timer_mod(xhci->mfwrap_timer, now + left * 125000);
652 } else {
653 timer_del(xhci->mfwrap_timer);
654 }
655 }
656
657 static void xhci_mfwrap_timer(void *opaque)
658 {
659 XHCIState *xhci = opaque;
660 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS };
661
662 xhci_event(xhci, &wrap, 0);
663 xhci_mfwrap_update(xhci);
664 }
665
666 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high)
667 {
668 if (sizeof(dma_addr_t) == 4) {
669 return low;
670 } else {
671 return low | (((dma_addr_t)high << 16) << 16);
672 }
673 }
674
675 static inline dma_addr_t xhci_mask64(uint64_t addr)
676 {
677 if (sizeof(dma_addr_t) == 4) {
678 return addr & 0xffffffff;
679 } else {
680 return addr;
681 }
682 }
683
684 static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr,
685 uint32_t *buf, size_t len)
686 {
687 int i;
688
689 assert((len % sizeof(uint32_t)) == 0);
690
691 pci_dma_read(PCI_DEVICE(xhci), addr, buf, len);
692
693 for (i = 0; i < (len / sizeof(uint32_t)); i++) {
694 buf[i] = le32_to_cpu(buf[i]);
695 }
696 }
697
698 static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr,
699 uint32_t *buf, size_t len)
700 {
701 int i;
702 uint32_t tmp[5];
703 uint32_t n = len / sizeof(uint32_t);
704
705 assert((len % sizeof(uint32_t)) == 0);
706 assert(n <= ARRAY_SIZE(tmp));
707
708 for (i = 0; i < n; i++) {
709 tmp[i] = cpu_to_le32(buf[i]);
710 }
711 pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len);
712 }
713
714 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
715 {
716 int index;
717
718 if (!uport->dev) {
719 return NULL;
720 }
721 switch (uport->dev->speed) {
722 case USB_SPEED_LOW:
723 case USB_SPEED_FULL:
724 case USB_SPEED_HIGH:
725 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
726 index = uport->index + xhci->numports_3;
727 } else {
728 index = uport->index;
729 }
730 break;
731 case USB_SPEED_SUPER:
732 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
733 index = uport->index;
734 } else {
735 index = uport->index + xhci->numports_2;
736 }
737 break;
738 default:
739 return NULL;
740 }
741 return &xhci->ports[index];
742 }
743
744 static void xhci_intx_update(XHCIState *xhci)
745 {
746 PCIDevice *pci_dev = PCI_DEVICE(xhci);
747 int level = 0;
748
749 if (msix_enabled(pci_dev) ||
750 msi_enabled(pci_dev)) {
751 return;
752 }
753
754 if (xhci->intr[0].iman & IMAN_IP &&
755 xhci->intr[0].iman & IMAN_IE &&
756 xhci->usbcmd & USBCMD_INTE) {
757 level = 1;
758 }
759
760 trace_usb_xhci_irq_intx(level);
761 pci_set_irq(pci_dev, level);
762 }
763
764 static void xhci_msix_update(XHCIState *xhci, int v)
765 {
766 PCIDevice *pci_dev = PCI_DEVICE(xhci);
767 bool enabled;
768
769 if (!msix_enabled(pci_dev)) {
770 return;
771 }
772
773 enabled = xhci->intr[v].iman & IMAN_IE;
774 if (enabled == xhci->intr[v].msix_used) {
775 return;
776 }
777
778 if (enabled) {
779 trace_usb_xhci_irq_msix_use(v);
780 msix_vector_use(pci_dev, v);
781 xhci->intr[v].msix_used = true;
782 } else {
783 trace_usb_xhci_irq_msix_unuse(v);
784 msix_vector_unuse(pci_dev, v);
785 xhci->intr[v].msix_used = false;
786 }
787 }
788
789 static void xhci_intr_raise(XHCIState *xhci, int v)
790 {
791 PCIDevice *pci_dev = PCI_DEVICE(xhci);
792
793 xhci->intr[v].erdp_low |= ERDP_EHB;
794 xhci->intr[v].iman |= IMAN_IP;
795 xhci->usbsts |= USBSTS_EINT;
796
797 if (!(xhci->intr[v].iman & IMAN_IE)) {
798 return;
799 }
800
801 if (!(xhci->usbcmd & USBCMD_INTE)) {
802 return;
803 }
804
805 if (msix_enabled(pci_dev)) {
806 trace_usb_xhci_irq_msix(v);
807 msix_notify(pci_dev, v);
808 return;
809 }
810
811 if (msi_enabled(pci_dev)) {
812 trace_usb_xhci_irq_msi(v);
813 msi_notify(pci_dev, v);
814 return;
815 }
816
817 if (v == 0) {
818 trace_usb_xhci_irq_intx(1);
819 pci_irq_assert(pci_dev);
820 }
821 }
822
823 static inline int xhci_running(XHCIState *xhci)
824 {
825 return !(xhci->usbsts & USBSTS_HCH) && !xhci->intr[0].er_full;
826 }
827
828 static void xhci_die(XHCIState *xhci)
829 {
830 xhci->usbsts |= USBSTS_HCE;
831 DPRINTF("xhci: asserted controller error\n");
832 }
833
834 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
835 {
836 PCIDevice *pci_dev = PCI_DEVICE(xhci);
837 XHCIInterrupter *intr = &xhci->intr[v];
838 XHCITRB ev_trb;
839 dma_addr_t addr;
840
841 ev_trb.parameter = cpu_to_le64(event->ptr);
842 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24));
843 ev_trb.control = (event->slotid << 24) | (event->epid << 16) |
844 event->flags | (event->type << TRB_TYPE_SHIFT);
845 if (intr->er_pcs) {
846 ev_trb.control |= TRB_C;
847 }
848 ev_trb.control = cpu_to_le32(ev_trb.control);
849
850 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb),
851 event_name(event), ev_trb.parameter,
852 ev_trb.status, ev_trb.control);
853
854 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx;
855 pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE);
856
857 intr->er_ep_idx++;
858 if (intr->er_ep_idx >= intr->er_size) {
859 intr->er_ep_idx = 0;
860 intr->er_pcs = !intr->er_pcs;
861 }
862 }
863
864 static void xhci_events_update(XHCIState *xhci, int v)
865 {
866 XHCIInterrupter *intr = &xhci->intr[v];
867 dma_addr_t erdp;
868 unsigned int dp_idx;
869 bool do_irq = 0;
870
871 if (xhci->usbsts & USBSTS_HCH) {
872 return;
873 }
874
875 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
876 if (erdp < intr->er_start ||
877 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {
878 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
879 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n",
880 v, intr->er_start, intr->er_size);
881 xhci_die(xhci);
882 return;
883 }
884 dp_idx = (erdp - intr->er_start) / TRB_SIZE;
885 assert(dp_idx < intr->er_size);
886
887 /* NEC didn't read section 4.9.4 of the spec (v1.0 p139 top Note) and thus
888 * deadlocks when the ER is full. Hack it by holding off events until
889 * the driver decides to free at least half of the ring */
890 if (intr->er_full) {
891 int er_free = dp_idx - intr->er_ep_idx;
892 if (er_free <= 0) {
893 er_free += intr->er_size;
894 }
895 if (er_free < (intr->er_size/2)) {
896 DPRINTF("xhci_events_update(): event ring still "
897 "more than half full (hack)\n");
898 return;
899 }
900 }
901
902 while (intr->ev_buffer_put != intr->ev_buffer_get) {
903 assert(intr->er_full);
904 if (((intr->er_ep_idx+1) % intr->er_size) == dp_idx) {
905 DPRINTF("xhci_events_update(): event ring full again\n");
906 #ifndef ER_FULL_HACK
907 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
908 xhci_write_event(xhci, &full, v);
909 #endif
910 do_irq = 1;
911 break;
912 }
913 XHCIEvent *event = &intr->ev_buffer[intr->ev_buffer_get];
914 xhci_write_event(xhci, event, v);
915 intr->ev_buffer_get++;
916 do_irq = 1;
917 if (intr->ev_buffer_get == EV_QUEUE) {
918 intr->ev_buffer_get = 0;
919 }
920 }
921
922 if (do_irq) {
923 xhci_intr_raise(xhci, v);
924 }
925
926 if (intr->er_full && intr->ev_buffer_put == intr->ev_buffer_get) {
927 DPRINTF("xhci_events_update(): event ring no longer full\n");
928 intr->er_full = 0;
929 }
930 }
931
932 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v)
933 {
934 XHCIInterrupter *intr;
935 dma_addr_t erdp;
936 unsigned int dp_idx;
937
938 if (v >= xhci->numintrs) {
939 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs);
940 return;
941 }
942 intr = &xhci->intr[v];
943
944 if (intr->er_full) {
945 DPRINTF("xhci_event(): ER full, queueing\n");
946 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) {
947 DPRINTF("xhci: event queue full, dropping event!\n");
948 return;
949 }
950 intr->ev_buffer[intr->ev_buffer_put++] = *event;
951 if (intr->ev_buffer_put == EV_QUEUE) {
952 intr->ev_buffer_put = 0;
953 }
954 return;
955 }
956
957 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high);
958 if (erdp < intr->er_start ||
959 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) {
960 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp);
961 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n",
962 v, intr->er_start, intr->er_size);
963 xhci_die(xhci);
964 return;
965 }
966
967 dp_idx = (erdp - intr->er_start) / TRB_SIZE;
968 assert(dp_idx < intr->er_size);
969
970 if ((intr->er_ep_idx+1) % intr->er_size == dp_idx) {
971 DPRINTF("xhci_event(): ER full, queueing\n");
972 #ifndef ER_FULL_HACK
973 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR};
974 xhci_write_event(xhci, &full);
975 #endif
976 intr->er_full = 1;
977 if (((intr->ev_buffer_put+1) % EV_QUEUE) == intr->ev_buffer_get) {
978 DPRINTF("xhci: event queue full, dropping event!\n");
979 return;
980 }
981 intr->ev_buffer[intr->ev_buffer_put++] = *event;
982 if (intr->ev_buffer_put == EV_QUEUE) {
983 intr->ev_buffer_put = 0;
984 }
985 } else {
986 xhci_write_event(xhci, event, v);
987 }
988
989 xhci_intr_raise(xhci, v);
990 }
991
992 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring,
993 dma_addr_t base)
994 {
995 ring->dequeue = base;
996 ring->ccs = 1;
997 }
998
999 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
1000 dma_addr_t *addr)
1001 {
1002 PCIDevice *pci_dev = PCI_DEVICE(xhci);
1003 uint32_t link_cnt = 0;
1004
1005 while (1) {
1006 TRBType type;
1007 pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE);
1008 trb->addr = ring->dequeue;
1009 trb->ccs = ring->ccs;
1010 le64_to_cpus(&trb->parameter);
1011 le32_to_cpus(&trb->status);
1012 le32_to_cpus(&trb->control);
1013
1014 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb),
1015 trb->parameter, trb->status, trb->control);
1016
1017 if ((trb->control & TRB_C) != ring->ccs) {
1018 return 0;
1019 }
1020
1021 type = TRB_TYPE(*trb);
1022
1023 if (type != TR_LINK) {
1024 if (addr) {
1025 *addr = ring->dequeue;
1026 }
1027 ring->dequeue += TRB_SIZE;
1028 return type;
1029 } else {
1030 if (++link_cnt > TRB_LINK_LIMIT) {
1031 return 0;
1032 }
1033 ring->dequeue = xhci_mask64(trb->parameter);
1034 if (trb->control & TRB_LK_TC) {
1035 ring->ccs = !ring->ccs;
1036 }
1037 }
1038 }
1039 }
1040
1041 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
1042 {
1043 PCIDevice *pci_dev = PCI_DEVICE(xhci);
1044 XHCITRB trb;
1045 int length = 0;
1046 dma_addr_t dequeue = ring->dequeue;
1047 bool ccs = ring->ccs;
1048 /* hack to bundle together the two/three TDs that make a setup transfer */
1049 bool control_td_set = 0;
1050 uint32_t link_cnt = 0;
1051
1052 while (1) {
1053 TRBType type;
1054 pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE);
1055 le64_to_cpus(&trb.parameter);
1056 le32_to_cpus(&trb.status);
1057 le32_to_cpus(&trb.control);
1058
1059 if ((trb.control & TRB_C) != ccs) {
1060 return -length;
1061 }
1062
1063 type = TRB_TYPE(trb);
1064
1065 if (type == TR_LINK) {
1066 if (++link_cnt > TRB_LINK_LIMIT) {
1067 return -length;
1068 }
1069 dequeue = xhci_mask64(trb.parameter);
1070 if (trb.control & TRB_LK_TC) {
1071 ccs = !ccs;
1072 }
1073 continue;
1074 }
1075
1076 length += 1;
1077 dequeue += TRB_SIZE;
1078
1079 if (type == TR_SETUP) {
1080 control_td_set = 1;
1081 } else if (type == TR_STATUS) {
1082 control_td_set = 0;
1083 }
1084
1085 if (!control_td_set && !(trb.control & TRB_TR_CH)) {
1086 return length;
1087 }
1088 }
1089 }
1090
1091 static void xhci_er_reset(XHCIState *xhci, int v)
1092 {
1093 XHCIInterrupter *intr = &xhci->intr[v];
1094 XHCIEvRingSeg seg;
1095
1096 if (intr->erstsz == 0) {
1097 /* disabled */
1098 intr->er_start = 0;
1099 intr->er_size = 0;
1100 return;
1101 }
1102 /* cache the (sole) event ring segment location */
1103 if (intr->erstsz != 1) {
1104 DPRINTF("xhci: invalid value for ERSTSZ: %d\n", intr->erstsz);
1105 xhci_die(xhci);
1106 return;
1107 }
1108 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high);
1109 pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg));
1110 le32_to_cpus(&seg.addr_low);
1111 le32_to_cpus(&seg.addr_high);
1112 le32_to_cpus(&seg.size);
1113 if (seg.size < 16 || seg.size > 4096) {
1114 DPRINTF("xhci: invalid value for segment size: %d\n", seg.size);
1115 xhci_die(xhci);
1116 return;
1117 }
1118 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high);
1119 intr->er_size = seg.size;
1120
1121 intr->er_ep_idx = 0;
1122 intr->er_pcs = 1;
1123 intr->er_full = 0;
1124
1125 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n",
1126 v, intr->er_start, intr->er_size);
1127 }
1128
1129 static void xhci_run(XHCIState *xhci)
1130 {
1131 trace_usb_xhci_run();
1132 xhci->usbsts &= ~USBSTS_HCH;
1133 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
1134 }
1135
1136 static void xhci_stop(XHCIState *xhci)
1137 {
1138 trace_usb_xhci_stop();
1139 xhci->usbsts |= USBSTS_HCH;
1140 xhci->crcr_low &= ~CRCR_CRR;
1141 }
1142
1143 static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count,
1144 dma_addr_t base)
1145 {
1146 XHCIStreamContext *stctx;
1147 unsigned int i;
1148
1149 stctx = g_new0(XHCIStreamContext, count);
1150 for (i = 0; i < count; i++) {
1151 stctx[i].pctx = base + i * 16;
1152 stctx[i].sct = -1;
1153 }
1154 return stctx;
1155 }
1156
1157 static void xhci_reset_streams(XHCIEPContext *epctx)
1158 {
1159 unsigned int i;
1160
1161 for (i = 0; i < epctx->nr_pstreams; i++) {
1162 epctx->pstreams[i].sct = -1;
1163 }
1164 }
1165
1166 static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base)
1167 {
1168 assert(epctx->pstreams == NULL);
1169 epctx->nr_pstreams = 2 << epctx->max_pstreams;
1170 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base);
1171 }
1172
1173 static void xhci_free_streams(XHCIEPContext *epctx)
1174 {
1175 assert(epctx->pstreams != NULL);
1176
1177 g_free(epctx->pstreams);
1178 epctx->pstreams = NULL;
1179 epctx->nr_pstreams = 0;
1180 }
1181
1182 static int xhci_epmask_to_eps_with_streams(XHCIState *xhci,
1183 unsigned int slotid,
1184 uint32_t epmask,
1185 XHCIEPContext **epctxs,
1186 USBEndpoint **eps)
1187 {
1188 XHCISlot *slot;
1189 XHCIEPContext *epctx;
1190 USBEndpoint *ep;
1191 int i, j;
1192
1193 assert(slotid >= 1 && slotid <= xhci->numslots);
1194
1195 slot = &xhci->slots[slotid - 1];
1196
1197 for (i = 2, j = 0; i <= 31; i++) {
1198 if (!(epmask & (1u << i))) {
1199 continue;
1200 }
1201
1202 epctx = slot->eps[i - 1];
1203 ep = xhci_epid_to_usbep(xhci, slotid, i);
1204 if (!epctx || !epctx->nr_pstreams || !ep) {
1205 continue;
1206 }
1207
1208 if (epctxs) {
1209 epctxs[j] = epctx;
1210 }
1211 eps[j++] = ep;
1212 }
1213 return j;
1214 }
1215
1216 static void xhci_free_device_streams(XHCIState *xhci, unsigned int slotid,
1217 uint32_t epmask)
1218 {
1219 USBEndpoint *eps[30];
1220 int nr_eps;
1221
1222 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, NULL, eps);
1223 if (nr_eps) {
1224 usb_device_free_streams(eps[0]->dev, eps, nr_eps);
1225 }
1226 }
1227
1228 static TRBCCode xhci_alloc_device_streams(XHCIState *xhci, unsigned int slotid,
1229 uint32_t epmask)
1230 {
1231 XHCIEPContext *epctxs[30];
1232 USBEndpoint *eps[30];
1233 int i, r, nr_eps, req_nr_streams, dev_max_streams;
1234
1235 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, epctxs,
1236 eps);
1237 if (nr_eps == 0) {
1238 return CC_SUCCESS;
1239 }
1240
1241 req_nr_streams = epctxs[0]->nr_pstreams;
1242 dev_max_streams = eps[0]->max_streams;
1243
1244 for (i = 1; i < nr_eps; i++) {
1245 /*
1246 * HdG: I don't expect these to ever trigger, but if they do we need
1247 * to come up with another solution, ie group identical endpoints
1248 * together and make an usb_device_alloc_streams call per group.
1249 */
1250 if (epctxs[i]->nr_pstreams != req_nr_streams) {
1251 FIXME("guest streams config not identical for all eps");
1252 return CC_RESOURCE_ERROR;
1253 }
1254 if (eps[i]->max_streams != dev_max_streams) {
1255 FIXME("device streams config not identical for all eps");
1256 return CC_RESOURCE_ERROR;
1257 }
1258 }
1259
1260 /*
1261 * max-streams in both the device descriptor and in the controller is a
1262 * power of 2. But stream id 0 is reserved, so if a device can do up to 4
1263 * streams the guest will ask for 5 rounded up to the next power of 2 which
1264 * becomes 8. For emulated devices usb_device_alloc_streams is a nop.
1265 *
1266 * For redirected devices however this is an issue, as there we must ask
1267 * the real xhci controller to alloc streams, and the host driver for the
1268 * real xhci controller will likely disallow allocating more streams then
1269 * the device can handle.
1270 *
1271 * So we limit the requested nr_streams to the maximum number the device
1272 * can handle.
1273 */
1274 if (req_nr_streams > dev_max_streams) {
1275 req_nr_streams = dev_max_streams;
1276 }
1277
1278 r = usb_device_alloc_streams(eps[0]->dev, eps, nr_eps, req_nr_streams);
1279 if (r != 0) {
1280 DPRINTF("xhci: alloc streams failed\n");
1281 return CC_RESOURCE_ERROR;
1282 }
1283
1284 return CC_SUCCESS;
1285 }
1286
1287 static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx,
1288 unsigned int streamid,
1289 uint32_t *cc_error)
1290 {
1291 XHCIStreamContext *sctx;
1292 dma_addr_t base;
1293 uint32_t ctx[2], sct;
1294
1295 assert(streamid != 0);
1296 if (epctx->lsa) {
1297 if (streamid >= epctx->nr_pstreams) {
1298 *cc_error = CC_INVALID_STREAM_ID_ERROR;
1299 return NULL;
1300 }
1301 sctx = epctx->pstreams + streamid;
1302 } else {
1303 FIXME("secondary streams not implemented yet");
1304 }
1305
1306 if (sctx->sct == -1) {
1307 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx));
1308 sct = (ctx[0] >> 1) & 0x07;
1309 if (epctx->lsa && sct != 1) {
1310 *cc_error = CC_INVALID_STREAM_TYPE_ERROR;
1311 return NULL;
1312 }
1313 sctx->sct = sct;
1314 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]);
1315 xhci_ring_init(epctx->xhci, &sctx->ring, base);
1316 }
1317 return sctx;
1318 }
1319
1320 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx,
1321 XHCIStreamContext *sctx, uint32_t state)
1322 {
1323 XHCIRing *ring = NULL;
1324 uint32_t ctx[5];
1325 uint32_t ctx2[2];
1326
1327 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1328 ctx[0] &= ~EP_STATE_MASK;
1329 ctx[0] |= state;
1330
1331 /* update ring dequeue ptr */
1332 if (epctx->nr_pstreams) {
1333 if (sctx != NULL) {
1334 ring = &sctx->ring;
1335 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1336 ctx2[0] &= 0xe;
1337 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs;
1338 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16;
1339 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2));
1340 }
1341 } else {
1342 ring = &epctx->ring;
1343 }
1344 if (ring) {
1345 ctx[2] = ring->dequeue | ring->ccs;
1346 ctx[3] = (ring->dequeue >> 16) >> 16;
1347
1348 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n",
1349 epctx->pctx, state, ctx[3], ctx[2]);
1350 }
1351
1352 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
1353 if (epctx->state != state) {
1354 trace_usb_xhci_ep_state(epctx->slotid, epctx->epid,
1355 ep_state_name(epctx->state),
1356 ep_state_name(state));
1357 }
1358 epctx->state = state;
1359 }
1360
1361 static void xhci_ep_kick_timer(void *opaque)
1362 {
1363 XHCIEPContext *epctx = opaque;
1364 xhci_kick_epctx(epctx, 0);
1365 }
1366
1367 static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci,
1368 unsigned int slotid,
1369 unsigned int epid)
1370 {
1371 XHCIEPContext *epctx;
1372
1373 epctx = g_new0(XHCIEPContext, 1);
1374 epctx->xhci = xhci;
1375 epctx->slotid = slotid;
1376 epctx->epid = epid;
1377
1378 QTAILQ_INIT(&epctx->transfers);
1379 epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx);
1380
1381 return epctx;
1382 }
1383
1384 static void xhci_init_epctx(XHCIEPContext *epctx,
1385 dma_addr_t pctx, uint32_t *ctx)
1386 {
1387 dma_addr_t dequeue;
1388
1389 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]);
1390
1391 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK;
1392 epctx->pctx = pctx;
1393 epctx->max_psize = ctx[1]>>16;
1394 epctx->max_psize *= 1+((ctx[1]>>8)&0xff);
1395 epctx->max_pstreams = (ctx[0] >> 10) & epctx->xhci->max_pstreams_mask;
1396 epctx->lsa = (ctx[0] >> 15) & 1;
1397 if (epctx->max_pstreams) {
1398 xhci_alloc_streams(epctx, dequeue);
1399 } else {
1400 xhci_ring_init(epctx->xhci, &epctx->ring, dequeue);
1401 epctx->ring.ccs = ctx[2] & 1;
1402 }
1403
1404 epctx->interval = 1 << ((ctx[0] >> 16) & 0xff);
1405 }
1406
1407 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid,
1408 unsigned int epid, dma_addr_t pctx,
1409 uint32_t *ctx)
1410 {
1411 XHCISlot *slot;
1412 XHCIEPContext *epctx;
1413
1414 trace_usb_xhci_ep_enable(slotid, epid);
1415 assert(slotid >= 1 && slotid <= xhci->numslots);
1416 assert(epid >= 1 && epid <= 31);
1417
1418 slot = &xhci->slots[slotid-1];
1419 if (slot->eps[epid-1]) {
1420 xhci_disable_ep(xhci, slotid, epid);
1421 }
1422
1423 epctx = xhci_alloc_epctx(xhci, slotid, epid);
1424 slot->eps[epid-1] = epctx;
1425 xhci_init_epctx(epctx, pctx, ctx);
1426
1427 DPRINTF("xhci: endpoint %d.%d type is %d, max transaction (burst) "
1428 "size is %d\n", epid/2, epid%2, epctx->type, epctx->max_psize);
1429
1430 epctx->mfindex_last = 0;
1431
1432 epctx->state = EP_RUNNING;
1433 ctx[0] &= ~EP_STATE_MASK;
1434 ctx[0] |= EP_RUNNING;
1435
1436 return CC_SUCCESS;
1437 }
1438
1439 static XHCITransfer *xhci_ep_alloc_xfer(XHCIEPContext *epctx,
1440 uint32_t length)
1441 {
1442 uint32_t limit = epctx->nr_pstreams + 16;
1443 XHCITransfer *xfer;
1444
1445 if (epctx->xfer_count >= limit) {
1446 return NULL;
1447 }
1448
1449 xfer = g_new0(XHCITransfer, 1);
1450 xfer->epctx = epctx;
1451 xfer->trbs = g_new(XHCITRB, length);
1452 xfer->trb_count = length;
1453 usb_packet_init(&xfer->packet);
1454
1455 QTAILQ_INSERT_TAIL(&epctx->transfers, xfer, next);
1456 epctx->xfer_count++;
1457
1458 return xfer;
1459 }
1460
1461 static void xhci_ep_free_xfer(XHCITransfer *xfer)
1462 {
1463 QTAILQ_REMOVE(&xfer->epctx->transfers, xfer, next);
1464 xfer->epctx->xfer_count--;
1465
1466 usb_packet_cleanup(&xfer->packet);
1467 g_free(xfer->trbs);
1468 g_free(xfer);
1469 }
1470
1471 static int xhci_ep_nuke_one_xfer(XHCITransfer *t, TRBCCode report)
1472 {
1473 int killed = 0;
1474
1475 if (report && (t->running_async || t->running_retry)) {
1476 t->status = report;
1477 xhci_xfer_report(t);
1478 }
1479
1480 if (t->running_async) {
1481 usb_cancel_packet(&t->packet);
1482 t->running_async = 0;
1483 killed = 1;
1484 }
1485 if (t->running_retry) {
1486 if (t->epctx) {
1487 t->epctx->retry = NULL;
1488 timer_del(t->epctx->kick_timer);
1489 }
1490 t->running_retry = 0;
1491 killed = 1;
1492 }
1493 g_free(t->trbs);
1494
1495 t->trbs = NULL;
1496 t->trb_count = 0;
1497
1498 return killed;
1499 }
1500
1501 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid,
1502 unsigned int epid, TRBCCode report)
1503 {
1504 XHCISlot *slot;
1505 XHCIEPContext *epctx;
1506 XHCITransfer *xfer;
1507 int killed = 0;
1508 USBEndpoint *ep = NULL;
1509 assert(slotid >= 1 && slotid <= xhci->numslots);
1510 assert(epid >= 1 && epid <= 31);
1511
1512 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid);
1513
1514 slot = &xhci->slots[slotid-1];
1515
1516 if (!slot->eps[epid-1]) {
1517 return 0;
1518 }
1519
1520 epctx = slot->eps[epid-1];
1521
1522 for (;;) {
1523 xfer = QTAILQ_FIRST(&epctx->transfers);
1524 if (xfer == NULL) {
1525 break;
1526 }
1527 killed += xhci_ep_nuke_one_xfer(xfer, report);
1528 if (killed) {
1529 report = 0; /* Only report once */
1530 }
1531 xhci_ep_free_xfer(xfer);
1532 }
1533
1534 ep = xhci_epid_to_usbep(xhci, slotid, epid);
1535 if (ep) {
1536 usb_device_ep_stopped(ep->dev, ep);
1537 }
1538 return killed;
1539 }
1540
1541 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid,
1542 unsigned int epid)
1543 {
1544 XHCISlot *slot;
1545 XHCIEPContext *epctx;
1546
1547 trace_usb_xhci_ep_disable(slotid, epid);
1548 assert(slotid >= 1 && slotid <= xhci->numslots);
1549 assert(epid >= 1 && epid <= 31);
1550
1551 slot = &xhci->slots[slotid-1];
1552
1553 if (!slot->eps[epid-1]) {
1554 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid);
1555 return CC_SUCCESS;
1556 }
1557
1558 xhci_ep_nuke_xfers(xhci, slotid, epid, 0);
1559
1560 epctx = slot->eps[epid-1];
1561
1562 if (epctx->nr_pstreams) {
1563 xhci_free_streams(epctx);
1564 }
1565
1566 /* only touch guest RAM if we're not resetting the HC */
1567 if (xhci->dcbaap_low || xhci->dcbaap_high) {
1568 xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED);
1569 }
1570
1571 timer_free(epctx->kick_timer);
1572 g_free(epctx);
1573 slot->eps[epid-1] = NULL;
1574
1575 return CC_SUCCESS;
1576 }
1577
1578 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid,
1579 unsigned int epid)
1580 {
1581 XHCISlot *slot;
1582 XHCIEPContext *epctx;
1583
1584 trace_usb_xhci_ep_stop(slotid, epid);
1585 assert(slotid >= 1 && slotid <= xhci->numslots);
1586
1587 if (epid < 1 || epid > 31) {
1588 DPRINTF("xhci: bad ep %d\n", epid);
1589 return CC_TRB_ERROR;
1590 }
1591
1592 slot = &xhci->slots[slotid-1];
1593
1594 if (!slot->eps[epid-1]) {
1595 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1596 return CC_EP_NOT_ENABLED_ERROR;
1597 }
1598
1599 if (xhci_ep_nuke_xfers(xhci, slotid, epid, CC_STOPPED) > 0) {
1600 DPRINTF("xhci: FIXME: endpoint stopped w/ xfers running, "
1601 "data might be lost\n");
1602 }
1603
1604 epctx = slot->eps[epid-1];
1605
1606 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1607
1608 if (epctx->nr_pstreams) {
1609 xhci_reset_streams(epctx);
1610 }
1611
1612 return CC_SUCCESS;
1613 }
1614
1615 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid,
1616 unsigned int epid)
1617 {
1618 XHCISlot *slot;
1619 XHCIEPContext *epctx;
1620
1621 trace_usb_xhci_ep_reset(slotid, epid);
1622 assert(slotid >= 1 && slotid <= xhci->numslots);
1623
1624 if (epid < 1 || epid > 31) {
1625 DPRINTF("xhci: bad ep %d\n", epid);
1626 return CC_TRB_ERROR;
1627 }
1628
1629 slot = &xhci->slots[slotid-1];
1630
1631 if (!slot->eps[epid-1]) {
1632 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1633 return CC_EP_NOT_ENABLED_ERROR;
1634 }
1635
1636 epctx = slot->eps[epid-1];
1637
1638 if (epctx->state != EP_HALTED) {
1639 DPRINTF("xhci: reset EP while EP %d not halted (%d)\n",
1640 epid, epctx->state);
1641 return CC_CONTEXT_STATE_ERROR;
1642 }
1643
1644 if (xhci_ep_nuke_xfers(xhci, slotid, epid, 0) > 0) {
1645 DPRINTF("xhci: FIXME: endpoint reset w/ xfers running, "
1646 "data might be lost\n");
1647 }
1648
1649 if (!xhci->slots[slotid-1].uport ||
1650 !xhci->slots[slotid-1].uport->dev ||
1651 !xhci->slots[slotid-1].uport->dev->attached) {
1652 return CC_USB_TRANSACTION_ERROR;
1653 }
1654
1655 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED);
1656
1657 if (epctx->nr_pstreams) {
1658 xhci_reset_streams(epctx);
1659 }
1660
1661 return CC_SUCCESS;
1662 }
1663
1664 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid,
1665 unsigned int epid, unsigned int streamid,
1666 uint64_t pdequeue)
1667 {
1668 XHCISlot *slot;
1669 XHCIEPContext *epctx;
1670 XHCIStreamContext *sctx;
1671 dma_addr_t dequeue;
1672
1673 assert(slotid >= 1 && slotid <= xhci->numslots);
1674
1675 if (epid < 1 || epid > 31) {
1676 DPRINTF("xhci: bad ep %d\n", epid);
1677 return CC_TRB_ERROR;
1678 }
1679
1680 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue);
1681 dequeue = xhci_mask64(pdequeue);
1682
1683 slot = &xhci->slots[slotid-1];
1684
1685 if (!slot->eps[epid-1]) {
1686 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid);
1687 return CC_EP_NOT_ENABLED_ERROR;
1688 }
1689
1690 epctx = slot->eps[epid-1];
1691
1692 if (epctx->state != EP_STOPPED) {
1693 DPRINTF("xhci: set EP dequeue pointer while EP %d not stopped\n", epid);
1694 return CC_CONTEXT_STATE_ERROR;
1695 }
1696
1697 if (epctx->nr_pstreams) {
1698 uint32_t err;
1699 sctx = xhci_find_stream(epctx, streamid, &err);
1700 if (sctx == NULL) {
1701 return err;
1702 }
1703 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf);
1704 sctx->ring.ccs = dequeue & 1;
1705 } else {
1706 sctx = NULL;
1707 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF);
1708 epctx->ring.ccs = dequeue & 1;
1709 }
1710
1711 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED);
1712
1713 return CC_SUCCESS;
1714 }
1715
1716 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer)
1717 {
1718 XHCIState *xhci = xfer->epctx->xhci;
1719 int i;
1720
1721 xfer->int_req = false;
1722 pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count);
1723 for (i = 0; i < xfer->trb_count; i++) {
1724 XHCITRB *trb = &xfer->trbs[i];
1725 dma_addr_t addr;
1726 unsigned int chunk = 0;
1727
1728 if (trb->control & TRB_TR_IOC) {
1729 xfer->int_req = true;
1730 }
1731
1732 switch (TRB_TYPE(*trb)) {
1733 case TR_DATA:
1734 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) {
1735 DPRINTF("xhci: data direction mismatch for TR_DATA\n");
1736 goto err;
1737 }
1738 /* fallthrough */
1739 case TR_NORMAL:
1740 case TR_ISOCH:
1741 addr = xhci_mask64(trb->parameter);
1742 chunk = trb->status & 0x1ffff;
1743 if (trb->control & TRB_TR_IDT) {
1744 if (chunk > 8 || in_xfer) {
1745 DPRINTF("xhci: invalid immediate data TRB\n");
1746 goto err;
1747 }
1748 qemu_sglist_add(&xfer->sgl, trb->addr, chunk);
1749 } else {
1750 qemu_sglist_add(&xfer->sgl, addr, chunk);
1751 }
1752 break;
1753 }
1754 }
1755
1756 return 0;
1757
1758 err:
1759 qemu_sglist_destroy(&xfer->sgl);
1760 xhci_die(xhci);
1761 return -1;
1762 }
1763
1764 static void xhci_xfer_unmap(XHCITransfer *xfer)
1765 {
1766 usb_packet_unmap(&xfer->packet, &xfer->sgl);
1767 qemu_sglist_destroy(&xfer->sgl);
1768 }
1769
1770 static void xhci_xfer_report(XHCITransfer *xfer)
1771 {
1772 uint32_t edtla = 0;
1773 unsigned int left;
1774 bool reported = 0;
1775 bool shortpkt = 0;
1776 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS};
1777 XHCIState *xhci = xfer->epctx->xhci;
1778 int i;
1779
1780 left = xfer->packet.actual_length;
1781
1782 for (i = 0; i < xfer->trb_count; i++) {
1783 XHCITRB *trb = &xfer->trbs[i];
1784 unsigned int chunk = 0;
1785
1786 switch (TRB_TYPE(*trb)) {
1787 case TR_SETUP:
1788 chunk = trb->status & 0x1ffff;
1789 if (chunk > 8) {
1790 chunk = 8;
1791 }
1792 break;
1793 case TR_DATA:
1794 case TR_NORMAL:
1795 case TR_ISOCH:
1796 chunk = trb->status & 0x1ffff;
1797 if (chunk > left) {
1798 chunk = left;
1799 if (xfer->status == CC_SUCCESS) {
1800 shortpkt = 1;
1801 }
1802 }
1803 left -= chunk;
1804 edtla += chunk;
1805 break;
1806 case TR_STATUS:
1807 reported = 0;
1808 shortpkt = 0;
1809 break;
1810 }
1811
1812 if (!reported && ((trb->control & TRB_TR_IOC) ||
1813 (shortpkt && (trb->control & TRB_TR_ISP)) ||
1814 (xfer->status != CC_SUCCESS && left == 0))) {
1815 event.slotid = xfer->epctx->slotid;
1816 event.epid = xfer->epctx->epid;
1817 event.length = (trb->status & 0x1ffff) - chunk;
1818 event.flags = 0;
1819 event.ptr = trb->addr;
1820 if (xfer->status == CC_SUCCESS) {
1821 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS;
1822 } else {
1823 event.ccode = xfer->status;
1824 }
1825 if (TRB_TYPE(*trb) == TR_EVDATA) {
1826 event.ptr = trb->parameter;
1827 event.flags |= TRB_EV_ED;
1828 event.length = edtla & 0xffffff;
1829 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length);
1830 edtla = 0;
1831 }
1832 xhci_event(xhci, &event, TRB_INTR(*trb));
1833 reported = 1;
1834 if (xfer->status != CC_SUCCESS) {
1835 return;
1836 }
1837 }
1838
1839 switch (TRB_TYPE(*trb)) {
1840 case TR_SETUP:
1841 reported = 0;
1842 shortpkt = 0;
1843 break;
1844 }
1845
1846 }
1847 }
1848
1849 static void xhci_stall_ep(XHCITransfer *xfer)
1850 {
1851 XHCIEPContext *epctx = xfer->epctx;
1852 XHCIState *xhci = epctx->xhci;
1853 uint32_t err;
1854 XHCIStreamContext *sctx;
1855
1856 if (epctx->nr_pstreams) {
1857 sctx = xhci_find_stream(epctx, xfer->streamid, &err);
1858 if (sctx == NULL) {
1859 return;
1860 }
1861 sctx->ring.dequeue = xfer->trbs[0].addr;
1862 sctx->ring.ccs = xfer->trbs[0].ccs;
1863 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED);
1864 } else {
1865 epctx->ring.dequeue = xfer->trbs[0].addr;
1866 epctx->ring.ccs = xfer->trbs[0].ccs;
1867 xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED);
1868 }
1869 }
1870
1871 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer,
1872 XHCIEPContext *epctx);
1873
1874 static int xhci_setup_packet(XHCITransfer *xfer)
1875 {
1876 XHCIState *xhci = xfer->epctx->xhci;
1877 USBEndpoint *ep;
1878 int dir;
1879
1880 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT;
1881
1882 if (xfer->packet.ep) {
1883 ep = xfer->packet.ep;
1884 } else {
1885 ep = xhci_epid_to_usbep(xhci, xfer->epctx->slotid, xfer->epctx->epid);
1886 if (!ep) {
1887 DPRINTF("xhci: slot %d has no device\n",
1888 xfer->slotid);
1889 return -1;
1890 }
1891 }
1892
1893 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */
1894 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid,
1895 xfer->trbs[0].addr, false, xfer->int_req);
1896 usb_packet_map(&xfer->packet, &xfer->sgl);
1897 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n",
1898 xfer->packet.pid, ep->dev->addr, ep->nr);
1899 return 0;
1900 }
1901
1902 static int xhci_complete_packet(XHCITransfer *xfer)
1903 {
1904 if (xfer->packet.status == USB_RET_ASYNC) {
1905 trace_usb_xhci_xfer_async(xfer);
1906 xfer->running_async = 1;
1907 xfer->running_retry = 0;
1908 xfer->complete = 0;
1909 return 0;
1910 } else if (xfer->packet.status == USB_RET_NAK) {
1911 trace_usb_xhci_xfer_nak(xfer);
1912 xfer->running_async = 0;
1913 xfer->running_retry = 1;
1914 xfer->complete = 0;
1915 return 0;
1916 } else {
1917 xfer->running_async = 0;
1918 xfer->running_retry = 0;
1919 xfer->complete = 1;
1920 xhci_xfer_unmap(xfer);
1921 }
1922
1923 if (xfer->packet.status == USB_RET_SUCCESS) {
1924 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length);
1925 xfer->status = CC_SUCCESS;
1926 xhci_xfer_report(xfer);
1927 return 0;
1928 }
1929
1930 /* error */
1931 trace_usb_xhci_xfer_error(xfer, xfer->packet.status);
1932 switch (xfer->packet.status) {
1933 case USB_RET_NODEV:
1934 case USB_RET_IOERROR:
1935 xfer->status = CC_USB_TRANSACTION_ERROR;
1936 xhci_xfer_report(xfer);
1937 xhci_stall_ep(xfer);
1938 break;
1939 case USB_RET_STALL:
1940 xfer->status = CC_STALL_ERROR;
1941 xhci_xfer_report(xfer);
1942 xhci_stall_ep(xfer);
1943 break;
1944 case USB_RET_BABBLE:
1945 xfer->status = CC_BABBLE_DETECTED;
1946 xhci_xfer_report(xfer);
1947 xhci_stall_ep(xfer);
1948 break;
1949 default:
1950 DPRINTF("%s: FIXME: status = %d\n", __func__,
1951 xfer->packet.status);
1952 FIXME("unhandled USB_RET_*");
1953 }
1954 return 0;
1955 }
1956
1957 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer)
1958 {
1959 XHCITRB *trb_setup, *trb_status;
1960 uint8_t bmRequestType;
1961
1962 trb_setup = &xfer->trbs[0];
1963 trb_status = &xfer->trbs[xfer->trb_count-1];
1964
1965 trace_usb_xhci_xfer_start(xfer, xfer->epctx->slotid,
1966 xfer->epctx->epid, xfer->streamid);
1967
1968 /* at most one Event Data TRB allowed after STATUS */
1969 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) {
1970 trb_status--;
1971 }
1972
1973 /* do some sanity checks */
1974 if (TRB_TYPE(*trb_setup) != TR_SETUP) {
1975 DPRINTF("xhci: ep0 first TD not SETUP: %d\n",
1976 TRB_TYPE(*trb_setup));
1977 return -1;
1978 }
1979 if (TRB_TYPE(*trb_status) != TR_STATUS) {
1980 DPRINTF("xhci: ep0 last TD not STATUS: %d\n",
1981 TRB_TYPE(*trb_status));
1982 return -1;
1983 }
1984 if (!(trb_setup->control & TRB_TR_IDT)) {
1985 DPRINTF("xhci: Setup TRB doesn't have IDT set\n");
1986 return -1;
1987 }
1988 if ((trb_setup->status & 0x1ffff) != 8) {
1989 DPRINTF("xhci: Setup TRB has bad length (%d)\n",
1990 (trb_setup->status & 0x1ffff));
1991 return -1;
1992 }
1993
1994 bmRequestType = trb_setup->parameter;
1995
1996 xfer->in_xfer = bmRequestType & USB_DIR_IN;
1997 xfer->iso_xfer = false;
1998 xfer->timed_xfer = false;
1999
2000 if (xhci_setup_packet(xfer) < 0) {
2001 return -1;
2002 }
2003 xfer->packet.parameter = trb_setup->parameter;
2004
2005 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
2006
2007 xhci_complete_packet(xfer);
2008 if (!xfer->running_async && !xfer->running_retry) {
2009 xhci_kick_epctx(xfer->epctx, 0);
2010 }
2011 return 0;
2012 }
2013
2014 static void xhci_calc_intr_kick(XHCIState *xhci, XHCITransfer *xfer,
2015 XHCIEPContext *epctx, uint64_t mfindex)
2016 {
2017 uint64_t asap = ((mfindex + epctx->interval - 1) &
2018 ~(epctx->interval-1));
2019 uint64_t kick = epctx->mfindex_last + epctx->interval;
2020
2021 assert(epctx->interval != 0);
2022 xfer->mfindex_kick = MAX(asap, kick);
2023 }
2024
2025 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
2026 XHCIEPContext *epctx, uint64_t mfindex)
2027 {
2028 if (xfer->trbs[0].control & TRB_TR_SIA) {
2029 uint64_t asap = ((mfindex + epctx->interval - 1) &
2030 ~(epctx->interval-1));
2031 if (asap >= epctx->mfindex_last &&
2032 asap <= epctx->mfindex_last + epctx->interval * 4) {
2033 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval;
2034 } else {
2035 xfer->mfindex_kick = asap;
2036 }
2037 } else {
2038 xfer->mfindex_kick = ((xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT)
2039 & TRB_TR_FRAMEID_MASK) << 3;
2040 xfer->mfindex_kick |= mfindex & ~0x3fff;
2041 if (xfer->mfindex_kick + 0x100 < mfindex) {
2042 xfer->mfindex_kick += 0x4000;
2043 }
2044 }
2045 }
2046
2047 static void xhci_check_intr_iso_kick(XHCIState *xhci, XHCITransfer *xfer,
2048 XHCIEPContext *epctx, uint64_t mfindex)
2049 {
2050 if (xfer->mfindex_kick > mfindex) {
2051 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
2052 (xfer->mfindex_kick - mfindex) * 125000);
2053 xfer->running_retry = 1;
2054 } else {
2055 epctx->mfindex_last = xfer->mfindex_kick;
2056 timer_del(epctx->kick_timer);
2057 xfer->running_retry = 0;
2058 }
2059 }
2060
2061
2062 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
2063 {
2064 uint64_t mfindex;
2065
2066 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid);
2067
2068 xfer->in_xfer = epctx->type>>2;
2069
2070 switch(epctx->type) {
2071 case ET_INTR_OUT:
2072 case ET_INTR_IN:
2073 xfer->pkts = 0;
2074 xfer->iso_xfer = false;
2075 xfer->timed_xfer = true;
2076 mfindex = xhci_mfindex_get(xhci);
2077 xhci_calc_intr_kick(xhci, xfer, epctx, mfindex);
2078 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
2079 if (xfer->running_retry) {
2080 return -1;
2081 }
2082 break;
2083 case ET_BULK_OUT:
2084 case ET_BULK_IN:
2085 xfer->pkts = 0;
2086 xfer->iso_xfer = false;
2087 xfer->timed_xfer = false;
2088 break;
2089 case ET_ISO_OUT:
2090 case ET_ISO_IN:
2091 xfer->pkts = 1;
2092 xfer->iso_xfer = true;
2093 xfer->timed_xfer = true;
2094 mfindex = xhci_mfindex_get(xhci);
2095 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex);
2096 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
2097 if (xfer->running_retry) {
2098 return -1;
2099 }
2100 break;
2101 default:
2102 trace_usb_xhci_unimplemented("endpoint type", epctx->type);
2103 return -1;
2104 }
2105
2106 if (xhci_setup_packet(xfer) < 0) {
2107 return -1;
2108 }
2109 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
2110
2111 xhci_complete_packet(xfer);
2112 if (!xfer->running_async && !xfer->running_retry) {
2113 xhci_kick_epctx(xfer->epctx, xfer->streamid);
2114 }
2115 return 0;
2116 }
2117
2118 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx)
2119 {
2120 trace_usb_xhci_xfer_start(xfer, xfer->epctx->slotid,
2121 xfer->epctx->epid, xfer->streamid);
2122 return xhci_submit(xhci, xfer, epctx);
2123 }
2124
2125 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid,
2126 unsigned int epid, unsigned int streamid)
2127 {
2128 XHCIEPContext *epctx;
2129
2130 assert(slotid >= 1 && slotid <= xhci->numslots);
2131 assert(epid >= 1 && epid <= 31);
2132
2133 if (!xhci->slots[slotid-1].enabled) {
2134 DPRINTF("xhci: xhci_kick_ep for disabled slot %d\n", slotid);
2135 return;
2136 }
2137 epctx = xhci->slots[slotid-1].eps[epid-1];
2138 if (!epctx) {
2139 DPRINTF("xhci: xhci_kick_ep for disabled endpoint %d,%d\n",
2140 epid, slotid);
2141 return;
2142 }
2143
2144 xhci_kick_epctx(epctx, streamid);
2145 }
2146
2147 static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid)
2148 {
2149 XHCIState *xhci = epctx->xhci;
2150 XHCIStreamContext *stctx;
2151 XHCITransfer *xfer;
2152 XHCIRing *ring;
2153 USBEndpoint *ep = NULL;
2154 uint64_t mfindex;
2155 int length;
2156 int i;
2157
2158 trace_usb_xhci_ep_kick(epctx->slotid, epctx->epid, streamid);
2159
2160 /* If the device has been detached, but the guest has not noticed this
2161 yet the 2 above checks will succeed, but we must NOT continue */
2162 if (!xhci->slots[epctx->slotid - 1].uport ||
2163 !xhci->slots[epctx->slotid - 1].uport->dev ||
2164 !xhci->slots[epctx->slotid - 1].uport->dev->attached) {
2165 return;
2166 }
2167
2168 if (epctx->retry) {
2169 XHCITransfer *xfer = epctx->retry;
2170
2171 trace_usb_xhci_xfer_retry(xfer);
2172 assert(xfer->running_retry);
2173 if (xfer->timed_xfer) {
2174 /* time to kick the transfer? */
2175 mfindex = xhci_mfindex_get(xhci);
2176 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex);
2177 if (xfer->running_retry) {
2178 return;
2179 }
2180 xfer->timed_xfer = 0;
2181 xfer->running_retry = 1;
2182 }
2183 if (xfer->iso_xfer) {
2184 /* retry iso transfer */
2185 if (xhci_setup_packet(xfer) < 0) {
2186 return;
2187 }
2188 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
2189 assert(xfer->packet.status != USB_RET_NAK);
2190 xhci_complete_packet(xfer);
2191 } else {
2192 /* retry nak'ed transfer */
2193 if (xhci_setup_packet(xfer) < 0) {
2194 return;
2195 }
2196 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet);
2197 if (xfer->packet.status == USB_RET_NAK) {
2198 return;
2199 }
2200 xhci_complete_packet(xfer);
2201 }
2202 assert(!xfer->running_retry);
2203 xhci_ep_free_xfer(epctx->retry);
2204 epctx->retry = NULL;
2205 }
2206
2207 if (epctx->state == EP_HALTED) {
2208 DPRINTF("xhci: ep halted, not running schedule\n");
2209 return;
2210 }
2211
2212
2213 if (epctx->nr_pstreams) {
2214 uint32_t err;
2215 stctx = xhci_find_stream(epctx, streamid, &err);
2216 if (stctx == NULL) {
2217 return;
2218 }
2219 ring = &stctx->ring;
2220 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING);
2221 } else {
2222 ring = &epctx->ring;
2223 streamid = 0;
2224 xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING);
2225 }
2226 assert(ring->dequeue != 0);
2227
2228 while (1) {
2229 length = xhci_ring_chain_length(xhci, ring);
2230 if (length <= 0) {
2231 break;
2232 }
2233 xfer = xhci_ep_alloc_xfer(epctx, length);
2234 if (xfer == NULL) {
2235 break;
2236 }
2237
2238 for (i = 0; i < length; i++) {
2239 TRBType type;
2240 type = xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL);
2241 assert(type);
2242 }
2243 xfer->streamid = streamid;
2244
2245 if (epctx->epid == 1) {
2246 xhci_fire_ctl_transfer(xhci, xfer);
2247 } else {
2248 xhci_fire_transfer(xhci, xfer, epctx);
2249 }
2250 if (xfer->complete) {
2251 xhci_ep_free_xfer(xfer);
2252 xfer = NULL;
2253 }
2254
2255 if (epctx->state == EP_HALTED) {
2256 break;
2257 }
2258 if (xfer != NULL && xfer->running_retry) {
2259 DPRINTF("xhci: xfer nacked, stopping schedule\n");
2260 epctx->retry = xfer;
2261 break;
2262 }
2263 }
2264
2265 ep = xhci_epid_to_usbep(xhci, epctx->slotid, epctx->epid);
2266 if (ep) {
2267 usb_device_flush_ep_queue(ep->dev, ep);
2268 }
2269 }
2270
2271 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid)
2272 {
2273 trace_usb_xhci_slot_enable(slotid);
2274 assert(slotid >= 1 && slotid <= xhci->numslots);
2275 xhci->slots[slotid-1].enabled = 1;
2276 xhci->slots[slotid-1].uport = NULL;
2277 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31);
2278
2279 return CC_SUCCESS;
2280 }
2281
2282 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid)
2283 {
2284 int i;
2285
2286 trace_usb_xhci_slot_disable(slotid);
2287 assert(slotid >= 1 && slotid <= xhci->numslots);
2288
2289 for (i = 1; i <= 31; i++) {
2290 if (xhci->slots[slotid-1].eps[i-1]) {
2291 xhci_disable_ep(xhci, slotid, i);
2292 }
2293 }
2294
2295 xhci->slots[slotid-1].enabled = 0;
2296 xhci->slots[slotid-1].addressed = 0;
2297 xhci->slots[slotid-1].uport = NULL;
2298 return CC_SUCCESS;
2299 }
2300
2301 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx)
2302 {
2303 USBPort *uport;
2304 char path[32];
2305 int i, pos, port;
2306
2307 port = (slot_ctx[1]>>16) & 0xFF;
2308 if (port < 1 || port > xhci->numports) {
2309 return NULL;
2310 }
2311 port = xhci->ports[port-1].uport->index+1;
2312 pos = snprintf(path, sizeof(path), "%d", port);
2313 for (i = 0; i < 5; i++) {
2314 port = (slot_ctx[0] >> 4*i) & 0x0f;
2315 if (!port) {
2316 break;
2317 }
2318 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port);
2319 }
2320
2321 QTAILQ_FOREACH(uport, &xhci->bus.used, next) {
2322 if (strcmp(uport->path, path) == 0) {
2323 return uport;
2324 }
2325 }
2326 return NULL;
2327 }
2328
2329 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid,
2330 uint64_t pictx, bool bsr)
2331 {
2332 XHCISlot *slot;
2333 USBPort *uport;
2334 USBDevice *dev;
2335 dma_addr_t ictx, octx, dcbaap;
2336 uint64_t poctx;
2337 uint32_t ictl_ctx[2];
2338 uint32_t slot_ctx[4];
2339 uint32_t ep0_ctx[5];
2340 int i;
2341 TRBCCode res;
2342
2343 assert(slotid >= 1 && slotid <= xhci->numslots);
2344
2345 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
2346 poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid);
2347 ictx = xhci_mask64(pictx);
2348 octx = xhci_mask64(poctx);
2349
2350 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2351 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2352
2353 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2354
2355 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) {
2356 DPRINTF("xhci: invalid input context control %08x %08x\n",
2357 ictl_ctx[0], ictl_ctx[1]);
2358 return CC_TRB_ERROR;
2359 }
2360
2361 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx));
2362 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx));
2363
2364 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2365 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2366
2367 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2368 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2369
2370 uport = xhci_lookup_uport(xhci, slot_ctx);
2371 if (uport == NULL) {
2372 DPRINTF("xhci: port not found\n");
2373 return CC_TRB_ERROR;
2374 }
2375 trace_usb_xhci_slot_address(slotid, uport->path);
2376
2377 dev = uport->dev;
2378 if (!dev || !dev->attached) {
2379 DPRINTF("xhci: port %s not connected\n", uport->path);
2380 return CC_USB_TRANSACTION_ERROR;
2381 }
2382
2383 for (i = 0; i < xhci->numslots; i++) {
2384 if (i == slotid-1) {
2385 continue;
2386 }
2387 if (xhci->slots[i].uport == uport) {
2388 DPRINTF("xhci: port %s already assigned to slot %d\n",
2389 uport->path, i+1);
2390 return CC_TRB_ERROR;
2391 }
2392 }
2393
2394 slot = &xhci->slots[slotid-1];
2395 slot->uport = uport;
2396 slot->ctx = octx;
2397
2398 /* Make sure device is in USB_STATE_DEFAULT state */
2399 usb_device_reset(dev);
2400 if (bsr) {
2401 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT;
2402 } else {
2403 USBPacket p;
2404 uint8_t buf[1];
2405
2406 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid;
2407 memset(&p, 0, sizeof(p));
2408 usb_packet_addbuf(&p, buf, sizeof(buf));
2409 usb_packet_setup(&p, USB_TOKEN_OUT,
2410 usb_ep_get(dev, USB_TOKEN_OUT, 0), 0,
2411 0, false, false);
2412 usb_device_handle_control(dev, &p,
2413 DeviceOutRequest | USB_REQ_SET_ADDRESS,
2414 slotid, 0, 0, NULL);
2415 assert(p.status != USB_RET_ASYNC);
2416 }
2417
2418 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx);
2419
2420 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2421 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2422 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2423 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2424
2425 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2426 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2427
2428 xhci->slots[slotid-1].addressed = 1;
2429 return res;
2430 }
2431
2432
2433 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid,
2434 uint64_t pictx, bool dc)
2435 {
2436 dma_addr_t ictx, octx;
2437 uint32_t ictl_ctx[2];
2438 uint32_t slot_ctx[4];
2439 uint32_t islot_ctx[4];
2440 uint32_t ep_ctx[5];
2441 int i;
2442 TRBCCode res;
2443
2444 trace_usb_xhci_slot_configure(slotid);
2445 assert(slotid >= 1 && slotid <= xhci->numslots);
2446
2447 ictx = xhci_mask64(pictx);
2448 octx = xhci->slots[slotid-1].ctx;
2449
2450 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2451 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2452
2453 if (dc) {
2454 for (i = 2; i <= 31; i++) {
2455 if (xhci->slots[slotid-1].eps[i-1]) {
2456 xhci_disable_ep(xhci, slotid, i);
2457 }
2458 }
2459
2460 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2461 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2462 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT;
2463 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2464 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2465 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2466
2467 return CC_SUCCESS;
2468 }
2469
2470 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2471
2472 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) {
2473 DPRINTF("xhci: invalid input context control %08x %08x\n",
2474 ictl_ctx[0], ictl_ctx[1]);
2475 return CC_TRB_ERROR;
2476 }
2477
2478 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2479 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2480
2481 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) {
2482 DPRINTF("xhci: invalid slot state %08x\n", slot_ctx[3]);
2483 return CC_CONTEXT_STATE_ERROR;
2484 }
2485
2486 xhci_free_device_streams(xhci, slotid, ictl_ctx[0] | ictl_ctx[1]);
2487
2488 for (i = 2; i <= 31; i++) {
2489 if (ictl_ctx[0] & (1<<i)) {
2490 xhci_disable_ep(xhci, slotid, i);
2491 }
2492 if (ictl_ctx[1] & (1<<i)) {
2493 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx));
2494 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n",
2495 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2496 ep_ctx[3], ep_ctx[4]);
2497 xhci_disable_ep(xhci, slotid, i);
2498 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx);
2499 if (res != CC_SUCCESS) {
2500 return res;
2501 }
2502 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n",
2503 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2],
2504 ep_ctx[3], ep_ctx[4]);
2505 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx));
2506 }
2507 }
2508
2509 res = xhci_alloc_device_streams(xhci, slotid, ictl_ctx[1]);
2510 if (res != CC_SUCCESS) {
2511 for (i = 2; i <= 31; i++) {
2512 if (ictl_ctx[1] & (1u << i)) {
2513 xhci_disable_ep(xhci, slotid, i);
2514 }
2515 }
2516 return res;
2517 }
2518
2519 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2520 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT;
2521 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT);
2522 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK <<
2523 SLOT_CONTEXT_ENTRIES_SHIFT);
2524 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2525 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2526
2527 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2528
2529 return CC_SUCCESS;
2530 }
2531
2532
2533 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid,
2534 uint64_t pictx)
2535 {
2536 dma_addr_t ictx, octx;
2537 uint32_t ictl_ctx[2];
2538 uint32_t iep0_ctx[5];
2539 uint32_t ep0_ctx[5];
2540 uint32_t islot_ctx[4];
2541 uint32_t slot_ctx[4];
2542
2543 trace_usb_xhci_slot_evaluate(slotid);
2544 assert(slotid >= 1 && slotid <= xhci->numslots);
2545
2546 ictx = xhci_mask64(pictx);
2547 octx = xhci->slots[slotid-1].ctx;
2548
2549 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx);
2550 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2551
2552 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx));
2553
2554 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) {
2555 DPRINTF("xhci: invalid input context control %08x %08x\n",
2556 ictl_ctx[0], ictl_ctx[1]);
2557 return CC_TRB_ERROR;
2558 }
2559
2560 if (ictl_ctx[1] & 0x1) {
2561 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx));
2562
2563 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n",
2564 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]);
2565
2566 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2567
2568 slot_ctx[1] &= ~0xFFFF; /* max exit latency */
2569 slot_ctx[1] |= islot_ctx[1] & 0xFFFF;
2570 slot_ctx[2] &= ~0xFF00000; /* interrupter target */
2571 slot_ctx[2] |= islot_ctx[2] & 0xFF000000;
2572
2573 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2574 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2575
2576 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2577 }
2578
2579 if (ictl_ctx[1] & 0x2) {
2580 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx));
2581
2582 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n",
2583 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2],
2584 iep0_ctx[3], iep0_ctx[4]);
2585
2586 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2587
2588 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/
2589 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000;
2590
2591 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n",
2592 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]);
2593
2594 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx));
2595 }
2596
2597 return CC_SUCCESS;
2598 }
2599
2600 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid)
2601 {
2602 uint32_t slot_ctx[4];
2603 dma_addr_t octx;
2604 int i;
2605
2606 trace_usb_xhci_slot_reset(slotid);
2607 assert(slotid >= 1 && slotid <= xhci->numslots);
2608
2609 octx = xhci->slots[slotid-1].ctx;
2610
2611 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx);
2612
2613 for (i = 2; i <= 31; i++) {
2614 if (xhci->slots[slotid-1].eps[i-1]) {
2615 xhci_disable_ep(xhci, slotid, i);
2616 }
2617 }
2618
2619 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2620 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT);
2621 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT;
2622 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n",
2623 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]);
2624 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx));
2625
2626 return CC_SUCCESS;
2627 }
2628
2629 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb)
2630 {
2631 unsigned int slotid;
2632 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK;
2633 if (slotid < 1 || slotid > xhci->numslots) {
2634 DPRINTF("xhci: bad slot id %d\n", slotid);
2635 event->ccode = CC_TRB_ERROR;
2636 return 0;
2637 } else if (!xhci->slots[slotid-1].enabled) {
2638 DPRINTF("xhci: slot id %d not enabled\n", slotid);
2639 event->ccode = CC_SLOT_NOT_ENABLED_ERROR;
2640 return 0;
2641 }
2642 return slotid;
2643 }
2644
2645 /* cleanup slot state on usb device detach */
2646 static void xhci_detach_slot(XHCIState *xhci, USBPort *uport)
2647 {
2648 int slot, ep;
2649
2650 for (slot = 0; slot < xhci->numslots; slot++) {
2651 if (xhci->slots[slot].uport == uport) {
2652 break;
2653 }
2654 }
2655 if (slot == xhci->numslots) {
2656 return;
2657 }
2658
2659 for (ep = 0; ep < 31; ep++) {
2660 if (xhci->slots[slot].eps[ep]) {
2661 xhci_ep_nuke_xfers(xhci, slot + 1, ep + 1, 0);
2662 }
2663 }
2664 xhci->slots[slot].uport = NULL;
2665 }
2666
2667 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx)
2668 {
2669 dma_addr_t ctx;
2670 uint8_t bw_ctx[xhci->numports+1];
2671
2672 DPRINTF("xhci_get_port_bandwidth()\n");
2673
2674 ctx = xhci_mask64(pctx);
2675
2676 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx);
2677
2678 /* TODO: actually implement real values here */
2679 bw_ctx[0] = 0;
2680 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */
2681 pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx));
2682
2683 return CC_SUCCESS;
2684 }
2685
2686 static uint32_t rotl(uint32_t v, unsigned count)
2687 {
2688 count &= 31;
2689 return (v << count) | (v >> (32 - count));
2690 }
2691
2692
2693 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo)
2694 {
2695 uint32_t val;
2696 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F));
2697 val += rotl(lo + 0x49434878, hi & 0x1F);
2698 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F);
2699 return ~val;
2700 }
2701
2702 static void xhci_via_challenge(XHCIState *xhci, uint64_t addr)
2703 {
2704 PCIDevice *pci_dev = PCI_DEVICE(xhci);
2705 uint32_t buf[8];
2706 uint32_t obuf[8];
2707 dma_addr_t paddr = xhci_mask64(addr);
2708
2709 pci_dma_read(pci_dev, paddr, &buf, 32);
2710
2711 memcpy(obuf, buf, sizeof(obuf));
2712
2713 if ((buf[0] & 0xff) == 2) {
2714 obuf[0] = 0x49932000 + 0x54dc200 * buf[2] + 0x7429b578 * buf[3];
2715 obuf[0] |= (buf[2] * buf[3]) & 0xff;
2716 obuf[1] = 0x0132bb37 + 0xe89 * buf[2] + 0xf09 * buf[3];
2717 obuf[2] = 0x0066c2e9 + 0x2091 * buf[2] + 0x19bd * buf[3];
2718 obuf[3] = 0xd5281342 + 0x2cc9691 * buf[2] + 0x2367662 * buf[3];
2719 obuf[4] = 0x0123c75c + 0x1595 * buf[2] + 0x19ec * buf[3];
2720 obuf[5] = 0x00f695de + 0x26fd * buf[2] + 0x3e9 * buf[3];
2721 obuf[6] = obuf[2] ^ obuf[3] ^ 0x29472956;
2722 obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593;
2723 }
2724
2725 pci_dma_write(pci_dev, paddr, &obuf, 32);
2726 }
2727
2728 static void xhci_process_commands(XHCIState *xhci)
2729 {
2730 XHCITRB trb;
2731 TRBType type;
2732 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS};
2733 dma_addr_t addr;
2734 unsigned int i, slotid = 0;
2735
2736 DPRINTF("xhci_process_commands()\n");
2737 if (!xhci_running(xhci)) {
2738 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n");
2739 return;
2740 }
2741
2742 xhci->crcr_low |= CRCR_CRR;
2743
2744 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) {
2745 event.ptr = addr;
2746 switch (type) {
2747 case CR_ENABLE_SLOT:
2748 for (i = 0; i < xhci->numslots; i++) {
2749 if (!xhci->slots[i].enabled) {
2750 break;
2751 }
2752 }
2753 if (i >= xhci->numslots) {
2754 DPRINTF("xhci: no device slots available\n");
2755 event.ccode = CC_NO_SLOTS_ERROR;
2756 } else {
2757 slotid = i+1;
2758 event.ccode = xhci_enable_slot(xhci, slotid);
2759 }
2760 break;
2761 case CR_DISABLE_SLOT:
2762 slotid = xhci_get_slot(xhci, &event, &trb);
2763 if (slotid) {
2764 event.ccode = xhci_disable_slot(xhci, slotid);
2765 }
2766 break;
2767 case CR_ADDRESS_DEVICE:
2768 slotid = xhci_get_slot(xhci, &event, &trb);
2769 if (slotid) {
2770 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter,
2771 trb.control & TRB_CR_BSR);
2772 }
2773 break;
2774 case CR_CONFIGURE_ENDPOINT:
2775 slotid = xhci_get_slot(xhci, &event, &trb);
2776 if (slotid) {
2777 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter,
2778 trb.control & TRB_CR_DC);
2779 }
2780 break;
2781 case CR_EVALUATE_CONTEXT:
2782 slotid = xhci_get_slot(xhci, &event, &trb);
2783 if (slotid) {
2784 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter);
2785 }
2786 break;
2787 case CR_STOP_ENDPOINT:
2788 slotid = xhci_get_slot(xhci, &event, &trb);
2789 if (slotid) {
2790 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2791 & TRB_CR_EPID_MASK;
2792 event.ccode = xhci_stop_ep(xhci, slotid, epid);
2793 }
2794 break;
2795 case CR_RESET_ENDPOINT:
2796 slotid = xhci_get_slot(xhci, &event, &trb);
2797 if (slotid) {
2798 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2799 & TRB_CR_EPID_MASK;
2800 event.ccode = xhci_reset_ep(xhci, slotid, epid);
2801 }
2802 break;
2803 case CR_SET_TR_DEQUEUE:
2804 slotid = xhci_get_slot(xhci, &event, &trb);
2805 if (slotid) {
2806 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT)
2807 & TRB_CR_EPID_MASK;
2808 unsigned int streamid = (trb.status >> 16) & 0xffff;
2809 event.ccode = xhci_set_ep_dequeue(xhci, slotid,
2810 epid, streamid,
2811 trb.parameter);
2812 }
2813 break;
2814 case CR_RESET_DEVICE:
2815 slotid = xhci_get_slot(xhci, &event, &trb);
2816 if (slotid) {
2817 event.ccode = xhci_reset_slot(xhci, slotid);
2818 }
2819 break;
2820 case CR_GET_PORT_BANDWIDTH:
2821 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter);
2822 break;
2823 case CR_VENDOR_VIA_CHALLENGE_RESPONSE:
2824 xhci_via_challenge(xhci, trb.parameter);
2825 break;
2826 case CR_VENDOR_NEC_FIRMWARE_REVISION:
2827 event.type = 48; /* NEC reply */
2828 event.length = 0x3025;
2829 break;
2830 case CR_VENDOR_NEC_CHALLENGE_RESPONSE:
2831 {
2832 uint32_t chi = trb.parameter >> 32;
2833 uint32_t clo = trb.parameter;
2834 uint32_t val = xhci_nec_challenge(chi, clo);
2835 event.length = val & 0xFFFF;
2836 event.epid = val >> 16;
2837 slotid = val >> 24;
2838 event.type = 48; /* NEC reply */
2839 }
2840 break;
2841 default:
2842 trace_usb_xhci_unimplemented("command", type);
2843 event.ccode = CC_TRB_ERROR;
2844 break;
2845 }
2846 event.slotid = slotid;
2847 xhci_event(xhci, &event, 0);
2848 }
2849 }
2850
2851 static bool xhci_port_have_device(XHCIPort *port)
2852 {
2853 if (!port->uport->dev || !port->uport->dev->attached) {
2854 return false; /* no device present */
2855 }
2856 if (!((1 << port->uport->dev->speed) & port->speedmask)) {
2857 return false; /* speed mismatch */
2858 }
2859 return true;
2860 }
2861
2862 static void xhci_port_notify(XHCIPort *port, uint32_t bits)
2863 {
2864 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS,
2865 port->portnr << 24 };
2866
2867 if ((port->portsc & bits) == bits) {
2868 return;
2869 }
2870 trace_usb_xhci_port_notify(port->portnr, bits);
2871 port->portsc |= bits;
2872 if (!xhci_running(port->xhci)) {
2873 return;
2874 }
2875 xhci_event(port->xhci, &ev, 0);
2876 }
2877
2878 static void xhci_port_update(XHCIPort *port, int is_detach)
2879 {
2880 uint32_t pls = PLS_RX_DETECT;
2881
2882 port->portsc = PORTSC_PP;
2883 if (!is_detach && xhci_port_have_device(port)) {
2884 port->portsc |= PORTSC_CCS;
2885 switch (port->uport->dev->speed) {
2886 case USB_SPEED_LOW:
2887 port->portsc |= PORTSC_SPEED_LOW;
2888 pls = PLS_POLLING;
2889 break;
2890 case USB_SPEED_FULL:
2891 port->portsc |= PORTSC_SPEED_FULL;
2892 pls = PLS_POLLING;
2893 break;
2894 case USB_SPEED_HIGH:
2895 port->portsc |= PORTSC_SPEED_HIGH;
2896 pls = PLS_POLLING;
2897 break;
2898 case USB_SPEED_SUPER:
2899 port->portsc |= PORTSC_SPEED_SUPER;
2900 port->portsc |= PORTSC_PED;
2901 pls = PLS_U0;
2902 break;
2903 }
2904 }
2905 set_field(&port->portsc, pls, PORTSC_PLS);
2906 trace_usb_xhci_port_link(port->portnr, pls);
2907 xhci_port_notify(port, PORTSC_CSC);
2908 }
2909
2910 static void xhci_port_reset(XHCIPort *port, bool warm_reset)
2911 {
2912 trace_usb_xhci_port_reset(port->portnr, warm_reset);
2913
2914 if (!xhci_port_have_device(port)) {
2915 return;
2916 }
2917
2918 usb_device_reset(port->uport->dev);
2919
2920 switch (port->uport->dev->speed) {
2921 case USB_SPEED_SUPER:
2922 if (warm_reset) {
2923 port->portsc |= PORTSC_WRC;
2924 }
2925 /* fall through */
2926 case USB_SPEED_LOW:
2927 case USB_SPEED_FULL:
2928 case USB_SPEED_HIGH:
2929 set_field(&port->portsc, PLS_U0, PORTSC_PLS);
2930 trace_usb_xhci_port_link(port->portnr, PLS_U0);
2931 port->portsc |= PORTSC_PED;
2932 break;
2933 }
2934
2935 port->portsc &= ~PORTSC_PR;
2936 xhci_port_notify(port, PORTSC_PRC);
2937 }
2938
2939 static void xhci_reset(DeviceState *dev)
2940 {
2941 XHCIState *xhci = XHCI(dev);
2942 int i;
2943
2944 trace_usb_xhci_reset();
2945 if (!(xhci->usbsts & USBSTS_HCH)) {
2946 DPRINTF("xhci: reset while running!\n");
2947 }
2948
2949 xhci->usbcmd = 0;
2950 xhci->usbsts = USBSTS_HCH;
2951 xhci->dnctrl = 0;
2952 xhci->crcr_low = 0;
2953 xhci->crcr_high = 0;
2954 xhci->dcbaap_low = 0;
2955 xhci->dcbaap_high = 0;
2956 xhci->config = 0;
2957
2958 for (i = 0; i < xhci->numslots; i++) {
2959 xhci_disable_slot(xhci, i+1);
2960 }
2961
2962 for (i = 0; i < xhci->numports; i++) {
2963 xhci_port_update(xhci->ports + i, 0);
2964 }
2965
2966 for (i = 0; i < xhci->numintrs; i++) {
2967 xhci->intr[i].iman = 0;
2968 xhci->intr[i].imod = 0;
2969 xhci->intr[i].erstsz = 0;
2970 xhci->intr[i].erstba_low = 0;
2971 xhci->intr[i].erstba_high = 0;
2972 xhci->intr[i].erdp_low = 0;
2973 xhci->intr[i].erdp_high = 0;
2974 xhci->intr[i].msix_used = 0;
2975
2976 xhci->intr[i].er_ep_idx = 0;
2977 xhci->intr[i].er_pcs = 1;
2978 xhci->intr[i].er_full = 0;
2979 xhci->intr[i].ev_buffer_put = 0;
2980 xhci->intr[i].ev_buffer_get = 0;
2981 }
2982
2983 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
2984 xhci_mfwrap_update(xhci);
2985 }
2986
2987 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size)
2988 {
2989 XHCIState *xhci = ptr;
2990 uint32_t ret;
2991
2992 switch (reg) {
2993 case 0x00: /* HCIVERSION, CAPLENGTH */
2994 ret = 0x01000000 | LEN_CAP;
2995 break;
2996 case 0x04: /* HCSPARAMS 1 */
2997 ret = ((xhci->numports_2+xhci->numports_3)<<24)
2998 | (xhci->numintrs<<8) | xhci->numslots;
2999 break;
3000 case 0x08: /* HCSPARAMS 2 */
3001 ret = 0x0000000f;
3002 break;
3003 case 0x0c: /* HCSPARAMS 3 */
3004 ret = 0x00000000;
3005 break;
3006 case 0x10: /* HCCPARAMS */
3007 if (sizeof(dma_addr_t) == 4) {
3008 ret = 0x00080000 | (xhci->max_pstreams_mask << 12);
3009 } else {
3010 ret = 0x00080001 | (xhci->max_pstreams_mask << 12);
3011 }
3012 break;
3013 case 0x14: /* DBOFF */
3014 ret = OFF_DOORBELL;
3015 break;
3016 case 0x18: /* RTSOFF */
3017 ret = OFF_RUNTIME;
3018 break;
3019
3020 /* extended capabilities */
3021 case 0x20: /* Supported Protocol:00 */
3022 ret = 0x02000402; /* USB 2.0 */
3023 break;
3024 case 0x24: /* Supported Protocol:04 */
3025 ret = 0x20425355; /* "USB " */
3026 break;
3027 case 0x28: /* Supported Protocol:08 */
3028 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
3029 ret = (xhci->numports_2<<8) | (xhci->numports_3+1);
3030 } else {
3031 ret = (xhci->numports_2<<8) | 1;
3032 }
3033 break;
3034 case 0x2c: /* Supported Protocol:0c */
3035 ret = 0x00000000; /* reserved */
3036 break;
3037 case 0x30: /* Supported Protocol:00 */
3038 ret = 0x03000002; /* USB 3.0 */
3039 break;
3040 case 0x34: /* Supported Protocol:04 */
3041 ret = 0x20425355; /* "USB " */
3042 break;
3043 case 0x38: /* Supported Protocol:08 */
3044 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
3045 ret = (xhci->numports_3<<8) | 1;
3046 } else {
3047 ret = (xhci->numports_3<<8) | (xhci->numports_2+1);
3048 }
3049 break;
3050 case 0x3c: /* Supported Protocol:0c */
3051 ret = 0x00000000; /* reserved */
3052 break;
3053 default:
3054 trace_usb_xhci_unimplemented("cap read", reg);
3055 ret = 0;
3056 }
3057
3058 trace_usb_xhci_cap_read(reg, ret);
3059 return ret;
3060 }
3061
3062 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size)
3063 {
3064 XHCIPort *port = ptr;
3065 uint32_t ret;
3066
3067 switch (reg) {
3068 case 0x00: /* PORTSC */
3069 ret = port->portsc;
3070 break;
3071 case 0x04: /* PORTPMSC */
3072 case 0x08: /* PORTLI */
3073 ret = 0;
3074 break;
3075 case 0x0c: /* reserved */
3076 default:
3077 trace_usb_xhci_unimplemented("port read", reg);
3078 ret = 0;
3079 }
3080
3081 trace_usb_xhci_port_read(port->portnr, reg, ret);
3082 return ret;
3083 }
3084
3085 static void xhci_port_write(void *ptr, hwaddr reg,
3086 uint64_t val, unsigned size)
3087 {
3088 XHCIPort *port = ptr;
3089 uint32_t portsc, notify;
3090
3091 trace_usb_xhci_port_write(port->portnr, reg, val);
3092
3093 switch (reg) {
3094 case 0x00: /* PORTSC */
3095 /* write-1-to-start bits */
3096 if (val & PORTSC_WPR) {
3097 xhci_port_reset(port, true);
3098 break;
3099 }
3100 if (val & PORTSC_PR) {
3101 xhci_port_reset(port, false);
3102 break;
3103 }
3104
3105 portsc = port->portsc;
3106 notify = 0;
3107 /* write-1-to-clear bits*/
3108 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC|
3109 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC));
3110 if (val & PORTSC_LWS) {
3111 /* overwrite PLS only when LWS=1 */
3112 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS);
3113 uint32_t new_pls = get_field(val, PORTSC_PLS);
3114 switch (new_pls) {
3115 case PLS_U0:
3116 if (old_pls != PLS_U0) {
3117 set_field(&portsc, new_pls, PORTSC_PLS);
3118 trace_usb_xhci_port_link(port->portnr, new_pls);
3119 notify = PORTSC_PLC;
3120 }
3121 break;
3122 case PLS_U3:
3123 if (old_pls < PLS_U3) {
3124 set_field(&portsc, new_pls, PORTSC_PLS);
3125 trace_usb_xhci_port_link(port->portnr, new_pls);
3126 }
3127 break;
3128 case PLS_RESUME:
3129 /* windows does this for some reason, don't spam stderr */
3130 break;
3131 default:
3132 DPRINTF("%s: ignore pls write (old %d, new %d)\n",
3133 __func__, old_pls, new_pls);
3134 break;
3135 }
3136 }
3137 /* read/write bits */
3138 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE);
3139 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE));
3140 port->portsc = portsc;
3141 if (notify) {
3142 xhci_port_notify(port, notify);
3143 }
3144 break;
3145 case 0x04: /* PORTPMSC */
3146 case 0x08: /* PORTLI */
3147 default:
3148 trace_usb_xhci_unimplemented("port write", reg);
3149 }
3150 }
3151
3152 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size)
3153 {
3154 XHCIState *xhci = ptr;
3155 uint32_t ret;
3156
3157 switch (reg) {
3158 case 0x00: /* USBCMD */
3159 ret = xhci->usbcmd;
3160 break;
3161 case 0x04: /* USBSTS */
3162 ret = xhci->usbsts;
3163 break;
3164 case 0x08: /* PAGESIZE */
3165 ret = 1; /* 4KiB */
3166 break;
3167 case 0x14: /* DNCTRL */
3168 ret = xhci->dnctrl;
3169 break;
3170 case 0x18: /* CRCR low */
3171 ret = xhci->crcr_low & ~0xe;
3172 break;
3173 case 0x1c: /* CRCR high */
3174 ret = xhci->crcr_high;
3175 break;
3176 case 0x30: /* DCBAAP low */
3177 ret = xhci->dcbaap_low;
3178 break;
3179 case 0x34: /* DCBAAP high */
3180 ret = xhci->dcbaap_high;
3181 break;
3182 case 0x38: /* CONFIG */
3183 ret = xhci->config;
3184 break;
3185 default:
3186 trace_usb_xhci_unimplemented("oper read", reg);
3187 ret = 0;
3188 }
3189
3190 trace_usb_xhci_oper_read(reg, ret);
3191 return ret;
3192 }
3193
3194 static void xhci_oper_write(void *ptr, hwaddr reg,
3195 uint64_t val, unsigned size)
3196 {
3197 XHCIState *xhci = ptr;
3198 DeviceState *d = DEVICE(ptr);
3199
3200 trace_usb_xhci_oper_write(reg, val);
3201
3202 switch (reg) {
3203 case 0x00: /* USBCMD */
3204 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) {
3205 xhci_run(xhci);
3206 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) {
3207 xhci_stop(xhci);
3208 }
3209 if (val & USBCMD_CSS) {
3210 /* save state */
3211 xhci->usbsts &= ~USBSTS_SRE;
3212 }
3213 if (val & USBCMD_CRS) {
3214 /* restore state */
3215 xhci->usbsts |= USBSTS_SRE;
3216 }
3217 xhci->usbcmd = val & 0xc0f;
3218 xhci_mfwrap_update(xhci);
3219 if (val & USBCMD_HCRST) {
3220 xhci_reset(d);
3221 }
3222 xhci_intx_update(xhci);
3223 break;
3224
3225 case 0x04: /* USBSTS */
3226 /* these bits are write-1-to-clear */
3227 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE));
3228 xhci_intx_update(xhci);
3229 break;
3230
3231 case 0x14: /* DNCTRL */
3232 xhci->dnctrl = val & 0xffff;
3233 break;
3234 case 0x18: /* CRCR low */
3235 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR);
3236 break;
3237 case 0x1c: /* CRCR high */
3238 xhci->crcr_high = val;
3239 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) {
3240 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED};
3241 xhci->crcr_low &= ~CRCR_CRR;
3242 xhci_event(xhci, &event, 0);
3243 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low);
3244 } else {
3245 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val);
3246 xhci_ring_init(xhci, &xhci->cmd_ring, base);
3247 }
3248 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS);
3249 break;
3250 case 0x30: /* DCBAAP low */
3251 xhci->dcbaap_low = val & 0xffffffc0;
3252 break;
3253 case 0x34: /* DCBAAP high */
3254 xhci->dcbaap_high = val;
3255 break;
3256 case 0x38: /* CONFIG */
3257 xhci->config = val & 0xff;
3258 break;
3259 default:
3260 trace_usb_xhci_unimplemented("oper write", reg);
3261 }
3262 }
3263
3264 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg,
3265 unsigned size)
3266 {
3267 XHCIState *xhci = ptr;
3268 uint32_t ret = 0;
3269
3270 if (reg < 0x20) {
3271 switch (reg) {
3272 case 0x00: /* MFINDEX */
3273 ret = xhci_mfindex_get(xhci) & 0x3fff;
3274 break;
3275 default:
3276 trace_usb_xhci_unimplemented("runtime read", reg);
3277 break;
3278 }
3279 } else {
3280 int v = (reg - 0x20) / 0x20;
3281 XHCIInterrupter *intr = &xhci->intr[v];
3282 switch (reg & 0x1f) {
3283 case 0x00: /* IMAN */
3284 ret = intr->iman;
3285 break;
3286 case 0x04: /* IMOD */
3287 ret = intr->imod;
3288 break;
3289 case 0x08: /* ERSTSZ */
3290 ret = intr->erstsz;
3291 break;
3292 case 0x10: /* ERSTBA low */
3293 ret = intr->erstba_low;
3294 break;
3295 case 0x14: /* ERSTBA high */
3296 ret = intr->erstba_high;
3297 break;
3298 case 0x18: /* ERDP low */
3299 ret = intr->erdp_low;
3300 break;
3301 case 0x1c: /* ERDP high */
3302 ret = intr->erdp_high;
3303 break;
3304 }
3305 }
3306
3307 trace_usb_xhci_runtime_read(reg, ret);
3308 return ret;
3309 }
3310
3311 static void xhci_runtime_write(void *ptr, hwaddr reg,
3312 uint64_t val, unsigned size)
3313 {
3314 XHCIState *xhci = ptr;
3315 int v = (reg - 0x20) / 0x20;
3316 XHCIInterrupter *intr = &xhci->intr[v];
3317 trace_usb_xhci_runtime_write(reg, val);
3318
3319 if (reg < 0x20) {
3320 trace_usb_xhci_unimplemented("runtime write", reg);
3321 return;
3322 }
3323
3324 switch (reg & 0x1f) {
3325 case 0x00: /* IMAN */
3326 if (val & IMAN_IP) {
3327 intr->iman &= ~IMAN_IP;
3328 }
3329 intr->iman &= ~IMAN_IE;
3330 intr->iman |= val & IMAN_IE;
3331 if (v == 0) {
3332 xhci_intx_update(xhci);
3333 }
3334 xhci_msix_update(xhci, v);
3335 break;
3336 case 0x04: /* IMOD */
3337 intr->imod = val;
3338 break;
3339 case 0x08: /* ERSTSZ */
3340 intr->erstsz = val & 0xffff;
3341 break;
3342 case 0x10: /* ERSTBA low */
3343 /* XXX NEC driver bug: it doesn't align this to 64 bytes
3344 intr->erstba_low = val & 0xffffffc0; */
3345 intr->erstba_low = val & 0xfffffff0;
3346 break;
3347 case 0x14: /* ERSTBA high */
3348 intr->erstba_high = val;
3349 xhci_er_reset(xhci, v);
3350 break;
3351 case 0x18: /* ERDP low */
3352 if (val & ERDP_EHB) {
3353 intr->erdp_low &= ~ERDP_EHB;
3354 }
3355 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB);
3356 break;
3357 case 0x1c: /* ERDP high */
3358 intr->erdp_high = val;
3359 xhci_events_update(xhci, v);
3360 break;
3361 default:
3362 trace_usb_xhci_unimplemented("oper write", reg);
3363 }
3364 }
3365
3366 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg,
3367 unsigned size)
3368 {
3369 /* doorbells always read as 0 */
3370 trace_usb_xhci_doorbell_read(reg, 0);
3371 return 0;
3372 }
3373
3374 static void xhci_doorbell_write(void *ptr, hwaddr reg,
3375 uint64_t val, unsigned size)
3376 {
3377 XHCIState *xhci = ptr;
3378 unsigned int epid, streamid;
3379
3380 trace_usb_xhci_doorbell_write(reg, val);
3381
3382 if (!xhci_running(xhci)) {
3383 DPRINTF("xhci: wrote doorbell while xHC stopped or paused\n");
3384 return;
3385 }
3386
3387 reg >>= 2;
3388
3389 if (reg == 0) {
3390 if (val == 0) {
3391 xhci_process_commands(xhci);
3392 } else {
3393 DPRINTF("xhci: bad doorbell 0 write: 0x%x\n",
3394 (uint32_t)val);
3395 }
3396 } else {
3397 epid = val & 0xff;
3398 streamid = (val >> 16) & 0xffff;
3399 if (reg > xhci->numslots) {
3400 DPRINTF("xhci: bad doorbell %d\n", (int)reg);
3401 } else if (epid > 31) {
3402 DPRINTF("xhci: bad doorbell %d write: 0x%x\n",
3403 (int)reg, (uint32_t)val);
3404 } else {
3405 xhci_kick_ep(xhci, reg, epid, streamid);
3406 }
3407 }
3408 }
3409
3410 static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val,
3411 unsigned width)
3412 {
3413 /* nothing */
3414 }
3415
3416 static const MemoryRegionOps xhci_cap_ops = {
3417 .read = xhci_cap_read,
3418 .write = xhci_cap_write,
3419 .valid.min_access_size = 1,
3420 .valid.max_access_size = 4,
3421 .impl.min_access_size = 4,
3422 .impl.max_access_size = 4,
3423 .endianness = DEVICE_LITTLE_ENDIAN,
3424 };
3425
3426 static const MemoryRegionOps xhci_oper_ops = {
3427 .read = xhci_oper_read,
3428 .write = xhci_oper_write,
3429 .valid.min_access_size = 4,
3430 .valid.max_access_size = 4,
3431 .endianness = DEVICE_LITTLE_ENDIAN,
3432 };
3433
3434 static const MemoryRegionOps xhci_port_ops = {
3435 .read = xhci_port_read,
3436 .write = xhci_port_write,
3437 .valid.min_access_size = 4,
3438 .valid.max_access_size = 4,
3439 .endianness = DEVICE_LITTLE_ENDIAN,
3440 };
3441
3442 static const MemoryRegionOps xhci_runtime_ops = {
3443 .read = xhci_runtime_read,
3444 .write = xhci_runtime_write,
3445 .valid.min_access_size = 4,
3446 .valid.max_access_size = 4,
3447 .endianness = DEVICE_LITTLE_ENDIAN,
3448 };
3449
3450 static const MemoryRegionOps xhci_doorbell_ops = {
3451 .read = xhci_doorbell_read,
3452 .write = xhci_doorbell_write,
3453 .valid.min_access_size = 4,
3454 .valid.max_access_size = 4,
3455 .endianness = DEVICE_LITTLE_ENDIAN,
3456 };
3457
3458 static void xhci_attach(USBPort *usbport)
3459 {
3460 XHCIState *xhci = usbport->opaque;
3461 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3462
3463 xhci_port_update(port, 0);
3464 }
3465
3466 static void xhci_detach(USBPort *usbport)
3467 {
3468 XHCIState *xhci = usbport->opaque;
3469 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3470
3471 xhci_detach_slot(xhci, usbport);
3472 xhci_port_update(port, 1);
3473 }
3474
3475 static void xhci_wakeup(USBPort *usbport)
3476 {
3477 XHCIState *xhci = usbport->opaque;
3478 XHCIPort *port = xhci_lookup_port(xhci, usbport);
3479
3480 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) {
3481 return;
3482 }
3483 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS);
3484 xhci_port_notify(port, PORTSC_PLC);
3485 }
3486
3487 static void xhci_complete(USBPort *port, USBPacket *packet)
3488 {
3489 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet);
3490
3491 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) {
3492 xhci_ep_nuke_one_xfer(xfer, 0);
3493 return;
3494 }
3495 xhci_complete_packet(xfer);
3496 xhci_kick_epctx(xfer->epctx, xfer->streamid);
3497 if (xfer->complete) {
3498 xhci_ep_free_xfer(xfer);
3499 }
3500 }
3501
3502 static void xhci_child_detach(USBPort *uport, USBDevice *child)
3503 {
3504 USBBus *bus = usb_bus_from_device(child);
3505 XHCIState *xhci = container_of(bus, XHCIState, bus);
3506
3507 xhci_detach_slot(xhci, child->port);
3508 }
3509
3510 static USBPortOps xhci_uport_ops = {
3511 .attach = xhci_attach,
3512 .detach = xhci_detach,
3513 .wakeup = xhci_wakeup,
3514 .complete = xhci_complete,
3515 .child_detach = xhci_child_detach,
3516 };
3517
3518 static int xhci_find_epid(USBEndpoint *ep)
3519 {
3520 if (ep->nr == 0) {
3521 return 1;
3522 }
3523 if (ep->pid == USB_TOKEN_IN) {
3524 return ep->nr * 2 + 1;
3525 } else {
3526 return ep->nr * 2;
3527 }
3528 }
3529
3530 static USBEndpoint *xhci_epid_to_usbep(XHCIState *xhci,
3531 unsigned int slotid, unsigned int epid)
3532 {
3533 assert(slotid >= 1 && slotid <= xhci->numslots);
3534
3535 if (!xhci->slots[slotid - 1].uport) {
3536 return NULL;
3537 }
3538
3539 return usb_ep_get(xhci->slots[slotid - 1].uport->dev,
3540 (epid & 1) ? USB_TOKEN_IN : USB_TOKEN_OUT, epid >> 1);
3541 }
3542
3543 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep,
3544 unsigned int stream)
3545 {
3546 XHCIState *xhci = container_of(bus, XHCIState, bus);
3547 int slotid;
3548
3549 DPRINTF("%s\n", __func__);
3550 slotid = ep->dev->addr;
3551 if (slotid == 0 || !xhci->slots[slotid-1].enabled) {
3552 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr);
3553 return;
3554 }
3555 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream);
3556 }
3557
3558 static USBBusOps xhci_bus_ops = {
3559 .wakeup_endpoint = xhci_wakeup_endpoint,
3560 };
3561
3562 static void usb_xhci_init(XHCIState *xhci)
3563 {
3564 DeviceState *dev = DEVICE(xhci);
3565 XHCIPort *port;
3566 int i, usbports, speedmask;
3567
3568 xhci->usbsts = USBSTS_HCH;
3569
3570 if (xhci->numports_2 > MAXPORTS_2) {
3571 xhci->numports_2 = MAXPORTS_2;
3572 }
3573 if (xhci->numports_3 > MAXPORTS_3) {
3574 xhci->numports_3 = MAXPORTS_3;
3575 }
3576 usbports = MAX(xhci->numports_2, xhci->numports_3);
3577 xhci->numports = xhci->numports_2 + xhci->numports_3;
3578
3579 usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, dev);
3580
3581 for (i = 0; i < usbports; i++) {
3582 speedmask = 0;
3583 if (i < xhci->numports_2) {
3584 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
3585 port = &xhci->ports[i + xhci->numports_3];
3586 port->portnr = i + 1 + xhci->numports_3;
3587 } else {
3588 port = &xhci->ports[i];
3589 port->portnr = i + 1;
3590 }
3591 port->uport = &xhci->uports[i];
3592 port->speedmask =
3593 USB_SPEED_MASK_LOW |
3594 USB_SPEED_MASK_FULL |
3595 USB_SPEED_MASK_HIGH;
3596 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1);
3597 speedmask |= port->speedmask;
3598 }
3599 if (i < xhci->numports_3) {
3600 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) {
3601 port = &xhci->ports[i];
3602 port->portnr = i + 1;
3603 } else {
3604 port = &xhci->ports[i + xhci->numports_2];
3605 port->portnr = i + 1 + xhci->numports_2;
3606 }
3607 port->uport = &xhci->uports[i];
3608 port->speedmask = USB_SPEED_MASK_SUPER;
3609 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1);
3610 speedmask |= port->speedmask;
3611 }
3612 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i,
3613 &xhci_uport_ops, speedmask);
3614 }
3615 }
3616
3617 static void usb_xhci_realize(struct PCIDevice *dev, Error **errp)
3618 {
3619 int i, ret;
3620 Error *err = NULL;
3621
3622 XHCIState *xhci = XHCI(dev);
3623
3624 dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */
3625 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
3626 dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
3627 dev->config[0x60] = 0x30; /* release number */
3628
3629 usb_xhci_init(xhci);
3630
3631 if (xhci->msi != ON_OFF_AUTO_OFF) {
3632 ret = msi_init(dev, 0x70, xhci->numintrs, true, false, &err);
3633 /* Any error other than -ENOTSUP(board's MSI support is broken)
3634 * is a programming error */
3635 assert(!ret || ret == -ENOTSUP);
3636 if (ret && xhci->msi == ON_OFF_AUTO_ON) {
3637 /* Can't satisfy user's explicit msi=on request, fail */
3638 error_append_hint(&err, "You have to use msi=auto (default) or "
3639 "msi=off with this machine type.\n");
3640 error_propagate(errp, err);
3641 return;
3642 }
3643 assert(!err || xhci->msi == ON_OFF_AUTO_AUTO);
3644 /* With msi=auto, we fall back to MSI off silently */
3645 error_free(err);
3646 }
3647
3648 if (xhci->numintrs > MAXINTRS) {
3649 xhci->numintrs = MAXINTRS;
3650 }
3651 while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */
3652 xhci->numintrs++;
3653 }
3654 if (xhci->numintrs < 1) {
3655 xhci->numintrs = 1;
3656 }
3657 if (xhci->numslots > MAXSLOTS) {
3658 xhci->numslots = MAXSLOTS;
3659 }
3660 if (xhci->numslots < 1) {
3661 xhci->numslots = 1;
3662 }
3663 if (xhci_get_flag(xhci, XHCI_FLAG_ENABLE_STREAMS)) {
3664 xhci->max_pstreams_mask = 7; /* == 256 primary streams */
3665 } else {
3666 xhci->max_pstreams_mask = 0;
3667 }
3668
3669 xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci);
3670
3671 memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS);
3672 memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci,
3673 "capabilities", LEN_CAP);
3674 memory_region_init_io(&xhci->mem_oper, OBJECT(xhci), &xhci_oper_ops, xhci,
3675 "operational", 0x400);
3676 memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci), &xhci_runtime_ops, xhci,
3677 "runtime", LEN_RUNTIME);
3678 memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci), &xhci_doorbell_ops, xhci,
3679 "doorbell", LEN_DOORBELL);
3680
3681 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap);
3682 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper);
3683 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime);
3684 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell);
3685
3686 for (i = 0; i < xhci->numports; i++) {
3687 XHCIPort *port = &xhci->ports[i];
3688 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i;
3689 port->xhci = xhci;
3690 memory_region_init_io(&port->mem, OBJECT(xhci), &xhci_port_ops, port,
3691 port->name, 0x10);
3692 memory_region_add_subregion(&xhci->mem, offset, &port->mem);
3693 }
3694
3695 pci_register_bar(dev, 0,
3696 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
3697 &xhci->mem);
3698
3699 if (pci_bus_is_express(dev->bus) ||
3700 xhci_get_flag(xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) {
3701 ret = pcie_endpoint_cap_init(dev, 0xa0);
3702 assert(ret >= 0);
3703 }
3704
3705 if (xhci->msix != ON_OFF_AUTO_OFF) {
3706 /* TODO check for errors */
3707 msix_init(dev, xhci->numintrs,
3708 &xhci->mem, 0, OFF_MSIX_TABLE,
3709 &xhci->mem, 0, OFF_MSIX_PBA,
3710 0x90);
3711 }
3712 }
3713
3714 static void usb_xhci_exit(PCIDevice *dev)
3715 {
3716 int i;
3717 XHCIState *xhci = XHCI(dev);
3718
3719 trace_usb_xhci_exit();
3720
3721 for (i = 0; i < xhci->numslots; i++) {
3722 xhci_disable_slot(xhci, i + 1);
3723 }
3724
3725 if (xhci->mfwrap_timer) {
3726 timer_del(xhci->mfwrap_timer);
3727 timer_free(xhci->mfwrap_timer);
3728 xhci->mfwrap_timer = NULL;
3729 }
3730
3731 memory_region_del_subregion(&xhci->mem, &xhci->mem_cap);
3732 memory_region_del_subregion(&xhci->mem, &xhci->mem_oper);
3733 memory_region_del_subregion(&xhci->mem, &xhci->mem_runtime);
3734 memory_region_del_subregion(&xhci->mem, &xhci->mem_doorbell);
3735
3736 for (i = 0; i < xhci->numports; i++) {
3737 XHCIPort *port = &xhci->ports[i];
3738 memory_region_del_subregion(&xhci->mem, &port->mem);
3739 }
3740
3741 /* destroy msix memory region */
3742 if (dev->msix_table && dev->msix_pba
3743 && dev->msix_entry_used) {
3744 msix_uninit(dev, &xhci->mem, &xhci->mem);
3745 }
3746
3747 usb_bus_release(&xhci->bus);
3748 }
3749
3750 static int usb_xhci_post_load(void *opaque, int version_id)
3751 {
3752 XHCIState *xhci = opaque;
3753 PCIDevice *pci_dev = PCI_DEVICE(xhci);
3754 XHCISlot *slot;
3755 XHCIEPContext *epctx;
3756 dma_addr_t dcbaap, pctx;
3757 uint32_t slot_ctx[4];
3758 uint32_t ep_ctx[5];
3759 int slotid, epid, state, intr;
3760
3761 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
3762
3763 for (slotid = 1; slotid <= xhci->numslots; slotid++) {
3764 slot = &xhci->slots[slotid-1];
3765 if (!slot->addressed) {
3766 continue;
3767 }
3768 slot->ctx =
3769 xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid));
3770 xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx));
3771 slot->uport = xhci_lookup_uport(xhci, slot_ctx);
3772 if (!slot->uport) {
3773 /* should not happen, but may trigger on guest bugs */
3774 slot->enabled = 0;
3775 slot->addressed = 0;
3776 continue;
3777 }
3778 assert(slot->uport && slot->uport->dev);
3779
3780 for (epid = 1; epid <= 31; epid++) {
3781 pctx = slot->ctx + 32 * epid;
3782 xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx));
3783 state = ep_ctx[0] & EP_STATE_MASK;
3784 if (state == EP_DISABLED) {
3785 continue;
3786 }
3787 epctx = xhci_alloc_epctx(xhci, slotid, epid);
3788 slot->eps[epid-1] = epctx;
3789 xhci_init_epctx(epctx, pctx, ep_ctx);
3790 epctx->state = state;
3791 if (state == EP_RUNNING) {
3792 /* kick endpoint after vmload is finished */
3793 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
3794 }
3795 }
3796 }
3797
3798 for (intr = 0; intr < xhci->numintrs; intr++) {
3799 if (xhci->intr[intr].msix_used) {
3800 msix_vector_use(pci_dev, intr);
3801 } else {
3802 msix_vector_unuse(pci_dev, intr);
3803 }
3804 }
3805
3806 return 0;
3807 }
3808
3809 static const VMStateDescription vmstate_xhci_ring = {
3810 .name = "xhci-ring",
3811 .version_id = 1,
3812 .fields = (VMStateField[]) {
3813 VMSTATE_UINT64(dequeue, XHCIRing),
3814 VMSTATE_BOOL(ccs, XHCIRing),
3815 VMSTATE_END_OF_LIST()
3816 }
3817 };
3818
3819 static const VMStateDescription vmstate_xhci_port = {
3820 .name = "xhci-port",
3821 .version_id = 1,
3822 .fields = (VMStateField[]) {
3823 VMSTATE_UINT32(portsc, XHCIPort),
3824 VMSTATE_END_OF_LIST()
3825 }
3826 };
3827
3828 static const VMStateDescription vmstate_xhci_slot = {
3829 .name = "xhci-slot",
3830 .version_id = 1,
3831 .fields = (VMStateField[]) {
3832 VMSTATE_BOOL(enabled, XHCISlot),
3833 VMSTATE_BOOL(addressed, XHCISlot),
3834 VMSTATE_END_OF_LIST()
3835 }
3836 };
3837
3838 static const VMStateDescription vmstate_xhci_event = {
3839 .name = "xhci-event",
3840 .version_id = 1,
3841 .fields = (VMStateField[]) {
3842 VMSTATE_UINT32(type, XHCIEvent),
3843 VMSTATE_UINT32(ccode, XHCIEvent),
3844 VMSTATE_UINT64(ptr, XHCIEvent),
3845 VMSTATE_UINT32(length, XHCIEvent),
3846 VMSTATE_UINT32(flags, XHCIEvent),
3847 VMSTATE_UINT8(slotid, XHCIEvent),
3848 VMSTATE_UINT8(epid, XHCIEvent),
3849 VMSTATE_END_OF_LIST()
3850 }
3851 };
3852
3853 static bool xhci_er_full(void *opaque, int version_id)
3854 {
3855 struct XHCIInterrupter *intr = opaque;
3856 return intr->er_full;
3857 }
3858
3859 static const VMStateDescription vmstate_xhci_intr = {
3860 .name = "xhci-intr",
3861 .version_id = 1,
3862 .fields = (VMStateField[]) {
3863 /* registers */
3864 VMSTATE_UINT32(iman, XHCIInterrupter),
3865 VMSTATE_UINT32(imod, XHCIInterrupter),
3866 VMSTATE_UINT32(erstsz, XHCIInterrupter),
3867 VMSTATE_UINT32(erstba_low, XHCIInterrupter),
3868 VMSTATE_UINT32(erstba_high, XHCIInterrupter),
3869 VMSTATE_UINT32(erdp_low, XHCIInterrupter),
3870 VMSTATE_UINT32(erdp_high, XHCIInterrupter),
3871
3872 /* state */
3873 VMSTATE_BOOL(msix_used, XHCIInterrupter),
3874 VMSTATE_BOOL(er_pcs, XHCIInterrupter),
3875 VMSTATE_UINT64(er_start, XHCIInterrupter),
3876 VMSTATE_UINT32(er_size, XHCIInterrupter),
3877 VMSTATE_UINT32(er_ep_idx, XHCIInterrupter),
3878
3879 /* event queue (used if ring is full) */
3880 VMSTATE_BOOL(er_full, XHCIInterrupter),
3881 VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full),
3882 VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full),
3883 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE,
3884 xhci_er_full, 1,
3885 vmstate_xhci_event, XHCIEvent),
3886
3887 VMSTATE_END_OF_LIST()
3888 }
3889 };
3890
3891 static const VMStateDescription vmstate_xhci = {
3892 .name = "xhci",
3893 .version_id = 1,
3894 .post_load = usb_xhci_post_load,
3895 .fields = (VMStateField[]) {
3896 VMSTATE_PCIE_DEVICE(parent_obj, XHCIState),
3897 VMSTATE_MSIX(parent_obj, XHCIState),
3898
3899 VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1,
3900 vmstate_xhci_port, XHCIPort),
3901 VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1,
3902 vmstate_xhci_slot, XHCISlot),
3903 VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1,
3904 vmstate_xhci_intr, XHCIInterrupter),
3905
3906 /* Operational Registers */
3907 VMSTATE_UINT32(usbcmd, XHCIState),
3908 VMSTATE_UINT32(usbsts, XHCIState),
3909 VMSTATE_UINT32(dnctrl, XHCIState),
3910 VMSTATE_UINT32(crcr_low, XHCIState),
3911 VMSTATE_UINT32(crcr_high, XHCIState),
3912 VMSTATE_UINT32(dcbaap_low, XHCIState),
3913 VMSTATE_UINT32(dcbaap_high, XHCIState),
3914 VMSTATE_UINT32(config, XHCIState),
3915
3916 /* Runtime Registers & state */
3917 VMSTATE_INT64(mfindex_start, XHCIState),
3918 VMSTATE_TIMER_PTR(mfwrap_timer, XHCIState),
3919 VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing),
3920
3921 VMSTATE_END_OF_LIST()
3922 }
3923 };
3924
3925 static Property xhci_properties[] = {
3926 DEFINE_PROP_ON_OFF_AUTO("msi", XHCIState, msi, ON_OFF_AUTO_AUTO),
3927 DEFINE_PROP_ON_OFF_AUTO("msix", XHCIState, msix, ON_OFF_AUTO_AUTO),
3928 DEFINE_PROP_BIT("superspeed-ports-first",
3929 XHCIState, flags, XHCI_FLAG_SS_FIRST, true),
3930 DEFINE_PROP_BIT("force-pcie-endcap", XHCIState, flags,
3931 XHCI_FLAG_FORCE_PCIE_ENDCAP, false),
3932 DEFINE_PROP_BIT("streams", XHCIState, flags,
3933 XHCI_FLAG_ENABLE_STREAMS, true),
3934 DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS),
3935 DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS),
3936 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4),
3937 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4),
3938 DEFINE_PROP_END_OF_LIST(),
3939 };
3940
3941 static void xhci_class_init(ObjectClass *klass, void *data)
3942 {
3943 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
3944 DeviceClass *dc = DEVICE_CLASS(klass);
3945
3946 dc->vmsd = &vmstate_xhci;
3947 dc->props = xhci_properties;
3948 dc->reset = xhci_reset;
3949 set_bit(DEVICE_CATEGORY_USB, dc->categories);
3950 k->realize = usb_xhci_realize;
3951 k->exit = usb_xhci_exit;
3952 k->vendor_id = PCI_VENDOR_ID_NEC;
3953 k->device_id = PCI_DEVICE_ID_NEC_UPD720200;
3954 k->class_id = PCI_CLASS_SERIAL_USB;
3955 k->revision = 0x03;
3956 k->is_express = 1;
3957 }
3958
3959 static const TypeInfo xhci_info = {
3960 .name = TYPE_XHCI,
3961 .parent = TYPE_PCI_DEVICE,
3962 .instance_size = sizeof(XHCIState),
3963 .class_init = xhci_class_init,
3964 };
3965
3966 static void xhci_register_types(void)
3967 {
3968 type_register_static(&xhci_info);
3969 }
3970
3971 type_init(xhci_register_types)
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