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[qemu.git] / hw / usb-ehci.c
1 /*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 *
6 * EHCI project was started by Mark Burkley, with contributions by
7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
8 * Jan Kiszka and Vincent Palatin contributed bugfixes.
9 *
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or(at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 *
24 * TODO:
25 * o Downstream port handoff
26 */
27
28 #include "hw.h"
29 #include "qemu-timer.h"
30 #include "usb.h"
31 #include "pci.h"
32 #include "monitor.h"
33 #include "trace.h"
34
35 #define EHCI_DEBUG 0
36
37 #if EHCI_DEBUG
38 #define DPRINTF printf
39 #else
40 #define DPRINTF(...)
41 #endif
42
43 /* internal processing - reset HC to try and recover */
44 #define USB_RET_PROCERR (-99)
45
46 #define MMIO_SIZE 0x1000
47
48 /* Capability Registers Base Address - section 2.2 */
49 #define CAPREGBASE 0x0000
50 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
51 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
52 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
53 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
54 #define EECP HCCPARAMS + 1
55 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
56 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
57
58 #define OPREGBASE 0x0020 // Operational Registers Base Address
59
60 #define USBCMD OPREGBASE + 0x0000
61 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
62 #define USBCMD_HCRESET (1 << 1) // HC Reset
63 #define USBCMD_FLS (3 << 2) // Frame List Size
64 #define USBCMD_FLS_SH 2 // Frame List Size Shift
65 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
66 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
67 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
68 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
69 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
70 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
71 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
72 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
73
74 #define USBSTS OPREGBASE + 0x0004
75 #define USBSTS_RO_MASK 0x0000003f
76 #define USBSTS_INT (1 << 0) // USB Interrupt
77 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
78 #define USBSTS_PCD (1 << 2) // Port Change Detect
79 #define USBSTS_FLR (1 << 3) // Frame List Rollover
80 #define USBSTS_HSE (1 << 4) // Host System Error
81 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
82 #define USBSTS_HALT (1 << 12) // HC Halted
83 #define USBSTS_REC (1 << 13) // Reclamation
84 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
85 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
86
87 /*
88 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
89 * so no need to redefine here.
90 */
91 #define USBINTR OPREGBASE + 0x0008
92 #define USBINTR_MASK 0x0000003f
93
94 #define FRINDEX OPREGBASE + 0x000c
95 #define CTRLDSSEGMENT OPREGBASE + 0x0010
96 #define PERIODICLISTBASE OPREGBASE + 0x0014
97 #define ASYNCLISTADDR OPREGBASE + 0x0018
98 #define ASYNCLISTADDR_MASK 0xffffffe0
99
100 #define CONFIGFLAG OPREGBASE + 0x0040
101
102 #define PORTSC (OPREGBASE + 0x0044)
103 #define PORTSC_BEGIN PORTSC
104 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
105 /*
106 * Bits that are reserverd or are read-only are masked out of values
107 * written to us by software
108 */
109 #define PORTSC_RO_MASK 0x007021c5
110 #define PORTSC_RWC_MASK 0x0000002a
111 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
112 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
113 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
114 #define PORTSC_PTC (15 << 16) // Port Test Control
115 #define PORTSC_PTC_SH 16 // Port Test Control shift
116 #define PORTSC_PIC (3 << 14) // Port Indicator Control
117 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
118 #define PORTSC_POWNER (1 << 13) // Port Owner
119 #define PORTSC_PPOWER (1 << 12) // Port Power
120 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
121 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
122 #define PORTSC_PRESET (1 << 8) // Port Reset
123 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
124 #define PORTSC_FPRES (1 << 6) // Force Port Resume
125 #define PORTSC_OCC (1 << 5) // Over Current Change
126 #define PORTSC_OCA (1 << 4) // Over Current Active
127 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
128 #define PORTSC_PED (1 << 2) // Port Enable/Disable
129 #define PORTSC_CSC (1 << 1) // Connect Status Change
130 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
131
132 #define FRAME_TIMER_FREQ 1000
133 #define FRAME_TIMER_USEC (1000000 / FRAME_TIMER_FREQ)
134
135 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
136 #define NB_PORTS 4 // Number of downstream ports
137 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
138 #define MAX_ITERATIONS 20 // Max number of QH before we break the loop
139 #define MAX_QH 100 // Max allowable queue heads in a chain
140
141 /* Internal periodic / asynchronous schedule state machine states
142 */
143 typedef enum {
144 EST_INACTIVE = 1000,
145 EST_ACTIVE,
146 EST_EXECUTING,
147 EST_SLEEPING,
148 /* The following states are internal to the state machine function
149 */
150 EST_WAITLISTHEAD,
151 EST_FETCHENTRY,
152 EST_FETCHQH,
153 EST_FETCHITD,
154 EST_ADVANCEQUEUE,
155 EST_FETCHQTD,
156 EST_EXECUTE,
157 EST_WRITEBACK,
158 EST_HORIZONTALQH
159 } EHCI_STATES;
160
161 /* macros for accessing fields within next link pointer entry */
162 #define NLPTR_GET(x) ((x) & 0xffffffe0)
163 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
164 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
165
166 /* link pointer types */
167 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
168 #define NLPTR_TYPE_QH 1 // queue head
169 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
170 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
171
172
173 /* EHCI spec version 1.0 Section 3.3
174 */
175 typedef struct EHCIitd {
176 uint32_t next;
177
178 uint32_t transact[8];
179 #define ITD_XACT_ACTIVE (1 << 31)
180 #define ITD_XACT_DBERROR (1 << 30)
181 #define ITD_XACT_BABBLE (1 << 29)
182 #define ITD_XACT_XACTERR (1 << 28)
183 #define ITD_XACT_LENGTH_MASK 0x0fff0000
184 #define ITD_XACT_LENGTH_SH 16
185 #define ITD_XACT_IOC (1 << 15)
186 #define ITD_XACT_PGSEL_MASK 0x00007000
187 #define ITD_XACT_PGSEL_SH 12
188 #define ITD_XACT_OFFSET_MASK 0x00000fff
189
190 uint32_t bufptr[7];
191 #define ITD_BUFPTR_MASK 0xfffff000
192 #define ITD_BUFPTR_SH 12
193 #define ITD_BUFPTR_EP_MASK 0x00000f00
194 #define ITD_BUFPTR_EP_SH 8
195 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
196 #define ITD_BUFPTR_DEVADDR_SH 0
197 #define ITD_BUFPTR_DIRECTION (1 << 11)
198 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
199 #define ITD_BUFPTR_MAXPKT_SH 0
200 #define ITD_BUFPTR_MULT_MASK 0x00000003
201 #define ITD_BUFPTR_MULT_SH 0
202 } EHCIitd;
203
204 /* EHCI spec version 1.0 Section 3.4
205 */
206 typedef struct EHCIsitd {
207 uint32_t next; // Standard next link pointer
208 uint32_t epchar;
209 #define SITD_EPCHAR_IO (1 << 31)
210 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
211 #define SITD_EPCHAR_PORTNUM_SH 24
212 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
213 #define SITD_EPCHAR_HUBADDR_SH 16
214 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
215 #define SITD_EPCHAR_EPNUM_SH 8
216 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
217
218 uint32_t uframe;
219 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
220 #define SITD_UFRAME_CMASK_SH 8
221 #define SITD_UFRAME_SMASK_MASK 0x000000ff
222
223 uint32_t results;
224 #define SITD_RESULTS_IOC (1 << 31)
225 #define SITD_RESULTS_PGSEL (1 << 30)
226 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
227 #define SITD_RESULTS_TYBYTES_SH 16
228 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
229 #define SITD_RESULTS_CPROGMASK_SH 8
230 #define SITD_RESULTS_ACTIVE (1 << 7)
231 #define SITD_RESULTS_ERR (1 << 6)
232 #define SITD_RESULTS_DBERR (1 << 5)
233 #define SITD_RESULTS_BABBLE (1 << 4)
234 #define SITD_RESULTS_XACTERR (1 << 3)
235 #define SITD_RESULTS_MISSEDUF (1 << 2)
236 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
237
238 uint32_t bufptr[2];
239 #define SITD_BUFPTR_MASK 0xfffff000
240 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
241 #define SITD_BUFPTR_TPOS_MASK 0x00000018
242 #define SITD_BUFPTR_TPOS_SH 3
243 #define SITD_BUFPTR_TCNT_MASK 0x00000007
244
245 uint32_t backptr; // Standard next link pointer
246 } EHCIsitd;
247
248 /* EHCI spec version 1.0 Section 3.5
249 */
250 typedef struct EHCIqtd {
251 uint32_t next; // Standard next link pointer
252 uint32_t altnext; // Standard next link pointer
253 uint32_t token;
254 #define QTD_TOKEN_DTOGGLE (1 << 31)
255 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
256 #define QTD_TOKEN_TBYTES_SH 16
257 #define QTD_TOKEN_IOC (1 << 15)
258 #define QTD_TOKEN_CPAGE_MASK 0x00007000
259 #define QTD_TOKEN_CPAGE_SH 12
260 #define QTD_TOKEN_CERR_MASK 0x00000c00
261 #define QTD_TOKEN_CERR_SH 10
262 #define QTD_TOKEN_PID_MASK 0x00000300
263 #define QTD_TOKEN_PID_SH 8
264 #define QTD_TOKEN_ACTIVE (1 << 7)
265 #define QTD_TOKEN_HALT (1 << 6)
266 #define QTD_TOKEN_DBERR (1 << 5)
267 #define QTD_TOKEN_BABBLE (1 << 4)
268 #define QTD_TOKEN_XACTERR (1 << 3)
269 #define QTD_TOKEN_MISSEDUF (1 << 2)
270 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
271 #define QTD_TOKEN_PING (1 << 0)
272
273 uint32_t bufptr[5]; // Standard buffer pointer
274 #define QTD_BUFPTR_MASK 0xfffff000
275 } EHCIqtd;
276
277 /* EHCI spec version 1.0 Section 3.6
278 */
279 typedef struct EHCIqh {
280 uint32_t next; // Standard next link pointer
281
282 /* endpoint characteristics */
283 uint32_t epchar;
284 #define QH_EPCHAR_RL_MASK 0xf0000000
285 #define QH_EPCHAR_RL_SH 28
286 #define QH_EPCHAR_C (1 << 27)
287 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
288 #define QH_EPCHAR_MPLEN_SH 16
289 #define QH_EPCHAR_H (1 << 15)
290 #define QH_EPCHAR_DTC (1 << 14)
291 #define QH_EPCHAR_EPS_MASK 0x00003000
292 #define QH_EPCHAR_EPS_SH 12
293 #define EHCI_QH_EPS_FULL 0
294 #define EHCI_QH_EPS_LOW 1
295 #define EHCI_QH_EPS_HIGH 2
296 #define EHCI_QH_EPS_RESERVED 3
297
298 #define QH_EPCHAR_EP_MASK 0x00000f00
299 #define QH_EPCHAR_EP_SH 8
300 #define QH_EPCHAR_I (1 << 7)
301 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
302 #define QH_EPCHAR_DEVADDR_SH 0
303
304 /* endpoint capabilities */
305 uint32_t epcap;
306 #define QH_EPCAP_MULT_MASK 0xc0000000
307 #define QH_EPCAP_MULT_SH 30
308 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
309 #define QH_EPCAP_PORTNUM_SH 23
310 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
311 #define QH_EPCAP_HUBADDR_SH 16
312 #define QH_EPCAP_CMASK_MASK 0x0000ff00
313 #define QH_EPCAP_CMASK_SH 8
314 #define QH_EPCAP_SMASK_MASK 0x000000ff
315 #define QH_EPCAP_SMASK_SH 0
316
317 uint32_t current_qtd; // Standard next link pointer
318 uint32_t next_qtd; // Standard next link pointer
319 uint32_t altnext_qtd;
320 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
321 #define QH_ALTNEXT_NAKCNT_SH 1
322
323 uint32_t token; // Same as QTD token
324 uint32_t bufptr[5]; // Standard buffer pointer
325 #define BUFPTR_CPROGMASK_MASK 0x000000ff
326 #define BUFPTR_FRAMETAG_MASK 0x0000001f
327 #define BUFPTR_SBYTES_MASK 0x00000fe0
328 #define BUFPTR_SBYTES_SH 5
329 } EHCIqh;
330
331 /* EHCI spec version 1.0 Section 3.7
332 */
333 typedef struct EHCIfstn {
334 uint32_t next; // Standard next link pointer
335 uint32_t backptr; // Standard next link pointer
336 } EHCIfstn;
337
338 typedef struct EHCIQueue EHCIQueue;
339 typedef struct EHCIState EHCIState;
340
341 enum async_state {
342 EHCI_ASYNC_NONE = 0,
343 EHCI_ASYNC_INFLIGHT,
344 EHCI_ASYNC_FINISHED,
345 };
346
347 struct EHCIQueue {
348 EHCIState *ehci;
349 QTAILQ_ENTRY(EHCIQueue) next;
350 bool async_schedule;
351 uint32_t seen, ts;
352
353 /* cached data from guest - needs to be flushed
354 * when guest removes an entry (doorbell, handshake sequence)
355 */
356 EHCIqh qh; // copy of current QH (being worked on)
357 uint32_t qhaddr; // address QH read from
358 EHCIqtd qtd; // copy of current QTD (being worked on)
359 uint32_t qtdaddr; // address QTD read from
360
361 USBPacket packet;
362 uint8_t buffer[BUFF_SIZE];
363 int pid;
364 uint32_t tbytes;
365 enum async_state async;
366 int usb_status;
367 };
368
369 struct EHCIState {
370 PCIDevice dev;
371 USBBus bus;
372 qemu_irq irq;
373 target_phys_addr_t mem_base;
374 int mem;
375 int num_ports;
376 /*
377 * EHCI spec version 1.0 Section 2.3
378 * Host Controller Operational Registers
379 */
380 union {
381 uint8_t mmio[MMIO_SIZE];
382 struct {
383 uint8_t cap[OPREGBASE];
384 uint32_t usbcmd;
385 uint32_t usbsts;
386 uint32_t usbintr;
387 uint32_t frindex;
388 uint32_t ctrldssegment;
389 uint32_t periodiclistbase;
390 uint32_t asynclistaddr;
391 uint32_t notused[9];
392 uint32_t configflag;
393 uint32_t portsc[NB_PORTS];
394 };
395 };
396
397 /*
398 * Internal states, shadow registers, etc
399 */
400 uint32_t sofv;
401 QEMUTimer *frame_timer;
402 int attach_poll_counter;
403 int astate; // Current state in asynchronous schedule
404 int pstate; // Current state in periodic schedule
405 USBPort ports[NB_PORTS];
406 uint32_t usbsts_pending;
407 QTAILQ_HEAD(, EHCIQueue) queues;
408
409 uint32_t a_fetch_addr; // which address to look at next
410 uint32_t p_fetch_addr; // which address to look at next
411
412 USBPacket ipacket;
413 uint8_t ibuffer[BUFF_SIZE];
414 int isoch_pause;
415
416 uint32_t last_run_usec;
417 uint32_t frame_end_usec;
418 };
419
420 #define SET_LAST_RUN_CLOCK(s) \
421 (s)->last_run_usec = qemu_get_clock_ns(vm_clock) / 1000;
422
423 /* nifty macros from Arnon's EHCI version */
424 #define get_field(data, field) \
425 (((data) & field##_MASK) >> field##_SH)
426
427 #define set_field(data, newval, field) do { \
428 uint32_t val = *data; \
429 val &= ~ field##_MASK; \
430 val |= ((newval) << field##_SH) & field##_MASK; \
431 *data = val; \
432 } while(0)
433
434 static const char *ehci_state_names[] = {
435 [ EST_INACTIVE ] = "INACTIVE",
436 [ EST_ACTIVE ] = "ACTIVE",
437 [ EST_EXECUTING ] = "EXECUTING",
438 [ EST_SLEEPING ] = "SLEEPING",
439 [ EST_WAITLISTHEAD ] = "WAITLISTHEAD",
440 [ EST_FETCHENTRY ] = "FETCH ENTRY",
441 [ EST_FETCHQH ] = "FETCH QH",
442 [ EST_FETCHITD ] = "FETCH ITD",
443 [ EST_ADVANCEQUEUE ] = "ADVANCEQUEUE",
444 [ EST_FETCHQTD ] = "FETCH QTD",
445 [ EST_EXECUTE ] = "EXECUTE",
446 [ EST_WRITEBACK ] = "WRITEBACK",
447 [ EST_HORIZONTALQH ] = "HORIZONTALQH",
448 };
449
450 static const char *ehci_mmio_names[] = {
451 [ CAPLENGTH ] = "CAPLENGTH",
452 [ HCIVERSION ] = "HCIVERSION",
453 [ HCSPARAMS ] = "HCSPARAMS",
454 [ HCCPARAMS ] = "HCCPARAMS",
455 [ USBCMD ] = "USBCMD",
456 [ USBSTS ] = "USBSTS",
457 [ USBINTR ] = "USBINTR",
458 [ FRINDEX ] = "FRINDEX",
459 [ PERIODICLISTBASE ] = "P-LIST BASE",
460 [ ASYNCLISTADDR ] = "A-LIST ADDR",
461 [ PORTSC_BEGIN ] = "PORTSC #0",
462 [ PORTSC_BEGIN + 4] = "PORTSC #1",
463 [ PORTSC_BEGIN + 8] = "PORTSC #2",
464 [ PORTSC_BEGIN + 12] = "PORTSC #3",
465 [ CONFIGFLAG ] = "CONFIGFLAG",
466 };
467
468 static const char *nr2str(const char **n, size_t len, uint32_t nr)
469 {
470 if (nr < len && n[nr] != NULL) {
471 return n[nr];
472 } else {
473 return "unknown";
474 }
475 }
476
477 static const char *state2str(uint32_t state)
478 {
479 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
480 }
481
482 static const char *addr2str(target_phys_addr_t addr)
483 {
484 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
485 }
486
487 static void ehci_trace_usbsts(uint32_t mask, int state)
488 {
489 /* interrupts */
490 if (mask & USBSTS_INT) {
491 trace_usb_ehci_usbsts("INT", state);
492 }
493 if (mask & USBSTS_ERRINT) {
494 trace_usb_ehci_usbsts("ERRINT", state);
495 }
496 if (mask & USBSTS_PCD) {
497 trace_usb_ehci_usbsts("PCD", state);
498 }
499 if (mask & USBSTS_FLR) {
500 trace_usb_ehci_usbsts("FLR", state);
501 }
502 if (mask & USBSTS_HSE) {
503 trace_usb_ehci_usbsts("HSE", state);
504 }
505 if (mask & USBSTS_IAA) {
506 trace_usb_ehci_usbsts("IAA", state);
507 }
508
509 /* status */
510 if (mask & USBSTS_HALT) {
511 trace_usb_ehci_usbsts("HALT", state);
512 }
513 if (mask & USBSTS_REC) {
514 trace_usb_ehci_usbsts("REC", state);
515 }
516 if (mask & USBSTS_PSS) {
517 trace_usb_ehci_usbsts("PSS", state);
518 }
519 if (mask & USBSTS_ASS) {
520 trace_usb_ehci_usbsts("ASS", state);
521 }
522 }
523
524 static inline void ehci_set_usbsts(EHCIState *s, int mask)
525 {
526 if ((s->usbsts & mask) == mask) {
527 return;
528 }
529 ehci_trace_usbsts(mask, 1);
530 s->usbsts |= mask;
531 }
532
533 static inline void ehci_clear_usbsts(EHCIState *s, int mask)
534 {
535 if ((s->usbsts & mask) == 0) {
536 return;
537 }
538 ehci_trace_usbsts(mask, 0);
539 s->usbsts &= ~mask;
540 }
541
542 static inline void ehci_set_interrupt(EHCIState *s, int intr)
543 {
544 int level = 0;
545
546 // TODO honour interrupt threshold requests
547
548 ehci_set_usbsts(s, intr);
549
550 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
551 level = 1;
552 }
553
554 qemu_set_irq(s->irq, level);
555 }
556
557 static inline void ehci_record_interrupt(EHCIState *s, int intr)
558 {
559 s->usbsts_pending |= intr;
560 }
561
562 static inline void ehci_commit_interrupt(EHCIState *s)
563 {
564 if (!s->usbsts_pending) {
565 return;
566 }
567 ehci_set_interrupt(s, s->usbsts_pending);
568 s->usbsts_pending = 0;
569 }
570
571 static void ehci_set_state(EHCIState *s, int async, int state)
572 {
573 if (async) {
574 trace_usb_ehci_state("async", state2str(state));
575 s->astate = state;
576 } else {
577 trace_usb_ehci_state("periodic", state2str(state));
578 s->pstate = state;
579 }
580 }
581
582 static int ehci_get_state(EHCIState *s, int async)
583 {
584 return async ? s->astate : s->pstate;
585 }
586
587 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr)
588 {
589 if (async) {
590 s->a_fetch_addr = addr;
591 } else {
592 s->p_fetch_addr = addr;
593 }
594 }
595
596 static int ehci_get_fetch_addr(EHCIState *s, int async)
597 {
598 return async ? s->a_fetch_addr : s->p_fetch_addr;
599 }
600
601 static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh)
602 {
603 trace_usb_ehci_qh(q, addr, qh->next,
604 qh->current_qtd, qh->next_qtd, qh->altnext_qtd,
605 get_field(qh->epchar, QH_EPCHAR_RL),
606 get_field(qh->epchar, QH_EPCHAR_MPLEN),
607 get_field(qh->epchar, QH_EPCHAR_EPS),
608 get_field(qh->epchar, QH_EPCHAR_EP),
609 get_field(qh->epchar, QH_EPCHAR_DEVADDR),
610 (bool)(qh->epchar & QH_EPCHAR_C),
611 (bool)(qh->epchar & QH_EPCHAR_H),
612 (bool)(qh->epchar & QH_EPCHAR_DTC),
613 (bool)(qh->epchar & QH_EPCHAR_I));
614 }
615
616 static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd)
617 {
618 trace_usb_ehci_qtd(q, addr, qtd->next, qtd->altnext,
619 get_field(qtd->token, QTD_TOKEN_TBYTES),
620 get_field(qtd->token, QTD_TOKEN_CPAGE),
621 get_field(qtd->token, QTD_TOKEN_CERR),
622 get_field(qtd->token, QTD_TOKEN_PID),
623 (bool)(qtd->token & QTD_TOKEN_IOC),
624 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
625 (bool)(qtd->token & QTD_TOKEN_HALT),
626 (bool)(qtd->token & QTD_TOKEN_BABBLE),
627 (bool)(qtd->token & QTD_TOKEN_XACTERR));
628 }
629
630 static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
631 {
632 trace_usb_ehci_itd(addr, itd->next,
633 get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
634 get_field(itd->bufptr[2], ITD_BUFPTR_MULT),
635 get_field(itd->bufptr[0], ITD_BUFPTR_EP),
636 get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
637 }
638
639 /* queue management */
640
641 static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, int async)
642 {
643 EHCIQueue *q;
644
645 q = qemu_mallocz(sizeof(*q));
646 q->ehci = ehci;
647 q->async_schedule = async;
648 QTAILQ_INSERT_HEAD(&ehci->queues, q, next);
649 trace_usb_ehci_queue_action(q, "alloc");
650 return q;
651 }
652
653 static void ehci_free_queue(EHCIQueue *q)
654 {
655 trace_usb_ehci_queue_action(q, "free");
656 if (q->async == EHCI_ASYNC_INFLIGHT) {
657 usb_cancel_packet(&q->packet);
658 }
659 QTAILQ_REMOVE(&q->ehci->queues, q, next);
660 qemu_free(q);
661 }
662
663 static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr)
664 {
665 EHCIQueue *q;
666
667 QTAILQ_FOREACH(q, &ehci->queues, next) {
668 if (addr == q->qhaddr) {
669 return q;
670 }
671 }
672 return NULL;
673 }
674
675 static void ehci_queues_rip_unused(EHCIState *ehci)
676 {
677 EHCIQueue *q, *tmp;
678
679 QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) {
680 if (q->seen) {
681 q->seen = 0;
682 q->ts = ehci->last_run_usec;
683 continue;
684 }
685 if (ehci->last_run_usec < q->ts + 250000) {
686 /* allow 0.25 sec idle */
687 continue;
688 }
689 ehci_free_queue(q);
690 }
691 }
692
693 static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev)
694 {
695 EHCIQueue *q, *tmp;
696
697 QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) {
698 if (q->packet.owner != dev) {
699 continue;
700 }
701 ehci_free_queue(q);
702 }
703 }
704
705 static void ehci_queues_rip_all(EHCIState *ehci)
706 {
707 EHCIQueue *q, *tmp;
708
709 QTAILQ_FOREACH_SAFE(q, &ehci->queues, next, tmp) {
710 ehci_free_queue(q);
711 }
712 }
713
714 /* Attach or detach a device on root hub */
715
716 static void ehci_attach(USBPort *port)
717 {
718 EHCIState *s = port->opaque;
719 uint32_t *portsc = &s->portsc[port->index];
720
721 trace_usb_ehci_port_attach(port->index, port->dev->product_desc);
722
723 *portsc |= PORTSC_CONNECT;
724 *portsc |= PORTSC_CSC;
725
726 /*
727 * If a high speed device is attached then we own this port(indicated
728 * by zero in the PORTSC_POWNER bit field) so set the status bit
729 * and set an interrupt if enabled.
730 */
731 if ( !(*portsc & PORTSC_POWNER)) {
732 ehci_set_interrupt(s, USBSTS_PCD);
733 }
734 }
735
736 static void ehci_detach(USBPort *port)
737 {
738 EHCIState *s = port->opaque;
739 uint32_t *portsc = &s->portsc[port->index];
740
741 trace_usb_ehci_port_detach(port->index);
742
743 *portsc &= ~PORTSC_CONNECT;
744 *portsc |= PORTSC_CSC;
745
746 /*
747 * If a high speed device is attached then we own this port(indicated
748 * by zero in the PORTSC_POWNER bit field) so set the status bit
749 * and set an interrupt if enabled.
750 */
751 if ( !(*portsc & PORTSC_POWNER)) {
752 ehci_set_interrupt(s, USBSTS_PCD);
753 }
754 }
755
756 /* 4.1 host controller initialization */
757 static void ehci_reset(void *opaque)
758 {
759 EHCIState *s = opaque;
760 int i;
761
762 trace_usb_ehci_reset();
763
764 memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
765
766 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
767 s->usbsts = USBSTS_HALT;
768
769 s->astate = EST_INACTIVE;
770 s->pstate = EST_INACTIVE;
771 s->isoch_pause = -1;
772 s->attach_poll_counter = 0;
773
774 for(i = 0; i < NB_PORTS; i++) {
775 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
776
777 if (s->ports[i].dev) {
778 usb_attach(&s->ports[i], s->ports[i].dev);
779 }
780 }
781 ehci_queues_rip_all(s);
782 }
783
784 static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
785 {
786 EHCIState *s = ptr;
787 uint32_t val;
788
789 val = s->mmio[addr];
790
791 return val;
792 }
793
794 static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
795 {
796 EHCIState *s = ptr;
797 uint32_t val;
798
799 val = s->mmio[addr] | (s->mmio[addr+1] << 8);
800
801 return val;
802 }
803
804 static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
805 {
806 EHCIState *s = ptr;
807 uint32_t val;
808
809 val = s->mmio[addr] | (s->mmio[addr+1] << 8) |
810 (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);
811
812 trace_usb_ehci_mmio_readl(addr, addr2str(addr), val);
813 return val;
814 }
815
816 static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
817 {
818 fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
819 exit(1);
820 }
821
822 static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
823 {
824 fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
825 exit(1);
826 }
827
828 static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
829 {
830 uint32_t *portsc = &s->portsc[port];
831 int rwc;
832 USBDevice *dev = s->ports[port].dev;
833
834 rwc = val & PORTSC_RWC_MASK;
835 val &= PORTSC_RO_MASK;
836
837 // handle_read_write_clear(&val, portsc, PORTSC_PEDC | PORTSC_CSC);
838
839 *portsc &= ~rwc;
840
841 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
842 trace_usb_ehci_port_reset(port, 1);
843 }
844
845 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
846 trace_usb_ehci_port_reset(port, 0);
847 usb_attach(&s->ports[port], dev);
848
849 // TODO how to handle reset of ports with no device
850 if (dev) {
851 usb_send_msg(dev, USB_MSG_RESET);
852 }
853
854 if (s->ports[port].dev) {
855 *portsc &= ~PORTSC_CSC;
856 }
857
858 /* Table 2.16 Set the enable bit(and enable bit change) to indicate
859 * to SW that this port has a high speed device attached
860 *
861 * TODO - when to disable?
862 */
863 val |= PORTSC_PED;
864 val |= PORTSC_PEDC;
865 }
866
867 *portsc &= ~PORTSC_RO_MASK;
868 *portsc |= val;
869 }
870
871 static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
872 {
873 EHCIState *s = ptr;
874 uint32_t *mmio = (uint32_t *)(&s->mmio[addr]);
875 uint32_t old = *mmio;
876 int i;
877
878 trace_usb_ehci_mmio_writel(addr, addr2str(addr), val);
879
880 /* Only aligned reads are allowed on OHCI */
881 if (addr & 3) {
882 fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
883 TARGET_FMT_plx "\n", addr);
884 return;
885 }
886
887 if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
888 handle_port_status_write(s, (addr-PORTSC)/4, val);
889 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
890 return;
891 }
892
893 if (addr < OPREGBASE) {
894 fprintf(stderr, "usb-ehci: write attempt to read-only register"
895 TARGET_FMT_plx "\n", addr);
896 return;
897 }
898
899
900 /* Do any register specific pre-write processing here. */
901 switch(addr) {
902 case USBCMD:
903 if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) {
904 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
905 SET_LAST_RUN_CLOCK(s);
906 ehci_clear_usbsts(s, USBSTS_HALT);
907 }
908
909 if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) {
910 qemu_del_timer(s->frame_timer);
911 // TODO - should finish out some stuff before setting halt
912 ehci_set_usbsts(s, USBSTS_HALT);
913 }
914
915 if (val & USBCMD_HCRESET) {
916 ehci_reset(s);
917 val &= ~USBCMD_HCRESET;
918 }
919
920 /* not supporting dynamic frame list size at the moment */
921 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
922 fprintf(stderr, "attempt to set frame list size -- value %d\n",
923 val & USBCMD_FLS);
924 val &= ~USBCMD_FLS;
925 }
926 break;
927
928 case USBSTS:
929 val &= USBSTS_RO_MASK; // bits 6 thru 31 are RO
930 ehci_clear_usbsts(s, val); // bits 0 thru 5 are R/WC
931 val = s->usbsts;
932 ehci_set_interrupt(s, 0);
933 break;
934
935 case USBINTR:
936 val &= USBINTR_MASK;
937 break;
938
939 case FRINDEX:
940 s->sofv = val >> 3;
941 break;
942
943 case CONFIGFLAG:
944 val &= 0x1;
945 if (val) {
946 for(i = 0; i < NB_PORTS; i++)
947 s->portsc[i] &= ~PORTSC_POWNER;
948 }
949 break;
950
951 case PERIODICLISTBASE:
952 if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) {
953 fprintf(stderr,
954 "ehci: PERIODIC list base register set while periodic schedule\n"
955 " is enabled and HC is enabled\n");
956 }
957 break;
958
959 case ASYNCLISTADDR:
960 if ((s->usbcmd & USBCMD_ASE) && (s->usbcmd & USBCMD_RUNSTOP)) {
961 fprintf(stderr,
962 "ehci: ASYNC list address register set while async schedule\n"
963 " is enabled and HC is enabled\n");
964 }
965 break;
966 }
967
968 *mmio = val;
969 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
970 }
971
972
973 // TODO : Put in common header file, duplication from usb-ohci.c
974
975 /* Get an array of dwords from main memory */
976 static inline int get_dwords(uint32_t addr, uint32_t *buf, int num)
977 {
978 int i;
979
980 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
981 cpu_physical_memory_rw(addr,(uint8_t *)buf, sizeof(*buf), 0);
982 *buf = le32_to_cpu(*buf);
983 }
984
985 return 1;
986 }
987
988 /* Put an array of dwords in to main memory */
989 static inline int put_dwords(uint32_t addr, uint32_t *buf, int num)
990 {
991 int i;
992
993 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
994 uint32_t tmp = cpu_to_le32(*buf);
995 cpu_physical_memory_rw(addr,(uint8_t *)&tmp, sizeof(tmp), 1);
996 }
997
998 return 1;
999 }
1000
1001 // 4.10.2
1002
1003 static int ehci_qh_do_overlay(EHCIQueue *q)
1004 {
1005 int i;
1006 int dtoggle;
1007 int ping;
1008 int eps;
1009 int reload;
1010
1011 // remember values in fields to preserve in qh after overlay
1012
1013 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE;
1014 ping = q->qh.token & QTD_TOKEN_PING;
1015
1016 q->qh.current_qtd = q->qtdaddr;
1017 q->qh.next_qtd = q->qtd.next;
1018 q->qh.altnext_qtd = q->qtd.altnext;
1019 q->qh.token = q->qtd.token;
1020
1021
1022 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS);
1023 if (eps == EHCI_QH_EPS_HIGH) {
1024 q->qh.token &= ~QTD_TOKEN_PING;
1025 q->qh.token |= ping;
1026 }
1027
1028 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1029 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1030
1031 for (i = 0; i < 5; i++) {
1032 q->qh.bufptr[i] = q->qtd.bufptr[i];
1033 }
1034
1035 if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
1036 // preserve QH DT bit
1037 q->qh.token &= ~QTD_TOKEN_DTOGGLE;
1038 q->qh.token |= dtoggle;
1039 }
1040
1041 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
1042 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
1043
1044 put_dwords(NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2);
1045
1046 return 0;
1047 }
1048
1049 static int ehci_buffer_rw(EHCIQueue *q, int bytes, int rw)
1050 {
1051 int bufpos = 0;
1052 int cpage, offset;
1053 uint32_t head;
1054 uint32_t tail;
1055
1056
1057 if (!bytes) {
1058 return 0;
1059 }
1060
1061 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1062 if (cpage > 4) {
1063 fprintf(stderr, "cpage out of range (%d)\n", cpage);
1064 return USB_RET_PROCERR;
1065 }
1066
1067 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1068
1069 do {
1070 /* start and end of this page */
1071 head = q->qh.bufptr[cpage] & QTD_BUFPTR_MASK;
1072 tail = head + ~QTD_BUFPTR_MASK + 1;
1073 /* add offset into page */
1074 head |= offset;
1075
1076 if (bytes <= (tail - head)) {
1077 tail = head + bytes;
1078 }
1079
1080 trace_usb_ehci_data(rw, cpage, offset, head, tail-head, bufpos);
1081 cpu_physical_memory_rw(head, q->buffer + bufpos, tail - head, rw);
1082
1083 bufpos += (tail - head);
1084 offset += (tail - head);
1085 bytes -= (tail - head);
1086
1087 if (bytes > 0) {
1088 cpage++;
1089 offset = 0;
1090 }
1091 } while (bytes > 0);
1092
1093 /* save cpage */
1094 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE);
1095
1096 /* save offset into cpage */
1097 q->qh.bufptr[0] &= QTD_BUFPTR_MASK;
1098 q->qh.bufptr[0] |= offset;
1099
1100 return 0;
1101 }
1102
1103 static void ehci_async_complete_packet(USBDevice *dev, USBPacket *packet)
1104 {
1105 EHCIQueue *q = container_of(packet, EHCIQueue, packet);
1106
1107 trace_usb_ehci_queue_action(q, "wakeup");
1108 assert(q->async == EHCI_ASYNC_INFLIGHT);
1109 q->async = EHCI_ASYNC_FINISHED;
1110 q->usb_status = packet->len;
1111 }
1112
1113 static void ehci_execute_complete(EHCIQueue *q)
1114 {
1115 int c_err, reload;
1116
1117 assert(q->async != EHCI_ASYNC_INFLIGHT);
1118 q->async = EHCI_ASYNC_NONE;
1119
1120 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1121 q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status);
1122
1123 if (q->usb_status < 0) {
1124 err:
1125 /* TO-DO: put this is in a function that can be invoked below as well */
1126 c_err = get_field(q->qh.token, QTD_TOKEN_CERR);
1127 c_err--;
1128 set_field(&q->qh.token, c_err, QTD_TOKEN_CERR);
1129
1130 switch(q->usb_status) {
1131 case USB_RET_NODEV:
1132 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR);
1133 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1134 break;
1135 case USB_RET_STALL:
1136 q->qh.token |= QTD_TOKEN_HALT;
1137 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1138 break;
1139 case USB_RET_NAK:
1140 /* 4.10.3 */
1141 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1142 if ((q->pid == USB_TOKEN_IN) && reload) {
1143 int nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1144 nakcnt--;
1145 set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1146 } else if (!reload) {
1147 return;
1148 }
1149 break;
1150 case USB_RET_BABBLE:
1151 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1152 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1153 break;
1154 default:
1155 /* should not be triggerable */
1156 fprintf(stderr, "USB invalid response %d to handle\n", q->usb_status);
1157 assert(0);
1158 break;
1159 }
1160 } else {
1161 // DPRINTF("Short packet condition\n");
1162 // TODO check 4.12 for splits
1163
1164 if ((q->usb_status > q->tbytes) && (q->pid == USB_TOKEN_IN)) {
1165 q->usb_status = USB_RET_BABBLE;
1166 goto err;
1167 }
1168
1169 if (q->tbytes && q->pid == USB_TOKEN_IN) {
1170 if (ehci_buffer_rw(q, q->usb_status, 1) != 0) {
1171 q->usb_status = USB_RET_PROCERR;
1172 return;
1173 }
1174 q->tbytes -= q->usb_status;
1175 } else {
1176 q->tbytes = 0;
1177 }
1178
1179 DPRINTF("updating tbytes to %d\n", q->tbytes);
1180 set_field(&q->qh.token, q->tbytes, QTD_TOKEN_TBYTES);
1181 }
1182
1183 q->qh.token ^= QTD_TOKEN_DTOGGLE;
1184 q->qh.token &= ~QTD_TOKEN_ACTIVE;
1185
1186 if ((q->usb_status >= 0) && (q->qh.token & QTD_TOKEN_IOC)) {
1187 ehci_record_interrupt(q->ehci, USBSTS_INT);
1188 }
1189 }
1190
1191 // 4.10.3
1192
1193 static int ehci_execute(EHCIQueue *q)
1194 {
1195 USBPort *port;
1196 USBDevice *dev;
1197 int ret;
1198 int i;
1199 int endp;
1200 int devadr;
1201
1202 if ( !(q->qh.token & QTD_TOKEN_ACTIVE)) {
1203 fprintf(stderr, "Attempting to execute inactive QH\n");
1204 return USB_RET_PROCERR;
1205 }
1206
1207 q->tbytes = (q->qh.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH;
1208 if (q->tbytes > BUFF_SIZE) {
1209 fprintf(stderr, "Request for more bytes than allowed\n");
1210 return USB_RET_PROCERR;
1211 }
1212
1213 q->pid = (q->qh.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
1214 switch(q->pid) {
1215 case 0: q->pid = USB_TOKEN_OUT; break;
1216 case 1: q->pid = USB_TOKEN_IN; break;
1217 case 2: q->pid = USB_TOKEN_SETUP; break;
1218 default: fprintf(stderr, "bad token\n"); break;
1219 }
1220
1221 if ((q->tbytes && q->pid != USB_TOKEN_IN) &&
1222 (ehci_buffer_rw(q, q->tbytes, 0) != 0)) {
1223 return USB_RET_PROCERR;
1224 }
1225
1226 endp = get_field(q->qh.epchar, QH_EPCHAR_EP);
1227 devadr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR);
1228
1229 ret = USB_RET_NODEV;
1230
1231 // TO-DO: associating device with ehci port
1232 for(i = 0; i < NB_PORTS; i++) {
1233 port = &q->ehci->ports[i];
1234 dev = port->dev;
1235
1236 // TODO sometime we will also need to check if we are the port owner
1237
1238 if (!(q->ehci->portsc[i] &(PORTSC_CONNECT))) {
1239 DPRINTF("Port %d, no exec, not connected(%08X)\n",
1240 i, q->ehci->portsc[i]);
1241 continue;
1242 }
1243
1244 q->packet.pid = q->pid;
1245 q->packet.devaddr = devadr;
1246 q->packet.devep = endp;
1247 q->packet.data = q->buffer;
1248 q->packet.len = q->tbytes;
1249
1250 ret = usb_handle_packet(dev, &q->packet);
1251
1252 DPRINTF("submit: qh %x next %x qtd %x pid %x len %d (total %d) endp %x ret %d\n",
1253 q->qhaddr, q->qh.next, q->qtdaddr, q->pid,
1254 q->packet.len, q->tbytes, endp, ret);
1255
1256 if (ret != USB_RET_NODEV) {
1257 break;
1258 }
1259 }
1260
1261 if (ret > BUFF_SIZE) {
1262 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1263 return USB_RET_PROCERR;
1264 }
1265
1266 return ret;
1267 }
1268
1269 /* 4.7.2
1270 */
1271
1272 static int ehci_process_itd(EHCIState *ehci,
1273 EHCIitd *itd)
1274 {
1275 USBPort *port;
1276 USBDevice *dev;
1277 int ret;
1278 uint32_t i, j, len, len1, len2, pid, dir, devaddr, endp;
1279 uint32_t pg, off, ptr1, ptr2, max, mult;
1280
1281 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1282 devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1283 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1284 max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1285 mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);
1286
1287 for(i = 0; i < 8; i++) {
1288 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1289 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1290 off = itd->transact[i] & ITD_XACT_OFFSET_MASK;
1291 ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK);
1292 ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK);
1293 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1294
1295 if (len > max * mult) {
1296 len = max * mult;
1297 }
1298
1299 if (len > BUFF_SIZE) {
1300 return USB_RET_PROCERR;
1301 }
1302
1303 if (off + len > 4096) {
1304 /* transfer crosses page border */
1305 len2 = off + len - 4096;
1306 len1 = len - len2;
1307 } else {
1308 len1 = len;
1309 len2 = 0;
1310 }
1311
1312 if (!dir) {
1313 pid = USB_TOKEN_OUT;
1314 trace_usb_ehci_data(0, pg, off, ptr1 + off, len1, 0);
1315 cpu_physical_memory_rw(ptr1 + off, &ehci->ibuffer[0], len1, 0);
1316 if (len2) {
1317 trace_usb_ehci_data(0, pg+1, 0, ptr2, len2, len1);
1318 cpu_physical_memory_rw(ptr2, &ehci->ibuffer[len1], len2, 0);
1319 }
1320 } else {
1321 pid = USB_TOKEN_IN;
1322 }
1323
1324 ret = USB_RET_NODEV;
1325
1326 for (j = 0; j < NB_PORTS; j++) {
1327 port = &ehci->ports[j];
1328 dev = port->dev;
1329
1330 // TODO sometime we will also need to check if we are the port owner
1331
1332 if (!(ehci->portsc[j] &(PORTSC_CONNECT))) {
1333 continue;
1334 }
1335
1336 ehci->ipacket.pid = pid;
1337 ehci->ipacket.devaddr = devaddr;
1338 ehci->ipacket.devep = endp;
1339 ehci->ipacket.data = ehci->ibuffer;
1340 ehci->ipacket.len = len;
1341
1342 ret = usb_handle_packet(dev, &ehci->ipacket);
1343
1344 if (ret != USB_RET_NODEV) {
1345 break;
1346 }
1347 }
1348
1349 #if 0
1350 /* In isoch, there is no facility to indicate a NAK so let's
1351 * instead just complete a zero-byte transaction. Setting
1352 * DBERR seems too draconian.
1353 */
1354
1355 if (ret == USB_RET_NAK) {
1356 if (ehci->isoch_pause > 0) {
1357 DPRINTF("ISOCH: received a NAK but paused so returning\n");
1358 ehci->isoch_pause--;
1359 return 0;
1360 } else if (ehci->isoch_pause == -1) {
1361 DPRINTF("ISOCH: recv NAK & isoch pause inactive, setting\n");
1362 // Pause frindex for up to 50 msec waiting for data from
1363 // remote
1364 ehci->isoch_pause = 50;
1365 return 0;
1366 } else {
1367 DPRINTF("ISOCH: isoch pause timeout! return 0\n");
1368 ret = 0;
1369 }
1370 } else {
1371 DPRINTF("ISOCH: received ACK, clearing pause\n");
1372 ehci->isoch_pause = -1;
1373 }
1374 #else
1375 if (ret == USB_RET_NAK) {
1376 ret = 0;
1377 }
1378 #endif
1379
1380 if (ret >= 0) {
1381 if (!dir) {
1382 /* OUT */
1383 set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH);
1384 } else {
1385 /* IN */
1386 if (len1 > ret) {
1387 len1 = ret;
1388 }
1389 if (len2 > ret - len1) {
1390 len2 = ret - len1;
1391 }
1392 if (len1) {
1393 trace_usb_ehci_data(1, pg, off, ptr1 + off, len1, 0);
1394 cpu_physical_memory_rw(ptr1 + off, &ehci->ibuffer[0], len1, 1);
1395 }
1396 if (len2) {
1397 trace_usb_ehci_data(1, pg+1, 0, ptr2, len2, len1);
1398 cpu_physical_memory_rw(ptr2, &ehci->ibuffer[len1], len2, 1);
1399 }
1400 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH);
1401 }
1402
1403 if (itd->transact[i] & ITD_XACT_IOC) {
1404 ehci_record_interrupt(ehci, USBSTS_INT);
1405 }
1406 }
1407 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1408 }
1409 }
1410 return 0;
1411 }
1412
1413 /* This state is the entry point for asynchronous schedule
1414 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1415 */
1416 static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1417 {
1418 EHCIqh qh;
1419 int i = 0;
1420 int again = 0;
1421 uint32_t entry = ehci->asynclistaddr;
1422
1423 /* set reclamation flag at start event (4.8.6) */
1424 if (async) {
1425 ehci_set_usbsts(ehci, USBSTS_REC);
1426 }
1427
1428 ehci_queues_rip_unused(ehci);
1429
1430 /* Find the head of the list (4.9.1.1) */
1431 for(i = 0; i < MAX_QH; i++) {
1432 get_dwords(NLPTR_GET(entry), (uint32_t *) &qh, sizeof(EHCIqh) >> 2);
1433 ehci_trace_qh(NULL, NLPTR_GET(entry), &qh);
1434
1435 if (qh.epchar & QH_EPCHAR_H) {
1436 if (async) {
1437 entry |= (NLPTR_TYPE_QH << 1);
1438 }
1439
1440 ehci_set_fetch_addr(ehci, async, entry);
1441 ehci_set_state(ehci, async, EST_FETCHENTRY);
1442 again = 1;
1443 goto out;
1444 }
1445
1446 entry = qh.next;
1447 if (entry == ehci->asynclistaddr) {
1448 break;
1449 }
1450 }
1451
1452 /* no head found for list. */
1453
1454 ehci_set_state(ehci, async, EST_ACTIVE);
1455
1456 out:
1457 return again;
1458 }
1459
1460
1461 /* This state is the entry point for periodic schedule processing as
1462 * well as being a continuation state for async processing.
1463 */
1464 static int ehci_state_fetchentry(EHCIState *ehci, int async)
1465 {
1466 int again = 0;
1467 uint32_t entry = ehci_get_fetch_addr(ehci, async);
1468
1469 if (entry < 0x1000) {
1470 DPRINTF("fetchentry: entry invalid (0x%08x)\n", entry);
1471 ehci_set_state(ehci, async, EST_ACTIVE);
1472 goto out;
1473 }
1474
1475 /* section 4.8, only QH in async schedule */
1476 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1477 fprintf(stderr, "non queue head request in async schedule\n");
1478 return -1;
1479 }
1480
1481 switch (NLPTR_TYPE_GET(entry)) {
1482 case NLPTR_TYPE_QH:
1483 ehci_set_state(ehci, async, EST_FETCHQH);
1484 again = 1;
1485 break;
1486
1487 case NLPTR_TYPE_ITD:
1488 ehci_set_state(ehci, async, EST_FETCHITD);
1489 again = 1;
1490 break;
1491
1492 default:
1493 // TODO: handle siTD and FSTN types
1494 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1495 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1496 return -1;
1497 }
1498
1499 out:
1500 return again;
1501 }
1502
1503 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)
1504 {
1505 uint32_t entry;
1506 EHCIQueue *q;
1507 int reload;
1508
1509 entry = ehci_get_fetch_addr(ehci, async);
1510 q = ehci_find_queue_by_qh(ehci, entry);
1511 if (NULL == q) {
1512 q = ehci_alloc_queue(ehci, async);
1513 }
1514 q->qhaddr = entry;
1515 q->seen++;
1516
1517 if (q->seen > 1) {
1518 /* we are going in circles -- stop processing */
1519 ehci_set_state(ehci, async, EST_ACTIVE);
1520 q = NULL;
1521 goto out;
1522 }
1523
1524 get_dwords(NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2);
1525 ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh);
1526
1527 if (q->async == EHCI_ASYNC_INFLIGHT) {
1528 /* I/O still in progress -- skip queue */
1529 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1530 goto out;
1531 }
1532 if (q->async == EHCI_ASYNC_FINISHED) {
1533 /* I/O finished -- continue processing queue */
1534 trace_usb_ehci_queue_action(q, "resume");
1535 ehci_set_state(ehci, async, EST_EXECUTING);
1536 goto out;
1537 }
1538
1539 if (async && (q->qh.epchar & QH_EPCHAR_H)) {
1540
1541 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1542 if (ehci->usbsts & USBSTS_REC) {
1543 ehci_clear_usbsts(ehci, USBSTS_REC);
1544 } else {
1545 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1546 " - done processing\n", q->qhaddr);
1547 ehci_set_state(ehci, async, EST_ACTIVE);
1548 q = NULL;
1549 goto out;
1550 }
1551 }
1552
1553 #if EHCI_DEBUG
1554 if (q->qhaddr != q->qh.next) {
1555 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1556 q->qhaddr,
1557 q->qh.epchar & QH_EPCHAR_H,
1558 q->qh.token & QTD_TOKEN_HALT,
1559 q->qh.token & QTD_TOKEN_ACTIVE,
1560 q->qh.next);
1561 }
1562 #endif
1563
1564 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1565 if (reload) {
1566 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1567 }
1568
1569 if (q->qh.token & QTD_TOKEN_HALT) {
1570 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1571
1572 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) && (q->qh.current_qtd > 0x1000)) {
1573 q->qtdaddr = q->qh.current_qtd;
1574 ehci_set_state(ehci, async, EST_FETCHQTD);
1575
1576 } else {
1577 /* EHCI spec version 1.0 Section 4.10.2 */
1578 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1579 }
1580
1581 out:
1582 return q;
1583 }
1584
1585 static int ehci_state_fetchitd(EHCIState *ehci, int async)
1586 {
1587 uint32_t entry;
1588 EHCIitd itd;
1589
1590 assert(!async);
1591 entry = ehci_get_fetch_addr(ehci, async);
1592
1593 get_dwords(NLPTR_GET(entry),(uint32_t *) &itd,
1594 sizeof(EHCIitd) >> 2);
1595 ehci_trace_itd(ehci, entry, &itd);
1596
1597 if (ehci_process_itd(ehci, &itd) != 0) {
1598 return -1;
1599 }
1600
1601 put_dwords(NLPTR_GET(entry), (uint32_t *) &itd,
1602 sizeof(EHCIitd) >> 2);
1603 ehci_set_fetch_addr(ehci, async, itd.next);
1604 ehci_set_state(ehci, async, EST_FETCHENTRY);
1605
1606 return 1;
1607 }
1608
1609 /* Section 4.10.2 - paragraph 3 */
1610 static int ehci_state_advqueue(EHCIQueue *q, int async)
1611 {
1612 #if 0
1613 /* TO-DO: 4.10.2 - paragraph 2
1614 * if I-bit is set to 1 and QH is not active
1615 * go to horizontal QH
1616 */
1617 if (I-bit set) {
1618 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1619 goto out;
1620 }
1621 #endif
1622
1623 /*
1624 * want data and alt-next qTD is valid
1625 */
1626 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1627 (q->qh.altnext_qtd > 0x1000) &&
1628 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
1629 q->qtdaddr = q->qh.altnext_qtd;
1630 ehci_set_state(q->ehci, async, EST_FETCHQTD);
1631
1632 /*
1633 * next qTD is valid
1634 */
1635 } else if ((q->qh.next_qtd > 0x1000) &&
1636 (NLPTR_TBIT(q->qh.next_qtd) == 0)) {
1637 q->qtdaddr = q->qh.next_qtd;
1638 ehci_set_state(q->ehci, async, EST_FETCHQTD);
1639
1640 /*
1641 * no valid qTD, try next QH
1642 */
1643 } else {
1644 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1645 }
1646
1647 return 1;
1648 }
1649
1650 /* Section 4.10.2 - paragraph 4 */
1651 static int ehci_state_fetchqtd(EHCIQueue *q, int async)
1652 {
1653 int again = 0;
1654
1655 get_dwords(NLPTR_GET(q->qtdaddr),(uint32_t *) &q->qtd, sizeof(EHCIqtd) >> 2);
1656 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &q->qtd);
1657
1658 if (q->qtd.token & QTD_TOKEN_ACTIVE) {
1659 ehci_set_state(q->ehci, async, EST_EXECUTE);
1660 again = 1;
1661 } else {
1662 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1663 again = 1;
1664 }
1665
1666 return again;
1667 }
1668
1669 static int ehci_state_horizqh(EHCIQueue *q, int async)
1670 {
1671 int again = 0;
1672
1673 if (ehci_get_fetch_addr(q->ehci, async) != q->qh.next) {
1674 ehci_set_fetch_addr(q->ehci, async, q->qh.next);
1675 ehci_set_state(q->ehci, async, EST_FETCHENTRY);
1676 again = 1;
1677 } else {
1678 ehci_set_state(q->ehci, async, EST_ACTIVE);
1679 }
1680
1681 return again;
1682 }
1683
1684 /*
1685 * Write the qh back to guest physical memory. This step isn't
1686 * in the EHCI spec but we need to do it since we don't share
1687 * physical memory with our guest VM.
1688 *
1689 * The first three dwords are read-only for the EHCI, so skip them
1690 * when writing back the qh.
1691 */
1692 static void ehci_flush_qh(EHCIQueue *q)
1693 {
1694 uint32_t *qh = (uint32_t *) &q->qh;
1695 uint32_t dwords = sizeof(EHCIqh) >> 2;
1696 uint32_t addr = NLPTR_GET(q->qhaddr);
1697
1698 put_dwords(addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3);
1699 }
1700
1701 static int ehci_state_execute(EHCIQueue *q, int async)
1702 {
1703 int again = 0;
1704 int reload, nakcnt;
1705 int smask;
1706
1707 if (ehci_qh_do_overlay(q) != 0) {
1708 return -1;
1709 }
1710
1711 smask = get_field(q->qh.epcap, QH_EPCAP_SMASK);
1712
1713 if (!smask) {
1714 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1715 nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1716 if (reload && !nakcnt) {
1717 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1718 again = 1;
1719 goto out;
1720 }
1721 }
1722
1723 // TODO verify enough time remains in the uframe as in 4.4.1.1
1724 // TODO write back ptr to async list when done or out of time
1725 // TODO Windows does not seem to ever set the MULT field
1726
1727 if (!async) {
1728 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1729 if (!transactCtr) {
1730 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1731 again = 1;
1732 goto out;
1733 }
1734 }
1735
1736 if (async) {
1737 ehci_set_usbsts(q->ehci, USBSTS_REC);
1738 }
1739
1740 q->usb_status = ehci_execute(q);
1741 if (q->usb_status == USB_RET_PROCERR) {
1742 again = -1;
1743 goto out;
1744 }
1745 if (q->usb_status == USB_RET_ASYNC) {
1746 ehci_flush_qh(q);
1747 trace_usb_ehci_queue_action(q, "suspend");
1748 q->async = EHCI_ASYNC_INFLIGHT;
1749 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1750 again = 1;
1751 goto out;
1752 }
1753
1754 ehci_set_state(q->ehci, async, EST_EXECUTING);
1755 again = 1;
1756
1757 out:
1758 return again;
1759 }
1760
1761 static int ehci_state_executing(EHCIQueue *q, int async)
1762 {
1763 int again = 0;
1764 int reload, nakcnt;
1765
1766 ehci_execute_complete(q);
1767 if (q->usb_status == USB_RET_ASYNC) {
1768 goto out;
1769 }
1770 if (q->usb_status == USB_RET_PROCERR) {
1771 again = -1;
1772 goto out;
1773 }
1774
1775 // 4.10.3
1776 if (!async) {
1777 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1778 transactCtr--;
1779 set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT);
1780 // 4.10.3, bottom of page 82, should exit this state when transaction
1781 // counter decrements to 0
1782 }
1783
1784 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1785 if (reload) {
1786 nakcnt = get_field(q->qh.altnext_qtd, QH_ALTNEXT_NAKCNT);
1787 if (q->usb_status == USB_RET_NAK) {
1788 if (nakcnt) {
1789 nakcnt--;
1790 }
1791 } else {
1792 nakcnt = reload;
1793 }
1794 set_field(&q->qh.altnext_qtd, nakcnt, QH_ALTNEXT_NAKCNT);
1795 }
1796
1797 /* 4.10.5 */
1798 if ((q->usb_status == USB_RET_NAK) || (q->qh.token & QTD_TOKEN_ACTIVE)) {
1799 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1800 } else {
1801 ehci_set_state(q->ehci, async, EST_WRITEBACK);
1802 }
1803
1804 again = 1;
1805
1806 out:
1807 ehci_flush_qh(q);
1808 return again;
1809 }
1810
1811
1812 static int ehci_state_writeback(EHCIQueue *q, int async)
1813 {
1814 int again = 0;
1815
1816 /* Write back the QTD from the QH area */
1817 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), (EHCIqtd*) &q->qh.next_qtd);
1818 put_dwords(NLPTR_GET(q->qtdaddr),(uint32_t *) &q->qh.next_qtd,
1819 sizeof(EHCIqtd) >> 2);
1820
1821 /*
1822 * EHCI specs say go horizontal here.
1823 *
1824 * We can also advance the queue here for performance reasons. We
1825 * need to take care to only take that shortcut in case we've
1826 * processed the qtd just written back without errors, i.e. halt
1827 * bit is clear.
1828 */
1829 if (q->qh.token & QTD_TOKEN_HALT) {
1830 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1831 again = 1;
1832 } else {
1833 ehci_set_state(q->ehci, async, EST_ADVANCEQUEUE);
1834 again = 1;
1835 }
1836 return again;
1837 }
1838
1839 /*
1840 * This is the state machine that is common to both async and periodic
1841 */
1842
1843 static void ehci_advance_state(EHCIState *ehci,
1844 int async)
1845 {
1846 EHCIQueue *q = NULL;
1847 int again;
1848 int iter = 0;
1849
1850 do {
1851 if (ehci_get_state(ehci, async) == EST_FETCHQH) {
1852 iter++;
1853 /* if we are roaming a lot of QH without executing a qTD
1854 * something is wrong with the linked list. TO-DO: why is
1855 * this hack needed?
1856 */
1857 assert(iter < MAX_ITERATIONS);
1858 #if 0
1859 if (iter > MAX_ITERATIONS) {
1860 DPRINTF("\n*** advance_state: bailing on MAX ITERATIONS***\n");
1861 ehci_set_state(ehci, async, EST_ACTIVE);
1862 break;
1863 }
1864 #endif
1865 }
1866 switch(ehci_get_state(ehci, async)) {
1867 case EST_WAITLISTHEAD:
1868 again = ehci_state_waitlisthead(ehci, async);
1869 break;
1870
1871 case EST_FETCHENTRY:
1872 again = ehci_state_fetchentry(ehci, async);
1873 break;
1874
1875 case EST_FETCHQH:
1876 q = ehci_state_fetchqh(ehci, async);
1877 again = q ? 1 : 0;
1878 break;
1879
1880 case EST_FETCHITD:
1881 again = ehci_state_fetchitd(ehci, async);
1882 break;
1883
1884 case EST_ADVANCEQUEUE:
1885 again = ehci_state_advqueue(q, async);
1886 break;
1887
1888 case EST_FETCHQTD:
1889 again = ehci_state_fetchqtd(q, async);
1890 break;
1891
1892 case EST_HORIZONTALQH:
1893 again = ehci_state_horizqh(q, async);
1894 break;
1895
1896 case EST_EXECUTE:
1897 iter = 0;
1898 again = ehci_state_execute(q, async);
1899 break;
1900
1901 case EST_EXECUTING:
1902 assert(q != NULL);
1903 again = ehci_state_executing(q, async);
1904 break;
1905
1906 case EST_WRITEBACK:
1907 again = ehci_state_writeback(q, async);
1908 break;
1909
1910 default:
1911 fprintf(stderr, "Bad state!\n");
1912 again = -1;
1913 assert(0);
1914 break;
1915 }
1916
1917 if (again < 0) {
1918 fprintf(stderr, "processing error - resetting ehci HC\n");
1919 ehci_reset(ehci);
1920 again = 0;
1921 assert(0);
1922 }
1923 }
1924 while (again);
1925
1926 ehci_commit_interrupt(ehci);
1927 }
1928
1929 static void ehci_advance_async_state(EHCIState *ehci)
1930 {
1931 int async = 1;
1932
1933 switch(ehci_get_state(ehci, async)) {
1934 case EST_INACTIVE:
1935 if (!(ehci->usbcmd & USBCMD_ASE)) {
1936 break;
1937 }
1938 ehci_set_usbsts(ehci, USBSTS_ASS);
1939 ehci_set_state(ehci, async, EST_ACTIVE);
1940 // No break, fall through to ACTIVE
1941
1942 case EST_ACTIVE:
1943 if ( !(ehci->usbcmd & USBCMD_ASE)) {
1944 ehci_clear_usbsts(ehci, USBSTS_ASS);
1945 ehci_set_state(ehci, async, EST_INACTIVE);
1946 break;
1947 }
1948
1949 /* If the doorbell is set, the guest wants to make a change to the
1950 * schedule. The host controller needs to release cached data.
1951 * (section 4.8.2)
1952 */
1953 if (ehci->usbcmd & USBCMD_IAAD) {
1954 DPRINTF("ASYNC: doorbell request acknowledged\n");
1955 ehci->usbcmd &= ~USBCMD_IAAD;
1956 ehci_set_interrupt(ehci, USBSTS_IAA);
1957 break;
1958 }
1959
1960 /* make sure guest has acknowledged */
1961 /* TO-DO: is this really needed? */
1962 if (ehci->usbsts & USBSTS_IAA) {
1963 DPRINTF("IAA status bit still set.\n");
1964 break;
1965 }
1966
1967 /* check that address register has been set */
1968 if (ehci->asynclistaddr == 0) {
1969 break;
1970 }
1971
1972 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
1973 ehci_advance_state(ehci, async);
1974 break;
1975
1976 default:
1977 /* this should only be due to a developer mistake */
1978 fprintf(stderr, "ehci: Bad asynchronous state %d. "
1979 "Resetting to active\n", ehci->astate);
1980 assert(0);
1981 }
1982 }
1983
1984 static void ehci_advance_periodic_state(EHCIState *ehci)
1985 {
1986 uint32_t entry;
1987 uint32_t list;
1988 int async = 0;
1989
1990 // 4.6
1991
1992 switch(ehci_get_state(ehci, async)) {
1993 case EST_INACTIVE:
1994 if ( !(ehci->frindex & 7) && (ehci->usbcmd & USBCMD_PSE)) {
1995 ehci_set_usbsts(ehci, USBSTS_PSS);
1996 ehci_set_state(ehci, async, EST_ACTIVE);
1997 // No break, fall through to ACTIVE
1998 } else
1999 break;
2000
2001 case EST_ACTIVE:
2002 if ( !(ehci->frindex & 7) && !(ehci->usbcmd & USBCMD_PSE)) {
2003 ehci_clear_usbsts(ehci, USBSTS_PSS);
2004 ehci_set_state(ehci, async, EST_INACTIVE);
2005 break;
2006 }
2007
2008 list = ehci->periodiclistbase & 0xfffff000;
2009 /* check that register has been set */
2010 if (list == 0) {
2011 break;
2012 }
2013 list |= ((ehci->frindex & 0x1ff8) >> 1);
2014
2015 cpu_physical_memory_rw(list, (uint8_t *) &entry, sizeof entry, 0);
2016 entry = le32_to_cpu(entry);
2017
2018 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2019 ehci->frindex / 8, list, entry);
2020 ehci_set_fetch_addr(ehci, async,entry);
2021 ehci_set_state(ehci, async, EST_FETCHENTRY);
2022 ehci_advance_state(ehci, async);
2023 break;
2024
2025 default:
2026 /* this should only be due to a developer mistake */
2027 fprintf(stderr, "ehci: Bad periodic state %d. "
2028 "Resetting to active\n", ehci->pstate);
2029 assert(0);
2030 }
2031 }
2032
2033 static void ehci_frame_timer(void *opaque)
2034 {
2035 EHCIState *ehci = opaque;
2036 int64_t expire_time, t_now;
2037 int usec_elapsed;
2038 int frames;
2039 int usec_now;
2040 int i;
2041 int skipped_frames = 0;
2042
2043
2044 t_now = qemu_get_clock_ns(vm_clock);
2045 expire_time = t_now + (get_ticks_per_sec() / FRAME_TIMER_FREQ);
2046 if (expire_time == t_now) {
2047 expire_time++;
2048 }
2049
2050 usec_now = t_now / 1000;
2051 usec_elapsed = usec_now - ehci->last_run_usec;
2052 frames = usec_elapsed / FRAME_TIMER_USEC;
2053 ehci->frame_end_usec = usec_now + FRAME_TIMER_USEC - 10;
2054
2055 for (i = 0; i < frames; i++) {
2056 if ( !(ehci->usbsts & USBSTS_HALT)) {
2057 if (ehci->isoch_pause <= 0) {
2058 ehci->frindex += 8;
2059 }
2060
2061 if (ehci->frindex > 0x00001fff) {
2062 ehci->frindex = 0;
2063 ehci_set_interrupt(ehci, USBSTS_FLR);
2064 }
2065
2066 ehci->sofv = (ehci->frindex - 1) >> 3;
2067 ehci->sofv &= 0x000003ff;
2068 }
2069
2070 if (frames - i > 10) {
2071 skipped_frames++;
2072 } else {
2073 ehci_advance_periodic_state(ehci);
2074 }
2075
2076 ehci->last_run_usec += FRAME_TIMER_USEC;
2077 }
2078
2079 #if 0
2080 if (skipped_frames) {
2081 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
2082 }
2083 #endif
2084
2085 /* Async is not inside loop since it executes everything it can once
2086 * called
2087 */
2088 ehci_advance_async_state(ehci);
2089
2090 qemu_mod_timer(ehci->frame_timer, expire_time);
2091 }
2092
2093 static CPUReadMemoryFunc *ehci_readfn[3]={
2094 ehci_mem_readb,
2095 ehci_mem_readw,
2096 ehci_mem_readl
2097 };
2098
2099 static CPUWriteMemoryFunc *ehci_writefn[3]={
2100 ehci_mem_writeb,
2101 ehci_mem_writew,
2102 ehci_mem_writel
2103 };
2104
2105 static void ehci_map(PCIDevice *pci_dev, int region_num,
2106 pcibus_t addr, pcibus_t size, int type)
2107 {
2108 EHCIState *s =(EHCIState *)pci_dev;
2109
2110 DPRINTF("ehci_map: region %d, addr %08" PRIx64 ", size %" PRId64 ", s->mem %08X\n",
2111 region_num, addr, size, s->mem);
2112 s->mem_base = addr;
2113 cpu_register_physical_memory(addr, size, s->mem);
2114 }
2115
2116 static void ehci_device_destroy(USBBus *bus, USBDevice *dev)
2117 {
2118 EHCIState *s = container_of(bus, EHCIState, bus);
2119
2120 ehci_queues_rip_device(s, dev);
2121 }
2122
2123 static int usb_ehci_initfn(PCIDevice *dev);
2124
2125 static USBPortOps ehci_port_ops = {
2126 .attach = ehci_attach,
2127 .detach = ehci_detach,
2128 .complete = ehci_async_complete_packet,
2129 };
2130
2131 static USBBusOps ehci_bus_ops = {
2132 .device_destroy = ehci_device_destroy,
2133 };
2134
2135 static PCIDeviceInfo ehci_info = {
2136 .qdev.name = "usb-ehci",
2137 .qdev.size = sizeof(EHCIState),
2138 .init = usb_ehci_initfn,
2139 };
2140
2141 static int usb_ehci_initfn(PCIDevice *dev)
2142 {
2143 EHCIState *s = DO_UPCAST(EHCIState, dev, dev);
2144 uint8_t *pci_conf = s->dev.config;
2145 int i;
2146
2147 pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
2148 pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82801D);
2149 pci_set_byte(&pci_conf[PCI_REVISION_ID], 0x10);
2150 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
2151 pci_config_set_class(pci_conf, PCI_CLASS_SERIAL_USB);
2152 pci_set_byte(&pci_conf[PCI_HEADER_TYPE], PCI_HEADER_TYPE_NORMAL);
2153
2154 /* capabilities pointer */
2155 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
2156 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2157
2158 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); // interrupt pin 3
2159 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
2160 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
2161
2162 // pci_conf[0x50] = 0x01; // power management caps
2163
2164 pci_set_byte(&pci_conf[0x60], 0x20); // spec release number (2.1.4)
2165 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5)
2166 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6)
2167
2168 pci_conf[0x64] = 0x00;
2169 pci_conf[0x65] = 0x00;
2170 pci_conf[0x66] = 0x00;
2171 pci_conf[0x67] = 0x00;
2172 pci_conf[0x68] = 0x01;
2173 pci_conf[0x69] = 0x00;
2174 pci_conf[0x6a] = 0x00;
2175 pci_conf[0x6b] = 0x00; // USBLEGSUP
2176 pci_conf[0x6c] = 0x00;
2177 pci_conf[0x6d] = 0x00;
2178 pci_conf[0x6e] = 0x00;
2179 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS
2180
2181 // 2.2 host controller interface version
2182 s->mmio[0x00] = (uint8_t) OPREGBASE;
2183 s->mmio[0x01] = 0x00;
2184 s->mmio[0x02] = 0x00;
2185 s->mmio[0x03] = 0x01; // HC version
2186 s->mmio[0x04] = NB_PORTS; // Number of downstream ports
2187 s->mmio[0x05] = 0x00; // No companion ports at present
2188 s->mmio[0x06] = 0x00;
2189 s->mmio[0x07] = 0x00;
2190 s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2191 s->mmio[0x09] = 0x68; // EECP
2192 s->mmio[0x0a] = 0x00;
2193 s->mmio[0x0b] = 0x00;
2194
2195 s->irq = s->dev.irq[3];
2196
2197 usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev);
2198 for(i = 0; i < NB_PORTS; i++) {
2199 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2200 USB_SPEED_MASK_HIGH);
2201 usb_port_location(&s->ports[i], NULL, i+1);
2202 s->ports[i].dev = 0;
2203 }
2204
2205 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2206 QTAILQ_INIT(&s->queues);
2207
2208 qemu_register_reset(ehci_reset, s);
2209
2210 s->mem = cpu_register_io_memory(ehci_readfn, ehci_writefn, s,
2211 DEVICE_LITTLE_ENDIAN);
2212
2213 pci_register_bar(&s->dev, 0, MMIO_SIZE, PCI_BASE_ADDRESS_SPACE_MEMORY,
2214 ehci_map);
2215
2216 fprintf(stderr, "*** EHCI support is under development ***\n");
2217
2218 return 0;
2219 }
2220
2221 static void ehci_register(void)
2222 {
2223 pci_qdev_register(&ehci_info);
2224 }
2225 device_init(ehci_register);
2226
2227 /*
2228 * vim: expandtab ts=4
2229 */
Qemu copy for testing