2 * QEMU USB OHCI Emulation
3 * Copyright (c) 2004 Gianni Tedesco
4 * Copyright (c) 2006 CodeSourcery
5 * Copyright (c) 2006 Openedhand Ltd.
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 * o Isochronous transfers
23 * o Allocate bandwidth in frames properly
24 * o Disable timers when nothing needs to be done, or remove timer usage
26 * o Handle unrecoverable errors properly
27 * o BIOS work to boot from USB storage
33 /* Dump packet contents. */
34 //#define DEBUG_PACKET
35 /* This causes frames to occur 1000x slower */
36 //#define OHCI_TIME_WARP 1
39 #define dprintf printf
44 /* Number of Downstream Ports on the root hub. */
46 #define OHCI_MAX_PORTS 15
48 static int64_t usb_frame_time
;
49 static int64_t usb_bit_time
;
51 typedef struct OHCIPort
{
64 target_phys_addr_t mem_base
;
73 /* Control partition */
78 /* memory pointer partition */
80 uint32_t ctrl_head
, ctrl_cur
;
81 uint32_t bulk_head
, bulk_cur
;
86 /* Frame counter partition */
91 uint16_t frame_number
;
96 /* Root Hub partition */
97 uint32_t rhdesc_a
, rhdesc_b
;
99 OHCIPort rhport
[OHCI_MAX_PORTS
];
101 /* PXA27x Non-OHCI events */
107 /* Active packets. */
109 USBPacket usb_packet
;
110 uint8_t usb_buf
[8192];
116 /* Host Controller Communications Area */
123 /* Bitfields for the first word of an Endpoint Desciptor. */
124 #define OHCI_ED_FA_SHIFT 0
125 #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT)
126 #define OHCI_ED_EN_SHIFT 7
127 #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT)
128 #define OHCI_ED_D_SHIFT 11
129 #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT)
130 #define OHCI_ED_S (1<<13)
131 #define OHCI_ED_K (1<<14)
132 #define OHCI_ED_F (1<<15)
133 #define OHCI_ED_MPS_SHIFT 7
134 #define OHCI_ED_MPS_MASK (0xf<<OHCI_ED_FA_SHIFT)
136 /* Flags in the head field of an Endpoint Desciptor. */
140 /* Bitfields for the first word of a Transfer Desciptor. */
141 #define OHCI_TD_R (1<<18)
142 #define OHCI_TD_DP_SHIFT 19
143 #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT)
144 #define OHCI_TD_DI_SHIFT 21
145 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT)
146 #define OHCI_TD_T0 (1<<24)
147 #define OHCI_TD_T1 (1<<24)
148 #define OHCI_TD_EC_SHIFT 26
149 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT)
150 #define OHCI_TD_CC_SHIFT 28
151 #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT)
153 #define OHCI_DPTR_MASK 0xfffffff0
155 #define OHCI_BM(val, field) \
156 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
158 #define OHCI_SET_BM(val, field, newval) do { \
159 val &= ~OHCI_##field##_MASK; \
160 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
163 /* endpoint descriptor */
171 /* General transfer descriptor */
179 #define USB_HZ 12000000
181 /* OHCI Local stuff */
182 #define OHCI_CTL_CBSR ((1<<0)|(1<<1))
183 #define OHCI_CTL_PLE (1<<2)
184 #define OHCI_CTL_IE (1<<3)
185 #define OHCI_CTL_CLE (1<<4)
186 #define OHCI_CTL_BLE (1<<5)
187 #define OHCI_CTL_HCFS ((1<<6)|(1<<7))
188 #define OHCI_USB_RESET 0x00
189 #define OHCI_USB_RESUME 0x40
190 #define OHCI_USB_OPERATIONAL 0x80
191 #define OHCI_USB_SUSPEND 0xc0
192 #define OHCI_CTL_IR (1<<8)
193 #define OHCI_CTL_RWC (1<<9)
194 #define OHCI_CTL_RWE (1<<10)
196 #define OHCI_STATUS_HCR (1<<0)
197 #define OHCI_STATUS_CLF (1<<1)
198 #define OHCI_STATUS_BLF (1<<2)
199 #define OHCI_STATUS_OCR (1<<3)
200 #define OHCI_STATUS_SOC ((1<<6)|(1<<7))
202 #define OHCI_INTR_SO (1<<0) /* Scheduling overrun */
203 #define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */
204 #define OHCI_INTR_SF (1<<2) /* Start of frame */
205 #define OHCI_INTR_RD (1<<3) /* Resume detect */
206 #define OHCI_INTR_UE (1<<4) /* Unrecoverable error */
207 #define OHCI_INTR_FNO (1<<5) /* Frame number overflow */
208 #define OHCI_INTR_RHSC (1<<6) /* Root hub status change */
209 #define OHCI_INTR_OC (1<<30) /* Ownership change */
210 #define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */
212 #define OHCI_HCCA_SIZE 0x100
213 #define OHCI_HCCA_MASK 0xffffff00
215 #define OHCI_EDPTR_MASK 0xfffffff0
217 #define OHCI_FMI_FI 0x00003fff
218 #define OHCI_FMI_FSMPS 0xffff0000
219 #define OHCI_FMI_FIT 0x80000000
221 #define OHCI_FR_RT (1<<31)
223 #define OHCI_LS_THRESH 0x628
225 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */
226 #define OHCI_RHA_PSM (1<<8)
227 #define OHCI_RHA_NPS (1<<9)
228 #define OHCI_RHA_DT (1<<10)
229 #define OHCI_RHA_OCPM (1<<11)
230 #define OHCI_RHA_NOCP (1<<12)
231 #define OHCI_RHA_POTPGT_MASK 0xff000000
233 #define OHCI_RHS_LPS (1<<0)
234 #define OHCI_RHS_OCI (1<<1)
235 #define OHCI_RHS_DRWE (1<<15)
236 #define OHCI_RHS_LPSC (1<<16)
237 #define OHCI_RHS_OCIC (1<<17)
238 #define OHCI_RHS_CRWE (1<<31)
240 #define OHCI_PORT_CCS (1<<0)
241 #define OHCI_PORT_PES (1<<1)
242 #define OHCI_PORT_PSS (1<<2)
243 #define OHCI_PORT_POCI (1<<3)
244 #define OHCI_PORT_PRS (1<<4)
245 #define OHCI_PORT_PPS (1<<8)
246 #define OHCI_PORT_LSDA (1<<9)
247 #define OHCI_PORT_CSC (1<<16)
248 #define OHCI_PORT_PESC (1<<17)
249 #define OHCI_PORT_PSSC (1<<18)
250 #define OHCI_PORT_OCIC (1<<19)
251 #define OHCI_PORT_PRSC (1<<20)
252 #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
253 |OHCI_PORT_OCIC|OHCI_PORT_PRSC)
255 #define OHCI_TD_DIR_SETUP 0x0
256 #define OHCI_TD_DIR_OUT 0x1
257 #define OHCI_TD_DIR_IN 0x2
258 #define OHCI_TD_DIR_RESERVED 0x3
260 #define OHCI_CC_NOERROR 0x0
261 #define OHCI_CC_CRC 0x1
262 #define OHCI_CC_BITSTUFFING 0x2
263 #define OHCI_CC_DATATOGGLEMISMATCH 0x3
264 #define OHCI_CC_STALL 0x4
265 #define OHCI_CC_DEVICENOTRESPONDING 0x5
266 #define OHCI_CC_PIDCHECKFAILURE 0x6
267 #define OHCI_CC_UNDEXPETEDPID 0x7
268 #define OHCI_CC_DATAOVERRUN 0x8
269 #define OHCI_CC_DATAUNDERRUN 0x9
270 #define OHCI_CC_BUFFEROVERRUN 0xc
271 #define OHCI_CC_BUFFERUNDERRUN 0xd
273 #define OHCI_HRESET_FSBIR (1 << 0)
275 /* Update IRQ levels */
276 static inline void ohci_intr_update(OHCIState
*ohci
)
280 if ((ohci
->intr
& OHCI_INTR_MIE
) &&
281 (ohci
->intr_status
& ohci
->intr
))
284 qemu_set_irq(ohci
->irq
, level
);
287 /* Set an interrupt */
288 static inline void ohci_set_interrupt(OHCIState
*ohci
, uint32_t intr
)
290 ohci
->intr_status
|= intr
;
291 ohci_intr_update(ohci
);
294 /* Attach or detach a device on a root hub port. */
295 static void ohci_attach(USBPort
*port1
, USBDevice
*dev
)
297 OHCIState
*s
= port1
->opaque
;
298 OHCIPort
*port
= &s
->rhport
[port1
->index
];
299 uint32_t old_state
= port
->ctrl
;
302 if (port
->port
.dev
) {
303 usb_attach(port1
, NULL
);
305 /* set connect status */
306 port
->ctrl
|= OHCI_PORT_CCS
| OHCI_PORT_CSC
;
309 if (dev
->speed
== USB_SPEED_LOW
)
310 port
->ctrl
|= OHCI_PORT_LSDA
;
312 port
->ctrl
&= ~OHCI_PORT_LSDA
;
313 port
->port
.dev
= dev
;
315 /* notify of remote-wakeup */
316 if ((s
->ctl
& OHCI_CTL_HCFS
) == OHCI_USB_SUSPEND
)
317 ohci_set_interrupt(s
, OHCI_INTR_RD
);
319 /* send the attach message */
320 usb_send_msg(dev
, USB_MSG_ATTACH
);
321 dprintf("usb-ohci: Attached port %d\n", port1
->index
);
323 /* set connect status */
324 if (port
->ctrl
& OHCI_PORT_CCS
) {
325 port
->ctrl
&= ~OHCI_PORT_CCS
;
326 port
->ctrl
|= OHCI_PORT_CSC
;
329 if (port
->ctrl
& OHCI_PORT_PES
) {
330 port
->ctrl
&= ~OHCI_PORT_PES
;
331 port
->ctrl
|= OHCI_PORT_PESC
;
333 dev
= port
->port
.dev
;
335 /* send the detach message */
336 usb_send_msg(dev
, USB_MSG_DETACH
);
338 port
->port
.dev
= NULL
;
339 dprintf("usb-ohci: Detached port %d\n", port1
->index
);
342 if (old_state
!= port
->ctrl
)
343 ohci_set_interrupt(s
, OHCI_INTR_RHSC
);
346 /* Reset the controller */
347 static void ohci_reset(OHCIState
*ohci
)
355 ohci
->intr_status
= 0;
356 ohci
->intr
= OHCI_INTR_MIE
;
359 ohci
->ctrl_head
= ohci
->ctrl_cur
= 0;
360 ohci
->bulk_head
= ohci
->bulk_cur
= 0;
363 ohci
->done_count
= 7;
365 /* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
366 * I took the value linux sets ...
368 ohci
->fsmps
= 0x2778;
372 ohci
->frame_number
= 0;
374 ohci
->lst
= OHCI_LS_THRESH
;
376 ohci
->rhdesc_a
= OHCI_RHA_NPS
| ohci
->num_ports
;
377 ohci
->rhdesc_b
= 0x0; /* Impl. specific */
380 for (i
= 0; i
< ohci
->num_ports
; i
++)
382 port
= &ohci
->rhport
[i
];
385 ohci_attach(&port
->port
, port
->port
.dev
);
387 if (ohci
->async_td
) {
388 usb_cancel_packet(&ohci
->usb_packet
);
391 dprintf("usb-ohci: Reset %s\n", ohci
->name
);
394 /* Get an array of dwords from main memory */
395 static inline int get_dwords(uint32_t addr
, uint32_t *buf
, int num
)
399 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
400 cpu_physical_memory_rw(addr
, (uint8_t *)buf
, sizeof(*buf
), 0);
401 *buf
= le32_to_cpu(*buf
);
407 /* Put an array of dwords in to main memory */
408 static inline int put_dwords(uint32_t addr
, uint32_t *buf
, int num
)
412 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
413 uint32_t tmp
= cpu_to_le32(*buf
);
414 cpu_physical_memory_rw(addr
, (uint8_t *)&tmp
, sizeof(tmp
), 1);
420 static inline int ohci_read_ed(uint32_t addr
, struct ohci_ed
*ed
)
422 return get_dwords(addr
, (uint32_t *)ed
, sizeof(*ed
) >> 2);
425 static inline int ohci_read_td(uint32_t addr
, struct ohci_td
*td
)
427 return get_dwords(addr
, (uint32_t *)td
, sizeof(*td
) >> 2);
430 static inline int ohci_put_ed(uint32_t addr
, struct ohci_ed
*ed
)
432 return put_dwords(addr
, (uint32_t *)ed
, sizeof(*ed
) >> 2);
435 static inline int ohci_put_td(uint32_t addr
, struct ohci_td
*td
)
437 return put_dwords(addr
, (uint32_t *)td
, sizeof(*td
) >> 2);
440 /* Read/Write the contents of a TD from/to main memory. */
441 static void ohci_copy_td(struct ohci_td
*td
, uint8_t *buf
, int len
, int write
)
447 n
= 0x1000 - (ptr
& 0xfff);
450 cpu_physical_memory_rw(ptr
, buf
, n
, write
);
453 ptr
= td
->be
& ~0xfffu
;
455 cpu_physical_memory_rw(ptr
, buf
, len
- n
, write
);
458 static void ohci_process_lists(OHCIState
*ohci
);
460 static void ohci_async_complete_packet(USBPacket
* packet
, void *opaque
)
462 OHCIState
*ohci
= opaque
;
464 dprintf("Async packet complete\n");
466 ohci
->async_complete
= 1;
467 ohci_process_lists(ohci
);
470 /* Service a transport descriptor.
471 Returns nonzero to terminate processing of this endpoint. */
473 static int ohci_service_td(OHCIState
*ohci
, struct ohci_ed
*ed
)
487 addr
= ed
->head
& OHCI_DPTR_MASK
;
488 /* See if this TD has already been submitted to the device. */
489 completion
= (addr
== ohci
->async_td
);
490 if (completion
&& !ohci
->async_complete
) {
492 dprintf("Skipping async TD\n");
496 if (!ohci_read_td(addr
, &td
)) {
497 fprintf(stderr
, "usb-ohci: TD read error at %x\n", addr
);
501 dir
= OHCI_BM(ed
->flags
, ED_D
);
503 case OHCI_TD_DIR_OUT
:
508 dir
= OHCI_BM(td
.flags
, TD_DP
);
517 case OHCI_TD_DIR_OUT
:
521 case OHCI_TD_DIR_SETUP
:
523 pid
= USB_TOKEN_SETUP
;
526 fprintf(stderr
, "usb-ohci: Bad direction\n");
529 if (td
.cbp
&& td
.be
) {
530 if ((td
.cbp
& 0xfffff000) != (td
.be
& 0xfffff000)) {
531 len
= (td
.be
& 0xfff) + 0x1001 - (td
.cbp
& 0xfff);
533 len
= (td
.be
- td
.cbp
) + 1;
536 if (len
&& dir
!= OHCI_TD_DIR_IN
&& !completion
) {
537 ohci_copy_td(&td
, ohci
->usb_buf
, len
, 0);
541 flag_r
= (td
.flags
& OHCI_TD_R
) != 0;
543 dprintf(" TD @ 0x%.8x %u bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
544 addr
, len
, str
, flag_r
, td
.cbp
, td
.be
);
546 if (len
>= 0 && dir
!= OHCI_TD_DIR_IN
) {
548 for (i
= 0; i
< len
; i
++)
549 printf(" %.2x", ohci
->usb_buf
[i
]);
554 ret
= ohci
->usb_packet
.len
;
556 ohci
->async_complete
= 0;
559 for (i
= 0; i
< ohci
->num_ports
; i
++) {
560 dev
= ohci
->rhport
[i
].port
.dev
;
561 if ((ohci
->rhport
[i
].ctrl
& OHCI_PORT_PES
) == 0)
564 if (ohci
->async_td
) {
565 /* ??? The hardware should allow one active packet per
566 endpoint. We only allow one active packet per controller.
567 This should be sufficient as long as devices respond in a
571 dprintf("Too many pending packets\n");
575 ohci
->usb_packet
.pid
= pid
;
576 ohci
->usb_packet
.devaddr
= OHCI_BM(ed
->flags
, ED_FA
);
577 ohci
->usb_packet
.devep
= OHCI_BM(ed
->flags
, ED_EN
);
578 ohci
->usb_packet
.data
= ohci
->usb_buf
;
579 ohci
->usb_packet
.len
= len
;
580 ohci
->usb_packet
.complete_cb
= ohci_async_complete_packet
;
581 ohci
->usb_packet
.complete_opaque
= ohci
;
582 ret
= dev
->handle_packet(dev
, &ohci
->usb_packet
);
583 if (ret
!= USB_RET_NODEV
)
587 dprintf("ret=%d\n", ret
);
589 if (ret
== USB_RET_ASYNC
) {
590 ohci
->async_td
= addr
;
595 if (dir
== OHCI_TD_DIR_IN
) {
596 ohci_copy_td(&td
, ohci
->usb_buf
, ret
, 1);
599 for (i
= 0; i
< ret
; i
++)
600 printf(" %.2x", ohci
->usb_buf
[i
]);
609 if (ret
== len
|| (dir
== OHCI_TD_DIR_IN
&& ret
>= 0 && flag_r
)) {
610 /* Transmission succeeded. */
615 if ((td
.cbp
& 0xfff) + ret
> 0xfff) {
617 td
.cbp
|= td
.be
& ~0xfff;
620 td
.flags
|= OHCI_TD_T1
;
621 td
.flags
^= OHCI_TD_T0
;
622 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_NOERROR
);
623 OHCI_SET_BM(td
.flags
, TD_EC
, 0);
625 ed
->head
&= ~OHCI_ED_C
;
626 if (td
.flags
& OHCI_TD_T0
)
627 ed
->head
|= OHCI_ED_C
;
630 dprintf("usb-ohci: Underrun\n");
631 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DATAUNDERRUN
);
635 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DEVICENOTRESPONDING
);
637 dprintf("usb-ohci: got NAK\n");
640 dprintf("usb-ohci: got STALL\n");
641 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_STALL
);
644 dprintf("usb-ohci: got BABBLE\n");
645 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DATAOVERRUN
);
648 fprintf(stderr
, "usb-ohci: Bad device response %d\n", ret
);
649 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_UNDEXPETEDPID
);
650 OHCI_SET_BM(td
.flags
, TD_EC
, 3);
654 ed
->head
|= OHCI_ED_H
;
658 ed
->head
&= ~OHCI_DPTR_MASK
;
659 ed
->head
|= td
.next
& OHCI_DPTR_MASK
;
660 td
.next
= ohci
->done
;
662 i
= OHCI_BM(td
.flags
, TD_DI
);
663 if (i
< ohci
->done_count
)
664 ohci
->done_count
= i
;
665 ohci_put_td(addr
, &td
);
666 return OHCI_BM(td
.flags
, TD_CC
) != OHCI_CC_NOERROR
;
669 /* Service an endpoint list. Returns nonzero if active TD were found. */
670 static int ohci_service_ed_list(OHCIState
*ohci
, uint32_t head
)
682 for (cur
= head
; cur
; cur
= next_ed
) {
683 if (!ohci_read_ed(cur
, &ed
)) {
684 fprintf(stderr
, "usb-ohci: ED read error at %x\n", cur
);
688 next_ed
= ed
.next
& OHCI_DPTR_MASK
;
690 if ((ed
.head
& OHCI_ED_H
) || (ed
.flags
& OHCI_ED_K
)) {
692 /* Cancel pending packets for ED that have been paused. */
693 addr
= ed
.head
& OHCI_DPTR_MASK
;
694 if (ohci
->async_td
&& addr
== ohci
->async_td
) {
695 usb_cancel_packet(&ohci
->usb_packet
);
701 /* Skip isochronous endpoints. */
702 if (ed
.flags
& OHCI_ED_F
)
705 while ((ed
.head
& OHCI_DPTR_MASK
) != ed
.tail
) {
707 dprintf("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
708 "h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur
,
709 OHCI_BM(ed
.flags
, ED_FA
), OHCI_BM(ed
.flags
, ED_EN
),
710 OHCI_BM(ed
.flags
, ED_D
), (ed
.flags
& OHCI_ED_S
)!= 0,
711 (ed
.flags
& OHCI_ED_K
) != 0, (ed
.flags
& OHCI_ED_F
) != 0,
712 OHCI_BM(ed
.flags
, ED_MPS
), (ed
.head
& OHCI_ED_H
) != 0,
713 (ed
.head
& OHCI_ED_C
) != 0, ed
.head
& OHCI_DPTR_MASK
,
714 ed
.tail
& OHCI_DPTR_MASK
, ed
.next
& OHCI_DPTR_MASK
);
718 if (ohci_service_td(ohci
, &ed
))
722 ohci_put_ed(cur
, &ed
);
728 /* Generate a SOF event, and set a timer for EOF */
729 static void ohci_sof(OHCIState
*ohci
)
731 ohci
->sof_time
= qemu_get_clock(vm_clock
);
732 qemu_mod_timer(ohci
->eof_timer
, ohci
->sof_time
+ usb_frame_time
);
733 ohci_set_interrupt(ohci
, OHCI_INTR_SF
);
736 /* Process Control and Bulk lists. */
737 static void ohci_process_lists(OHCIState
*ohci
)
739 if ((ohci
->ctl
& OHCI_CTL_CLE
) && (ohci
->status
& OHCI_STATUS_CLF
)) {
740 if (ohci
->ctrl_cur
&& ohci
->ctrl_cur
!= ohci
->ctrl_head
)
741 dprintf("usb-ohci: head %x, cur %x\n", ohci
->ctrl_head
, ohci
->ctrl_cur
);
742 if (!ohci_service_ed_list(ohci
, ohci
->ctrl_head
)) {
744 ohci
->status
&= ~OHCI_STATUS_CLF
;
748 if ((ohci
->ctl
& OHCI_CTL_BLE
) && (ohci
->status
& OHCI_STATUS_BLF
)) {
749 if (!ohci_service_ed_list(ohci
, ohci
->bulk_head
)) {
751 ohci
->status
&= ~OHCI_STATUS_BLF
;
756 /* Do frame processing on frame boundary */
757 static void ohci_frame_boundary(void *opaque
)
759 OHCIState
*ohci
= opaque
;
760 struct ohci_hcca hcca
;
762 cpu_physical_memory_rw(ohci
->hcca
, (uint8_t *)&hcca
, sizeof(hcca
), 0);
764 /* Process all the lists at the end of the frame */
765 if (ohci
->ctl
& OHCI_CTL_PLE
) {
768 n
= ohci
->frame_number
& 0x1f;
769 ohci_service_ed_list(ohci
, le32_to_cpu(hcca
.intr
[n
]));
772 /* Cancel all pending packets if either of the lists has been disabled. */
773 if (ohci
->async_td
&&
774 ohci
->old_ctl
& (~ohci
->ctl
) & (OHCI_CTL_BLE
| OHCI_CTL_CLE
)) {
775 usb_cancel_packet(&ohci
->usb_packet
);
778 ohci
->old_ctl
= ohci
->ctl
;
779 ohci_process_lists(ohci
);
781 /* Frame boundary, so do EOF stuf here */
782 ohci
->frt
= ohci
->fit
;
784 /* XXX: endianness */
785 ohci
->frame_number
= (ohci
->frame_number
+ 1) & 0xffff;
786 hcca
.frame
= cpu_to_le32(ohci
->frame_number
);
788 if (ohci
->done_count
== 0 && !(ohci
->intr_status
& OHCI_INTR_WD
)) {
791 if (ohci
->intr
& ohci
->intr_status
)
793 hcca
.done
= cpu_to_le32(ohci
->done
);
795 ohci
->done_count
= 7;
796 ohci_set_interrupt(ohci
, OHCI_INTR_WD
);
799 if (ohci
->done_count
!= 7 && ohci
->done_count
!= 0)
802 /* Do SOF stuff here */
806 cpu_physical_memory_rw(ohci
->hcca
, (uint8_t *)&hcca
, sizeof(hcca
), 1);
809 /* Start sending SOF tokens across the USB bus, lists are processed in
812 static int ohci_bus_start(OHCIState
*ohci
)
814 ohci
->eof_timer
= qemu_new_timer(vm_clock
,
818 if (ohci
->eof_timer
== NULL
) {
819 fprintf(stderr
, "usb-ohci: %s: qemu_new_timer failed\n", ohci
->name
);
820 /* TODO: Signal unrecoverable error */
824 dprintf("usb-ohci: %s: USB Operational\n", ohci
->name
);
831 /* Stop sending SOF tokens on the bus */
832 static void ohci_bus_stop(OHCIState
*ohci
)
835 qemu_del_timer(ohci
->eof_timer
);
838 /* Sets a flag in a port status register but only set it if the port is
839 * connected, if not set ConnectStatusChange flag. If flag is enabled
842 static int ohci_port_set_if_connected(OHCIState
*ohci
, int i
, uint32_t val
)
846 /* writing a 0 has no effect */
850 /* If CurrentConnectStatus is cleared we set
851 * ConnectStatusChange
853 if (!(ohci
->rhport
[i
].ctrl
& OHCI_PORT_CCS
)) {
854 ohci
->rhport
[i
].ctrl
|= OHCI_PORT_CSC
;
855 if (ohci
->rhstatus
& OHCI_RHS_DRWE
) {
856 /* TODO: CSC is a wakeup event */
861 if (ohci
->rhport
[i
].ctrl
& val
)
865 ohci
->rhport
[i
].ctrl
|= val
;
870 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */
871 static void ohci_set_frame_interval(OHCIState
*ohci
, uint16_t val
)
875 if (val
!= ohci
->fi
) {
876 dprintf("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
877 ohci
->name
, ohci
->fi
, ohci
->fi
);
883 static void ohci_port_power(OHCIState
*ohci
, int i
, int p
)
886 ohci
->rhport
[i
].ctrl
|= OHCI_PORT_PPS
;
888 ohci
->rhport
[i
].ctrl
&= ~(OHCI_PORT_PPS
|
895 /* Set HcControlRegister */
896 static void ohci_set_ctl(OHCIState
*ohci
, uint32_t val
)
901 old_state
= ohci
->ctl
& OHCI_CTL_HCFS
;
903 new_state
= ohci
->ctl
& OHCI_CTL_HCFS
;
905 /* no state change */
906 if (old_state
== new_state
)
910 case OHCI_USB_OPERATIONAL
:
911 ohci_bus_start(ohci
);
913 case OHCI_USB_SUSPEND
:
915 dprintf("usb-ohci: %s: USB Suspended\n", ohci
->name
);
917 case OHCI_USB_RESUME
:
918 dprintf("usb-ohci: %s: USB Resume\n", ohci
->name
);
921 dprintf("usb-ohci: %s: USB Reset\n", ohci
->name
);
926 static uint32_t ohci_get_frame_remaining(OHCIState
*ohci
)
931 if ((ohci
->ctl
& OHCI_CTL_HCFS
) != OHCI_USB_OPERATIONAL
)
932 return (ohci
->frt
<< 31);
934 /* Being in USB operational state guarnatees sof_time was
937 tks
= qemu_get_clock(vm_clock
) - ohci
->sof_time
;
939 /* avoid muldiv if possible */
940 if (tks
>= usb_frame_time
)
941 return (ohci
->frt
<< 31);
943 tks
= muldiv64(1, tks
, usb_bit_time
);
944 fr
= (uint16_t)(ohci
->fi
- tks
);
946 return (ohci
->frt
<< 31) | fr
;
950 /* Set root hub status */
951 static void ohci_set_hub_status(OHCIState
*ohci
, uint32_t val
)
955 old_state
= ohci
->rhstatus
;
957 /* write 1 to clear OCIC */
958 if (val
& OHCI_RHS_OCIC
)
959 ohci
->rhstatus
&= ~OHCI_RHS_OCIC
;
961 if (val
& OHCI_RHS_LPS
) {
964 for (i
= 0; i
< ohci
->num_ports
; i
++)
965 ohci_port_power(ohci
, i
, 0);
966 dprintf("usb-ohci: powered down all ports\n");
969 if (val
& OHCI_RHS_LPSC
) {
972 for (i
= 0; i
< ohci
->num_ports
; i
++)
973 ohci_port_power(ohci
, i
, 1);
974 dprintf("usb-ohci: powered up all ports\n");
977 if (val
& OHCI_RHS_DRWE
)
978 ohci
->rhstatus
|= OHCI_RHS_DRWE
;
980 if (val
& OHCI_RHS_CRWE
)
981 ohci
->rhstatus
&= ~OHCI_RHS_DRWE
;
983 if (old_state
!= ohci
->rhstatus
)
984 ohci_set_interrupt(ohci
, OHCI_INTR_RHSC
);
987 /* Set root hub port status */
988 static void ohci_port_set_status(OHCIState
*ohci
, int portnum
, uint32_t val
)
993 port
= &ohci
->rhport
[portnum
];
994 old_state
= port
->ctrl
;
996 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
997 if (val
& OHCI_PORT_WTC
)
998 port
->ctrl
&= ~(val
& OHCI_PORT_WTC
);
1000 if (val
& OHCI_PORT_CCS
)
1001 port
->ctrl
&= ~OHCI_PORT_PES
;
1003 ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PES
);
1005 if (ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PSS
))
1006 dprintf("usb-ohci: port %d: SUSPEND\n", portnum
);
1008 if (ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PRS
)) {
1009 dprintf("usb-ohci: port %d: RESET\n", portnum
);
1010 usb_send_msg(port
->port
.dev
, USB_MSG_RESET
);
1011 port
->ctrl
&= ~OHCI_PORT_PRS
;
1012 /* ??? Should this also set OHCI_PORT_PESC. */
1013 port
->ctrl
|= OHCI_PORT_PES
| OHCI_PORT_PRSC
;
1016 /* Invert order here to ensure in ambiguous case, device is
1019 if (val
& OHCI_PORT_LSDA
)
1020 ohci_port_power(ohci
, portnum
, 0);
1021 if (val
& OHCI_PORT_PPS
)
1022 ohci_port_power(ohci
, portnum
, 1);
1024 if (old_state
!= port
->ctrl
)
1025 ohci_set_interrupt(ohci
, OHCI_INTR_RHSC
);
1030 static uint32_t ohci_mem_read(void *ptr
, target_phys_addr_t addr
)
1032 OHCIState
*ohci
= ptr
;
1034 addr
-= ohci
->mem_base
;
1036 /* Only aligned reads are allowed on OHCI */
1038 fprintf(stderr
, "usb-ohci: Mis-aligned read\n");
1042 if (addr
>= 0x54 && addr
< 0x54 + ohci
->num_ports
* 4) {
1043 /* HcRhPortStatus */
1044 return ohci
->rhport
[(addr
- 0x54) >> 2].ctrl
| OHCI_PORT_PPS
;
1047 switch (addr
>> 2) {
1048 case 0: /* HcRevision */
1051 case 1: /* HcControl */
1054 case 2: /* HcCommandStatus */
1055 return ohci
->status
;
1057 case 3: /* HcInterruptStatus */
1058 return ohci
->intr_status
;
1060 case 4: /* HcInterruptEnable */
1061 case 5: /* HcInterruptDisable */
1064 case 6: /* HcHCCA */
1067 case 7: /* HcPeriodCurrentED */
1068 return ohci
->per_cur
;
1070 case 8: /* HcControlHeadED */
1071 return ohci
->ctrl_head
;
1073 case 9: /* HcControlCurrentED */
1074 return ohci
->ctrl_cur
;
1076 case 10: /* HcBulkHeadED */
1077 return ohci
->bulk_head
;
1079 case 11: /* HcBulkCurrentED */
1080 return ohci
->bulk_cur
;
1082 case 12: /* HcDoneHead */
1085 case 13: /* HcFmInterval */
1086 return (ohci
->fit
<< 31) | (ohci
->fsmps
<< 16) | (ohci
->fi
);
1088 case 14: /* HcFmRemaining */
1089 return ohci_get_frame_remaining(ohci
);
1091 case 15: /* HcFmNumber */
1092 return ohci
->frame_number
;
1094 case 16: /* HcPeriodicStart */
1095 return ohci
->pstart
;
1097 case 17: /* HcLSThreshold */
1100 case 18: /* HcRhDescriptorA */
1101 return ohci
->rhdesc_a
;
1103 case 19: /* HcRhDescriptorB */
1104 return ohci
->rhdesc_b
;
1106 case 20: /* HcRhStatus */
1107 return ohci
->rhstatus
;
1109 /* PXA27x specific registers */
1110 case 24: /* HcStatus */
1111 return ohci
->hstatus
& ohci
->hmask
;
1113 case 25: /* HcHReset */
1114 return ohci
->hreset
;
1116 case 26: /* HcHInterruptEnable */
1119 case 27: /* HcHInterruptTest */
1123 fprintf(stderr
, "ohci_read: Bad offset %x\n", (int)addr
);
1128 static void ohci_mem_write(void *ptr
, target_phys_addr_t addr
, uint32_t val
)
1130 OHCIState
*ohci
= ptr
;
1132 addr
-= ohci
->mem_base
;
1134 /* Only aligned reads are allowed on OHCI */
1136 fprintf(stderr
, "usb-ohci: Mis-aligned write\n");
1140 if (addr
>= 0x54 && addr
< 0x54 + ohci
->num_ports
* 4) {
1141 /* HcRhPortStatus */
1142 ohci_port_set_status(ohci
, (addr
- 0x54) >> 2, val
);
1146 switch (addr
>> 2) {
1147 case 1: /* HcControl */
1148 ohci_set_ctl(ohci
, val
);
1151 case 2: /* HcCommandStatus */
1152 /* SOC is read-only */
1153 val
= (val
& ~OHCI_STATUS_SOC
);
1155 /* Bits written as '0' remain unchanged in the register */
1156 ohci
->status
|= val
;
1158 if (ohci
->status
& OHCI_STATUS_HCR
)
1162 case 3: /* HcInterruptStatus */
1163 ohci
->intr_status
&= ~val
;
1164 ohci_intr_update(ohci
);
1167 case 4: /* HcInterruptEnable */
1169 ohci_intr_update(ohci
);
1172 case 5: /* HcInterruptDisable */
1174 ohci_intr_update(ohci
);
1177 case 6: /* HcHCCA */
1178 ohci
->hcca
= val
& OHCI_HCCA_MASK
;
1181 case 8: /* HcControlHeadED */
1182 ohci
->ctrl_head
= val
& OHCI_EDPTR_MASK
;
1185 case 9: /* HcControlCurrentED */
1186 ohci
->ctrl_cur
= val
& OHCI_EDPTR_MASK
;
1189 case 10: /* HcBulkHeadED */
1190 ohci
->bulk_head
= val
& OHCI_EDPTR_MASK
;
1193 case 11: /* HcBulkCurrentED */
1194 ohci
->bulk_cur
= val
& OHCI_EDPTR_MASK
;
1197 case 13: /* HcFmInterval */
1198 ohci
->fsmps
= (val
& OHCI_FMI_FSMPS
) >> 16;
1199 ohci
->fit
= (val
& OHCI_FMI_FIT
) >> 31;
1200 ohci_set_frame_interval(ohci
, val
);
1203 case 16: /* HcPeriodicStart */
1204 ohci
->pstart
= val
& 0xffff;
1207 case 17: /* HcLSThreshold */
1208 ohci
->lst
= val
& 0xffff;
1211 case 18: /* HcRhDescriptorA */
1212 ohci
->rhdesc_a
&= ~OHCI_RHA_RW_MASK
;
1213 ohci
->rhdesc_a
|= val
& OHCI_RHA_RW_MASK
;
1216 case 19: /* HcRhDescriptorB */
1219 case 20: /* HcRhStatus */
1220 ohci_set_hub_status(ohci
, val
);
1223 /* PXA27x specific registers */
1224 case 24: /* HcStatus */
1225 ohci
->hstatus
&= ~(val
& ohci
->hmask
);
1227 case 25: /* HcHReset */
1228 ohci
->hreset
= val
& ~OHCI_HRESET_FSBIR
;
1229 if (val
& OHCI_HRESET_FSBIR
)
1233 case 26: /* HcHInterruptEnable */
1237 case 27: /* HcHInterruptTest */
1242 fprintf(stderr
, "ohci_write: Bad offset %x\n", (int)addr
);
1247 /* Only dword reads are defined on OHCI register space */
1248 static CPUReadMemoryFunc
*ohci_readfn
[3]={
1254 /* Only dword writes are defined on OHCI register space */
1255 static CPUWriteMemoryFunc
*ohci_writefn
[3]={
1261 static void usb_ohci_init(OHCIState
*ohci
, int num_ports
, int devfn
,
1262 qemu_irq irq
, enum ohci_type type
, const char *name
)
1266 if (usb_frame_time
== 0) {
1268 usb_frame_time
= ticks_per_sec
;
1269 usb_bit_time
= muldiv64(1, ticks_per_sec
, USB_HZ
/1000);
1271 usb_frame_time
= muldiv64(1, ticks_per_sec
, 1000);
1272 if (ticks_per_sec
>= USB_HZ
) {
1273 usb_bit_time
= muldiv64(1, ticks_per_sec
, USB_HZ
);
1278 dprintf("usb-ohci: usb_bit_time=%lli usb_frame_time=%lli\n",
1279 usb_frame_time
, usb_bit_time
);
1282 ohci
->mem
= cpu_register_io_memory(0, ohci_readfn
, ohci_writefn
, ohci
);
1288 ohci
->num_ports
= num_ports
;
1289 for (i
= 0; i
< num_ports
; i
++) {
1290 qemu_register_usb_port(&ohci
->rhport
[i
].port
, ohci
, i
, ohci_attach
);
1302 static void ohci_mapfunc(PCIDevice
*pci_dev
, int i
,
1303 uint32_t addr
, uint32_t size
, int type
)
1305 OHCIPCIState
*ohci
= (OHCIPCIState
*)pci_dev
;
1306 ohci
->state
.mem_base
= addr
;
1307 cpu_register_physical_memory(addr
, size
, ohci
->state
.mem
);
1310 void usb_ohci_init_pci(struct PCIBus
*bus
, int num_ports
, int devfn
)
1316 ohci
= (OHCIPCIState
*)pci_register_device(bus
, "OHCI USB", sizeof(*ohci
),
1319 fprintf(stderr
, "usb-ohci: Failed to register PCI device\n");
1323 ohci
->pci_dev
.config
[0x00] = vid
& 0xff;
1324 ohci
->pci_dev
.config
[0x01] = (vid
>> 8) & 0xff;
1325 ohci
->pci_dev
.config
[0x02] = did
& 0xff;
1326 ohci
->pci_dev
.config
[0x03] = (did
>> 8) & 0xff;
1327 ohci
->pci_dev
.config
[0x09] = 0x10; /* OHCI */
1328 ohci
->pci_dev
.config
[0x0a] = 0x3;
1329 ohci
->pci_dev
.config
[0x0b] = 0xc;
1330 ohci
->pci_dev
.config
[0x3d] = 0x01; /* interrupt pin 1 */
1332 usb_ohci_init(&ohci
->state
, num_ports
, devfn
, ohci
->pci_dev
.irq
[0],
1333 OHCI_TYPE_PCI
, ohci
->pci_dev
.name
);
1335 pci_register_io_region((struct PCIDevice
*)ohci
, 0, 256,
1336 PCI_ADDRESS_SPACE_MEM
, ohci_mapfunc
);
1339 void usb_ohci_init_pxa(target_phys_addr_t base
, int num_ports
, int devfn
,
1342 OHCIState
*ohci
= (OHCIState
*)qemu_mallocz(sizeof(OHCIState
));
1344 usb_ohci_init(ohci
, num_ports
, devfn
, irq
,
1345 OHCI_TYPE_PXA
, "OHCI USB");
1346 ohci
->mem_base
= base
;
1348 cpu_register_physical_memory(ohci
->mem_base
, 0x1000, ohci
->mem
);