2 * QEMU USB OHCI Emulation
3 * Copyright (c) 2004 Gianni Tedesco
4 * Copyright (c) 2006 CodeSourcery
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 * o Isochronous transfers
22 * o Allocate bandwidth in frames properly
23 * o Disable timers when nothing needs to be done, or remove timer usage
25 * o Handle unrecoverable errors properly
26 * o BIOS work to boot from USB storage
32 /* Dump packet contents. */
33 //#define DEBUG_PACKET
34 /* This causes frames to occur 1000x slower */
35 //#define OHCI_TIME_WARP 1
38 #define dprintf printf
43 /* Number of Downstream Ports on the root hub. */
45 #define OHCI_MAX_PORTS 15
47 static int64_t usb_frame_time
;
48 static int64_t usb_bit_time
;
50 typedef struct OHCIPort
{
56 struct PCIDevice pci_dev
;
57 target_phys_addr_t mem_base
;
65 /* Control partition */
70 /* memory pointer partition */
72 uint32_t ctrl_head
, ctrl_cur
;
73 uint32_t bulk_head
, bulk_cur
;
78 /* Frame counter partition */
83 uint16_t frame_number
;
88 /* Root Hub partition */
89 uint32_t rhdesc_a
, rhdesc_b
;
91 OHCIPort rhport
[OHCI_MAX_PORTS
];
94 /* Host Controller Communications Area */
101 /* Bitfields for the first word of an Endpoint Desciptor. */
102 #define OHCI_ED_FA_SHIFT 0
103 #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT)
104 #define OHCI_ED_EN_SHIFT 7
105 #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT)
106 #define OHCI_ED_D_SHIFT 11
107 #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT)
108 #define OHCI_ED_S (1<<13)
109 #define OHCI_ED_K (1<<14)
110 #define OHCI_ED_F (1<<15)
111 #define OHCI_ED_MPS_SHIFT 7
112 #define OHCI_ED_MPS_MASK (0xf<<OHCI_ED_FA_SHIFT)
114 /* Flags in the head field of an Endpoint Desciptor. */
118 /* Bitfields for the first word of a Transfer Desciptor. */
119 #define OHCI_TD_R (1<<18)
120 #define OHCI_TD_DP_SHIFT 19
121 #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT)
122 #define OHCI_TD_DI_SHIFT 21
123 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT)
124 #define OHCI_TD_T0 (1<<24)
125 #define OHCI_TD_T1 (1<<24)
126 #define OHCI_TD_EC_SHIFT 26
127 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT)
128 #define OHCI_TD_CC_SHIFT 28
129 #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT)
131 #define OHCI_DPTR_MASK 0xfffffff0
133 #define OHCI_BM(val, field) \
134 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT)
136 #define OHCI_SET_BM(val, field, newval) do { \
137 val &= ~OHCI_##field##_MASK; \
138 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \
141 /* endpoint descriptor */
149 /* General transfer descriptor */
157 #define USB_HZ 12000000
159 /* OHCI Local stuff */
160 #define OHCI_CTL_CBSR ((1<<0)|(1<<1))
161 #define OHCI_CTL_PLE (1<<2)
162 #define OHCI_CTL_IE (1<<3)
163 #define OHCI_CTL_CLE (1<<4)
164 #define OHCI_CTL_BLE (1<<5)
165 #define OHCI_CTL_HCFS ((1<<6)|(1<<7))
166 #define OHCI_USB_RESET 0x00
167 #define OHCI_USB_RESUME 0x40
168 #define OHCI_USB_OPERATIONAL 0x80
169 #define OHCI_USB_SUSPEND 0xc0
170 #define OHCI_CTL_IR (1<<8)
171 #define OHCI_CTL_RWC (1<<9)
172 #define OHCI_CTL_RWE (1<<10)
174 #define OHCI_STATUS_HCR (1<<0)
175 #define OHCI_STATUS_CLF (1<<1)
176 #define OHCI_STATUS_BLF (1<<2)
177 #define OHCI_STATUS_OCR (1<<3)
178 #define OHCI_STATUS_SOC ((1<<6)|(1<<7))
180 #define OHCI_INTR_SO (1<<0) /* Scheduling overrun */
181 #define OHCI_INTR_WD (1<<1) /* HcDoneHead writeback */
182 #define OHCI_INTR_SF (1<<2) /* Start of frame */
183 #define OHCI_INTR_RD (1<<3) /* Resume detect */
184 #define OHCI_INTR_UE (1<<4) /* Unrecoverable error */
185 #define OHCI_INTR_FNO (1<<5) /* Frame number overflow */
186 #define OHCI_INTR_RHSC (1<<6) /* Root hub status change */
187 #define OHCI_INTR_OC (1<<30) /* Ownership change */
188 #define OHCI_INTR_MIE (1<<31) /* Master Interrupt Enable */
190 #define OHCI_HCCA_SIZE 0x100
191 #define OHCI_HCCA_MASK 0xffffff00
193 #define OHCI_EDPTR_MASK 0xfffffff0
195 #define OHCI_FMI_FI 0x00003fff
196 #define OHCI_FMI_FSMPS 0xffff0000
197 #define OHCI_FMI_FIT 0x80000000
199 #define OHCI_FR_RT (1<<31)
201 #define OHCI_LS_THRESH 0x628
203 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */
204 #define OHCI_RHA_PSM (1<<8)
205 #define OHCI_RHA_NPS (1<<9)
206 #define OHCI_RHA_DT (1<<10)
207 #define OHCI_RHA_OCPM (1<<11)
208 #define OHCI_RHA_NOCP (1<<12)
209 #define OHCI_RHA_POTPGT_MASK 0xff000000
211 #define OHCI_RHS_LPS (1<<0)
212 #define OHCI_RHS_OCI (1<<1)
213 #define OHCI_RHS_DRWE (1<<15)
214 #define OHCI_RHS_LPSC (1<<16)
215 #define OHCI_RHS_OCIC (1<<17)
216 #define OHCI_RHS_CRWE (1<<31)
218 #define OHCI_PORT_CCS (1<<0)
219 #define OHCI_PORT_PES (1<<1)
220 #define OHCI_PORT_PSS (1<<2)
221 #define OHCI_PORT_POCI (1<<3)
222 #define OHCI_PORT_PRS (1<<4)
223 #define OHCI_PORT_PPS (1<<8)
224 #define OHCI_PORT_LSDA (1<<9)
225 #define OHCI_PORT_CSC (1<<16)
226 #define OHCI_PORT_PESC (1<<17)
227 #define OHCI_PORT_PSSC (1<<18)
228 #define OHCI_PORT_OCIC (1<<19)
229 #define OHCI_PORT_PRSC (1<<20)
230 #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \
231 |OHCI_PORT_OCIC|OHCI_PORT_PRSC)
233 #define OHCI_TD_DIR_SETUP 0x0
234 #define OHCI_TD_DIR_OUT 0x1
235 #define OHCI_TD_DIR_IN 0x2
236 #define OHCI_TD_DIR_RESERVED 0x3
238 #define OHCI_CC_NOERROR 0x0
239 #define OHCI_CC_CRC 0x1
240 #define OHCI_CC_BITSTUFFING 0x2
241 #define OHCI_CC_DATATOGGLEMISMATCH 0x3
242 #define OHCI_CC_STALL 0x4
243 #define OHCI_CC_DEVICENOTRESPONDING 0x5
244 #define OHCI_CC_PIDCHECKFAILURE 0x6
245 #define OHCI_CC_UNDEXPETEDPID 0x7
246 #define OHCI_CC_DATAOVERRUN 0x8
247 #define OHCI_CC_DATAUNDERRUN 0x9
248 #define OHCI_CC_BUFFEROVERRUN 0xc
249 #define OHCI_CC_BUFFERUNDERRUN 0xd
251 /* Update IRQ levels */
252 static inline void ohci_intr_update(OHCIState
*ohci
)
256 if ((ohci
->intr
& OHCI_INTR_MIE
) &&
257 (ohci
->intr_status
& ohci
->intr
))
260 pci_set_irq(&ohci
->pci_dev
, 0, level
);
263 /* Set an interrupt */
264 static inline void ohci_set_interrupt(OHCIState
*ohci
, uint32_t intr
)
266 ohci
->intr_status
|= intr
;
267 ohci_intr_update(ohci
);
270 /* Attach or detach a device on a root hub port. */
271 static void ohci_attach(USBPort
*port1
, USBDevice
*dev
)
273 OHCIState
*s
= port1
->opaque
;
274 OHCIPort
*port
= &s
->rhport
[port1
->index
];
275 uint32_t old_state
= port
->ctrl
;
278 if (port
->port
.dev
) {
279 usb_attach(port1
, NULL
);
281 /* set connect status */
282 port
->ctrl
|= OHCI_PORT_CCS
| OHCI_PORT_CSC
;
285 if (dev
->speed
== USB_SPEED_LOW
)
286 port
->ctrl
|= OHCI_PORT_LSDA
;
288 port
->ctrl
&= ~OHCI_PORT_LSDA
;
289 port
->port
.dev
= dev
;
290 /* send the attach message */
291 dev
->handle_packet(dev
,
292 USB_MSG_ATTACH
, 0, 0, NULL
, 0);
293 dprintf("usb-ohci: Attached port %d\n", port1
->index
);
295 /* set connect status */
296 if (port
->ctrl
& OHCI_PORT_CCS
) {
297 port
->ctrl
&= ~OHCI_PORT_CCS
;
298 port
->ctrl
|= OHCI_PORT_CSC
;
301 if (port
->ctrl
& OHCI_PORT_PES
) {
302 port
->ctrl
&= ~OHCI_PORT_PES
;
303 port
->ctrl
|= OHCI_PORT_PESC
;
305 dev
= port
->port
.dev
;
307 /* send the detach message */
308 dev
->handle_packet(dev
,
309 USB_MSG_DETACH
, 0, 0, NULL
, 0);
311 port
->port
.dev
= NULL
;
312 dprintf("usb-ohci: Detached port %d\n", port1
->index
);
315 if (old_state
!= port
->ctrl
)
316 ohci_set_interrupt(s
, OHCI_INTR_RHSC
);
319 /* Reset the controller */
320 static void ohci_reset(OHCIState
*ohci
)
327 ohci
->intr_status
= 0;
328 ohci
->intr
= OHCI_INTR_MIE
;
331 ohci
->ctrl_head
= ohci
->ctrl_cur
= 0;
332 ohci
->bulk_head
= ohci
->bulk_cur
= 0;
335 ohci
->done_count
= 7;
337 /* FSMPS is marked TBD in OCHI 1.0, what gives ffs?
338 * I took the value linux sets ...
340 ohci
->fsmps
= 0x2778;
344 ohci
->frame_number
= 0;
346 ohci
->lst
= OHCI_LS_THRESH
;
348 ohci
->rhdesc_a
= OHCI_RHA_NPS
| ohci
->num_ports
;
349 ohci
->rhdesc_b
= 0x0; /* Impl. specific */
352 for (i
= 0; i
< ohci
->num_ports
; i
++)
354 port
= &ohci
->rhport
[i
];
357 ohci_attach(&port
->port
, port
->port
.dev
);
359 dprintf("usb-ohci: Reset %s\n", ohci
->pci_dev
.name
);
362 /* Get an array of dwords from main memory */
363 static inline int get_dwords(uint32_t addr
, uint32_t *buf
, int num
)
367 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
368 cpu_physical_memory_rw(addr
, (uint8_t *)buf
, sizeof(*buf
), 0);
369 *buf
= le32_to_cpu(*buf
);
375 /* Put an array of dwords in to main memory */
376 static inline int put_dwords(uint32_t addr
, uint32_t *buf
, int num
)
380 for (i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
381 uint32_t tmp
= cpu_to_le32(*buf
);
382 cpu_physical_memory_rw(addr
, (uint8_t *)&tmp
, sizeof(tmp
), 1);
388 static inline int ohci_read_ed(uint32_t addr
, struct ohci_ed
*ed
)
390 return get_dwords(addr
, (uint32_t *)ed
, sizeof(*ed
) >> 2);
393 static inline int ohci_read_td(uint32_t addr
, struct ohci_td
*td
)
395 return get_dwords(addr
, (uint32_t *)td
, sizeof(*td
) >> 2);
398 static inline int ohci_put_ed(uint32_t addr
, struct ohci_ed
*ed
)
400 return put_dwords(addr
, (uint32_t *)ed
, sizeof(*ed
) >> 2);
403 static inline int ohci_put_td(uint32_t addr
, struct ohci_td
*td
)
405 return put_dwords(addr
, (uint32_t *)td
, sizeof(*td
) >> 2);
408 /* Read/Write the contents of a TD from/to main memory. */
409 static void ohci_copy_td(struct ohci_td
*td
, uint8_t *buf
, int len
, int write
)
415 n
= 0x1000 - (ptr
& 0xfff);
418 cpu_physical_memory_rw(ptr
, buf
, n
, write
);
421 ptr
= td
->be
& ~0xfffu
;
422 cpu_physical_memory_rw(ptr
, buf
, len
- n
, write
);
425 /* Service a transport descriptor.
426 Returns nonzero to terminate processing of this endpoint. */
428 static int ohci_service_td(OHCIState
*ohci
, struct ohci_ed
*ed
)
442 addr
= ed
->head
& OHCI_DPTR_MASK
;
443 if (!ohci_read_td(addr
, &td
)) {
444 fprintf(stderr
, "usb-ohci: TD read error at %x\n", addr
);
448 dir
= OHCI_BM(ed
->flags
, ED_D
);
450 case OHCI_TD_DIR_OUT
:
455 dir
= OHCI_BM(td
.flags
, TD_DP
);
464 case OHCI_TD_DIR_OUT
:
468 case OHCI_TD_DIR_SETUP
:
470 pid
= USB_TOKEN_SETUP
;
473 fprintf(stderr
, "usb-ohci: Bad direction\n");
476 if (td
.cbp
&& td
.be
) {
477 len
= (td
.be
- td
.cbp
) + 1;
478 if (len
&& dir
!= OHCI_TD_DIR_IN
) {
479 ohci_copy_td(&td
, buf
, len
, 0);
483 flag_r
= (td
.flags
& OHCI_TD_R
) != 0;
485 dprintf(" TD @ 0x%.8x %u bytes %s r=%d cbp=0x%.8x be=0x%.8x\n",
486 addr
, len
, str
, flag_r
, td
.cbp
, td
.be
);
488 if (len
>= 0 && dir
!= OHCI_TD_DIR_IN
) {
490 for (i
= 0; i
< len
; i
++)
491 printf(" %.2x", buf
[i
]);
496 for (i
= 0; i
< ohci
->num_ports
; i
++) {
497 dev
= ohci
->rhport
[i
].port
.dev
;
498 if ((ohci
->rhport
[i
].ctrl
& OHCI_PORT_PES
) == 0)
501 ret
= dev
->handle_packet(dev
, pid
, OHCI_BM(ed
->flags
, ED_FA
),
502 OHCI_BM(ed
->flags
, ED_EN
), buf
, len
);
503 if (ret
!= USB_RET_NODEV
)
507 dprintf("ret=%d\n", ret
);
510 if (dir
== OHCI_TD_DIR_IN
) {
511 ohci_copy_td(&td
, buf
, ret
, 1);
514 for (i
= 0; i
< ret
; i
++)
515 printf(" %.2x", buf
[i
]);
524 if (ret
== len
|| (dir
== OHCI_TD_DIR_IN
&& ret
>= 0 && flag_r
)) {
525 /* Transmission succeeded. */
530 if ((td
.cbp
& 0xfff) + ret
> 0xfff) {
532 td
.cbp
|= td
.be
& ~0xfff;
535 td
.flags
|= OHCI_TD_T1
;
536 td
.flags
^= OHCI_TD_T0
;
537 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_NOERROR
);
538 OHCI_SET_BM(td
.flags
, TD_EC
, 0);
540 ed
->head
&= ~OHCI_ED_C
;
541 if (td
.flags
& OHCI_TD_T0
)
542 ed
->head
|= OHCI_ED_C
;
545 dprintf("usb-ohci: Underrun\n");
546 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DATAUNDERRUN
);
550 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DEVICENOTRESPONDING
);
552 dprintf("usb-ohci: got NAK\n");
555 dprintf("usb-ohci: got STALL\n");
556 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_STALL
);
559 dprintf("usb-ohci: got BABBLE\n");
560 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_DATAOVERRUN
);
563 fprintf(stderr
, "usb-ohci: Bad device response %d\n", ret
);
564 OHCI_SET_BM(td
.flags
, TD_CC
, OHCI_CC_UNDEXPETEDPID
);
565 OHCI_SET_BM(td
.flags
, TD_EC
, 3);
569 ed
->head
|= OHCI_ED_H
;
573 ed
->head
&= ~OHCI_DPTR_MASK
;
574 ed
->head
|= td
.next
& OHCI_DPTR_MASK
;
575 td
.next
= ohci
->done
;
577 i
= OHCI_BM(td
.flags
, TD_DI
);
578 if (i
< ohci
->done_count
)
579 ohci
->done_count
= i
;
580 ohci_put_td(addr
, &td
);
581 return OHCI_BM(td
.flags
, TD_CC
) != OHCI_CC_NOERROR
;
584 /* Service an endpoint list. Returns nonzero if active TD were found. */
585 static int ohci_service_ed_list(OHCIState
*ohci
, uint32_t head
)
597 for (cur
= head
; cur
; cur
= next_ed
) {
598 if (!ohci_read_ed(cur
, &ed
)) {
599 fprintf(stderr
, "usb-ohci: ED read error at %x\n", cur
);
603 next_ed
= ed
.next
& OHCI_DPTR_MASK
;
605 if ((ed
.head
& OHCI_ED_H
) || (ed
.flags
& OHCI_ED_K
))
608 /* Skip isochronous endpoints. */
609 if (ed
.flags
& OHCI_ED_F
)
612 while ((ed
.head
& OHCI_DPTR_MASK
) != ed
.tail
) {
614 dprintf("ED @ 0x%.8x fa=%u en=%u d=%u s=%u k=%u f=%u mps=%u "
615 "h=%u c=%u\n head=0x%.8x tailp=0x%.8x next=0x%.8x\n", cur
,
616 OHCI_BM(ed
.flags
, ED_FA
), OHCI_BM(ed
.flags
, ED_EN
),
617 OHCI_BM(ed
.flags
, ED_D
), (ed
.flags
& OHCI_ED_S
)!= 0,
618 (ed
.flags
& OHCI_ED_K
) != 0, (ed
.flags
& OHCI_ED_F
) != 0,
619 OHCI_BM(ed
.flags
, ED_MPS
), (ed
.head
& OHCI_ED_H
) != 0,
620 (ed
.head
& OHCI_ED_C
) != 0, ed
.head
& OHCI_DPTR_MASK
,
621 ed
.tail
& OHCI_DPTR_MASK
, ed
.next
& OHCI_DPTR_MASK
);
625 if (ohci_service_td(ohci
, &ed
))
629 ohci_put_ed(cur
, &ed
);
635 /* Generate a SOF event, and set a timer for EOF */
636 static void ohci_sof(OHCIState
*ohci
)
638 ohci
->sof_time
= qemu_get_clock(vm_clock
);
639 qemu_mod_timer(ohci
->eof_timer
, ohci
->sof_time
+ usb_frame_time
);
640 ohci_set_interrupt(ohci
, OHCI_INTR_SF
);
643 /* Do frame processing on frame boundary */
644 static void ohci_frame_boundary(void *opaque
)
646 OHCIState
*ohci
= opaque
;
647 struct ohci_hcca hcca
;
649 cpu_physical_memory_rw(ohci
->hcca
, (uint8_t *)&hcca
, sizeof(hcca
), 0);
651 /* Process all the lists at the end of the frame */
652 if (ohci
->ctl
& OHCI_CTL_PLE
) {
655 n
= ohci
->frame_number
& 0x1f;
656 ohci_service_ed_list(ohci
, le32_to_cpu(hcca
.intr
[n
]));
658 if ((ohci
->ctl
& OHCI_CTL_CLE
) && (ohci
->status
& OHCI_STATUS_CLF
)) {
659 if (ohci
->ctrl_cur
&& ohci
->ctrl_cur
!= ohci
->ctrl_head
)
660 dprintf("usb-ohci: head %x, cur %x\n", ohci
->ctrl_head
, ohci
->ctrl_cur
);
661 if (!ohci_service_ed_list(ohci
, ohci
->ctrl_head
)) {
663 ohci
->status
&= ~OHCI_STATUS_CLF
;
667 if ((ohci
->ctl
& OHCI_CTL_BLE
) && (ohci
->status
& OHCI_STATUS_BLF
)) {
668 if (!ohci_service_ed_list(ohci
, ohci
->bulk_head
)) {
670 ohci
->status
&= ~OHCI_STATUS_BLF
;
674 /* Frame boundary, so do EOF stuf here */
675 ohci
->frt
= ohci
->fit
;
677 /* XXX: endianness */
678 ohci
->frame_number
= (ohci
->frame_number
+ 1) & 0xffff;
679 hcca
.frame
= cpu_to_le32(ohci
->frame_number
);
681 if (ohci
->done_count
== 0 && !(ohci
->intr_status
& OHCI_INTR_WD
)) {
684 if (ohci
->intr
& ohci
->intr_status
)
686 hcca
.done
= cpu_to_le32(ohci
->done
);
688 ohci
->done_count
= 7;
689 ohci_set_interrupt(ohci
, OHCI_INTR_WD
);
692 if (ohci
->done_count
!= 7 && ohci
->done_count
!= 0)
695 /* Do SOF stuff here */
699 cpu_physical_memory_rw(ohci
->hcca
, (uint8_t *)&hcca
, sizeof(hcca
), 1);
702 /* Start sending SOF tokens across the USB bus, lists are processed in
705 static int ohci_bus_start(OHCIState
*ohci
)
707 ohci
->eof_timer
= qemu_new_timer(vm_clock
,
711 if (ohci
->eof_timer
== NULL
) {
712 fprintf(stderr
, "usb-ohci: %s: qemu_new_timer failed\n",
714 /* TODO: Signal unrecoverable error */
718 dprintf("usb-ohci: %s: USB Operational\n", ohci
->pci_dev
.name
);
725 /* Stop sending SOF tokens on the bus */
726 static void ohci_bus_stop(OHCIState
*ohci
)
729 qemu_del_timer(ohci
->eof_timer
);
732 /* Sets a flag in a port status register but only set it if the port is
733 * connected, if not set ConnectStatusChange flag. If flag is enabled
736 static int ohci_port_set_if_connected(OHCIState
*ohci
, int i
, uint32_t val
)
740 /* writing a 0 has no effect */
744 /* If CurrentConnectStatus is cleared we set
745 * ConnectStatusChange
747 if (!(ohci
->rhport
[i
].ctrl
& OHCI_PORT_CCS
)) {
748 ohci
->rhport
[i
].ctrl
|= OHCI_PORT_CSC
;
749 if (ohci
->rhstatus
& OHCI_RHS_DRWE
) {
750 /* TODO: CSC is a wakeup event */
755 if (ohci
->rhport
[i
].ctrl
& val
)
759 ohci
->rhport
[i
].ctrl
|= val
;
764 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */
765 static void ohci_set_frame_interval(OHCIState
*ohci
, uint16_t val
)
769 if (val
!= ohci
->fi
) {
770 dprintf("usb-ohci: %s: FrameInterval = 0x%x (%u)\n",
771 ohci
->pci_dev
.name
, ohci
->fi
, ohci
->fi
);
777 static void ohci_port_power(OHCIState
*ohci
, int i
, int p
)
780 ohci
->rhport
[i
].ctrl
|= OHCI_PORT_PPS
;
782 ohci
->rhport
[i
].ctrl
&= ~(OHCI_PORT_PPS
|
789 /* Set HcControlRegister */
790 static void ohci_set_ctl(OHCIState
*ohci
, uint32_t val
)
795 old_state
= ohci
->ctl
& OHCI_CTL_HCFS
;
797 new_state
= ohci
->ctl
& OHCI_CTL_HCFS
;
799 /* no state change */
800 if (old_state
== new_state
)
804 case OHCI_USB_OPERATIONAL
:
805 ohci_bus_start(ohci
);
807 case OHCI_USB_SUSPEND
:
809 dprintf("usb-ohci: %s: USB Suspended\n", ohci
->pci_dev
.name
);
811 case OHCI_USB_RESUME
:
812 dprintf("usb-ohci: %s: USB Resume\n", ohci
->pci_dev
.name
);
815 dprintf("usb-ohci: %s: USB Reset\n", ohci
->pci_dev
.name
);
820 static uint32_t ohci_get_frame_remaining(OHCIState
*ohci
)
825 if ((ohci
->ctl
& OHCI_CTL_HCFS
) != OHCI_USB_OPERATIONAL
)
826 return (ohci
->frt
<< 31);
828 /* Being in USB operational state guarnatees sof_time was
831 tks
= qemu_get_clock(vm_clock
) - ohci
->sof_time
;
833 /* avoid muldiv if possible */
834 if (tks
>= usb_frame_time
)
835 return (ohci
->frt
<< 31);
837 tks
= muldiv64(1, tks
, usb_bit_time
);
838 fr
= (uint16_t)(ohci
->fi
- tks
);
840 return (ohci
->frt
<< 31) | fr
;
844 /* Set root hub status */
845 static void ohci_set_hub_status(OHCIState
*ohci
, uint32_t val
)
849 old_state
= ohci
->rhstatus
;
851 /* write 1 to clear OCIC */
852 if (val
& OHCI_RHS_OCIC
)
853 ohci
->rhstatus
&= ~OHCI_RHS_OCIC
;
855 if (val
& OHCI_RHS_LPS
) {
858 for (i
= 0; i
< ohci
->num_ports
; i
++)
859 ohci_port_power(ohci
, i
, 0);
860 dprintf("usb-ohci: powered down all ports\n");
863 if (val
& OHCI_RHS_LPSC
) {
866 for (i
= 0; i
< ohci
->num_ports
; i
++)
867 ohci_port_power(ohci
, i
, 1);
868 dprintf("usb-ohci: powered up all ports\n");
871 if (val
& OHCI_RHS_DRWE
)
872 ohci
->rhstatus
|= OHCI_RHS_DRWE
;
874 if (val
& OHCI_RHS_CRWE
)
875 ohci
->rhstatus
&= ~OHCI_RHS_DRWE
;
877 if (old_state
!= ohci
->rhstatus
)
878 ohci_set_interrupt(ohci
, OHCI_INTR_RHSC
);
881 /* Set root hub port status */
882 static void ohci_port_set_status(OHCIState
*ohci
, int portnum
, uint32_t val
)
887 port
= &ohci
->rhport
[portnum
];
888 old_state
= port
->ctrl
;
890 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */
891 if (val
& OHCI_PORT_WTC
)
892 port
->ctrl
&= ~(val
& OHCI_PORT_WTC
);
894 if (val
& OHCI_PORT_CCS
)
895 port
->ctrl
&= ~OHCI_PORT_PES
;
897 ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PES
);
899 if (ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PSS
))
900 dprintf("usb-ohci: port %d: SUSPEND\n", portnum
);
902 if (ohci_port_set_if_connected(ohci
, portnum
, val
& OHCI_PORT_PRS
)) {
903 dprintf("usb-ohci: port %d: RESET\n", portnum
);
904 port
->port
.dev
->handle_packet(port
->port
.dev
, USB_MSG_RESET
,
906 port
->ctrl
&= ~OHCI_PORT_PRS
;
907 /* ??? Should this also set OHCI_PORT_PESC. */
908 port
->ctrl
|= OHCI_PORT_PES
| OHCI_PORT_PRSC
;
911 /* Invert order here to ensure in ambiguous case, device is
914 if (val
& OHCI_PORT_LSDA
)
915 ohci_port_power(ohci
, portnum
, 0);
916 if (val
& OHCI_PORT_PPS
)
917 ohci_port_power(ohci
, portnum
, 1);
919 if (old_state
!= port
->ctrl
)
920 ohci_set_interrupt(ohci
, OHCI_INTR_RHSC
);
925 static uint32_t ohci_mem_read(void *ptr
, target_phys_addr_t addr
)
927 OHCIState
*ohci
= ptr
;
929 addr
-= ohci
->mem_base
;
931 /* Only aligned reads are allowed on OHCI */
933 fprintf(stderr
, "usb-ohci: Mis-aligned read\n");
937 if (addr
>= 0x54 && addr
< 0x54 + ohci
->num_ports
* 4) {
939 return ohci
->rhport
[(addr
- 0x54) >> 2].ctrl
| OHCI_PORT_PPS
;
943 case 0: /* HcRevision */
946 case 1: /* HcControl */
949 case 2: /* HcCommandStatus */
952 case 3: /* HcInterruptStatus */
953 return ohci
->intr_status
;
955 case 4: /* HcInterruptEnable */
956 case 5: /* HcInterruptDisable */
962 case 7: /* HcPeriodCurrentED */
963 return ohci
->per_cur
;
965 case 8: /* HcControlHeadED */
966 return ohci
->ctrl_head
;
968 case 9: /* HcControlCurrentED */
969 return ohci
->ctrl_cur
;
971 case 10: /* HcBulkHeadED */
972 return ohci
->bulk_head
;
974 case 11: /* HcBulkCurrentED */
975 return ohci
->bulk_cur
;
977 case 12: /* HcDoneHead */
980 case 13: /* HcFmInterval */
981 return (ohci
->fit
<< 31) | (ohci
->fsmps
<< 16) | (ohci
->fi
);
983 case 14: /* HcFmRemaining */
984 return ohci_get_frame_remaining(ohci
);
986 case 15: /* HcFmNumber */
987 return ohci
->frame_number
;
989 case 16: /* HcPeriodicStart */
992 case 17: /* HcLSThreshold */
995 case 18: /* HcRhDescriptorA */
996 return ohci
->rhdesc_a
;
998 case 19: /* HcRhDescriptorB */
999 return ohci
->rhdesc_b
;
1001 case 20: /* HcRhStatus */
1002 return ohci
->rhstatus
;
1005 fprintf(stderr
, "ohci_read: Bad offset %x\n", (int)addr
);
1010 static void ohci_mem_write(void *ptr
, target_phys_addr_t addr
, uint32_t val
)
1012 OHCIState
*ohci
= ptr
;
1014 addr
-= ohci
->mem_base
;
1016 /* Only aligned reads are allowed on OHCI */
1018 fprintf(stderr
, "usb-ohci: Mis-aligned write\n");
1022 if (addr
>= 0x54 && addr
< 0x54 + ohci
->num_ports
* 4) {
1023 /* HcRhPortStatus */
1024 ohci_port_set_status(ohci
, (addr
- 0x54) >> 2, val
);
1028 switch (addr
>> 2) {
1029 case 1: /* HcControl */
1030 ohci_set_ctl(ohci
, val
);
1033 case 2: /* HcCommandStatus */
1034 /* SOC is read-only */
1035 val
= (val
& ~OHCI_STATUS_SOC
);
1037 /* Bits written as '0' remain unchanged in the register */
1038 ohci
->status
|= val
;
1040 if (ohci
->status
& OHCI_STATUS_HCR
)
1044 case 3: /* HcInterruptStatus */
1045 ohci
->intr_status
&= ~val
;
1046 ohci_intr_update(ohci
);
1049 case 4: /* HcInterruptEnable */
1051 ohci_intr_update(ohci
);
1054 case 5: /* HcInterruptDisable */
1056 ohci_intr_update(ohci
);
1059 case 6: /* HcHCCA */
1060 ohci
->hcca
= val
& OHCI_HCCA_MASK
;
1063 case 8: /* HcControlHeadED */
1064 ohci
->ctrl_head
= val
& OHCI_EDPTR_MASK
;
1067 case 9: /* HcControlCurrentED */
1068 ohci
->ctrl_cur
= val
& OHCI_EDPTR_MASK
;
1071 case 10: /* HcBulkHeadED */
1072 ohci
->bulk_head
= val
& OHCI_EDPTR_MASK
;
1075 case 11: /* HcBulkCurrentED */
1076 ohci
->bulk_cur
= val
& OHCI_EDPTR_MASK
;
1079 case 13: /* HcFmInterval */
1080 ohci
->fsmps
= (val
& OHCI_FMI_FSMPS
) >> 16;
1081 ohci
->fit
= (val
& OHCI_FMI_FIT
) >> 31;
1082 ohci_set_frame_interval(ohci
, val
);
1085 case 16: /* HcPeriodicStart */
1086 ohci
->pstart
= val
& 0xffff;
1089 case 17: /* HcLSThreshold */
1090 ohci
->lst
= val
& 0xffff;
1093 case 18: /* HcRhDescriptorA */
1094 ohci
->rhdesc_a
&= ~OHCI_RHA_RW_MASK
;
1095 ohci
->rhdesc_a
|= val
& OHCI_RHA_RW_MASK
;
1098 case 19: /* HcRhDescriptorB */
1101 case 20: /* HcRhStatus */
1102 ohci_set_hub_status(ohci
, val
);
1106 fprintf(stderr
, "ohci_write: Bad offset %x\n", (int)addr
);
1111 /* Only dword reads are defined on OHCI register space */
1112 static CPUReadMemoryFunc
*ohci_readfn
[3]={
1118 /* Only dword writes are defined on OHCI register space */
1119 static CPUWriteMemoryFunc
*ohci_writefn
[3]={
1125 static void ohci_mapfunc(PCIDevice
*pci_dev
, int i
,
1126 uint32_t addr
, uint32_t size
, int type
)
1128 OHCIState
*ohci
= (OHCIState
*)pci_dev
;
1129 ohci
->mem_base
= addr
;
1130 cpu_register_physical_memory(addr
, size
, ohci
->mem
);
1133 void usb_ohci_init(struct PCIBus
*bus
, int num_ports
, int devfn
)
1141 if (usb_frame_time
== 0) {
1143 usb_frame_time
= ticks_per_sec
;
1144 usb_bit_time
= muldiv64(1, ticks_per_sec
, USB_HZ
/1000);
1146 usb_frame_time
= muldiv64(1, ticks_per_sec
, 1000);
1147 if (ticks_per_sec
>= USB_HZ
) {
1148 usb_bit_time
= muldiv64(1, ticks_per_sec
, USB_HZ
);
1153 dprintf("usb-ohci: usb_bit_time=%lli usb_frame_time=%lli\n",
1154 usb_frame_time
, usb_bit_time
);
1157 ohci
= (OHCIState
*)pci_register_device(bus
, "OHCI USB", sizeof(*ohci
),
1160 fprintf(stderr
, "usb-ohci: Failed to register PCI device\n");
1164 ohci
->pci_dev
.config
[0x00] = vid
& 0xff;
1165 ohci
->pci_dev
.config
[0x01] = (vid
>> 8) & 0xff;
1166 ohci
->pci_dev
.config
[0x02] = did
& 0xff;
1167 ohci
->pci_dev
.config
[0x03] = (did
>> 8) & 0xff;
1168 ohci
->pci_dev
.config
[0x09] = 0x10; /* OHCI */
1169 ohci
->pci_dev
.config
[0x0a] = 0x3;
1170 ohci
->pci_dev
.config
[0x0b] = 0xc;
1171 ohci
->pci_dev
.config
[0x3d] = 0x01; /* interrupt pin 1 */
1173 ohci
->mem
= cpu_register_io_memory(0, ohci_readfn
, ohci_writefn
, ohci
);
1175 pci_register_io_region((struct PCIDevice
*)ohci
, 0, 256,
1176 PCI_ADDRESS_SPACE_MEM
, ohci_mapfunc
);
1178 ohci
->num_ports
= num_ports
;
1179 for (i
= 0; i
< num_ports
; i
++) {
1180 qemu_register_usb_port(&ohci
->rhport
[i
].port
, ohci
, i
, ohci_attach
);