hw/versatilepb.c

   1 /*
   2  * ARM Versatile Platform/Application Baseboard System emulation.
   3  *
   4  * Copyright (c) 2005-2007 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the GPL.
   8  */
   9
  10 #include "vl.h"
  11 #include "arm_pic.h"
  12
  13 /* Primary interrupt controller.  */
  14
  15 typedef struct vpb_sic_state
  16 {
  17   uint32_t base;
  18   uint32_t level;
  19   uint32_t mask;
  20   uint32_t pic_enable;
  21   qemu_irq *parent;
  22   int irq;
  23 } vpb_sic_state;
  24
  25 static void vpb_sic_update(vpb_sic_state *s)
  26 {
  27     uint32_t flags;
  28
  29     flags = s->level & s->mask;
  30     qemu_set_irq(s->parent[s->irq], flags != 0);
  31 }
  32
  33 static void vpb_sic_update_pic(vpb_sic_state *s)
  34 {
  35     int i;
  36     uint32_t mask;
  37
  38     for (i = 21; i <= 30; i++) {
  39         mask = 1u << i;
  40         if (!(s->pic_enable & mask))
  41             continue;
  42         qemu_set_irq(s->parent[i], (s->level & mask) != 0);
  43     }
  44 }
  45
  46 static void vpb_sic_set_irq(void *opaque, int irq, int level)
  47 {
  48     vpb_sic_state *s = (vpb_sic_state *)opaque;
  49     if (level)
  50         s->level |= 1u << irq;
  51     else
  52         s->level &= ~(1u << irq);
  53     if (s->pic_enable & (1u << irq))
  54         qemu_set_irq(s->parent[irq], level);
  55     vpb_sic_update(s);
  56 }
  57
  58 static uint32_t vpb_sic_read(void *opaque, target_phys_addr_t offset)
  59 {
  60     vpb_sic_state *s = (vpb_sic_state *)opaque;
  61
  62     offset -= s->base;
  63     switch (offset >> 2) {
  64     case 0: /* STATUS */
  65         return s->level & s->mask;
  66     case 1: /* RAWSTAT */
  67         return s->level;
  68     case 2: /* ENABLE */
  69         return s->mask;
  70     case 4: /* SOFTINT */
  71         return s->level & 1;
  72     case 8: /* PICENABLE */
  73         return s->pic_enable;
  74     default:
  75         printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
  76         return 0;
  77     }
  78 }
  79
  80 static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
  81                           uint32_t value)
  82 {
  83     vpb_sic_state *s = (vpb_sic_state *)opaque;
  84     offset -= s->base;
  85
  86     switch (offset >> 2) {
  87     case 2: /* ENSET */
  88         s->mask |= value;
  89         break;
  90     case 3: /* ENCLR */
  91         s->mask &= ~value;
  92         break;
  93     case 4: /* SOFTINTSET */
  94         if (value)
  95             s->mask |= 1;
  96         break;
  97     case 5: /* SOFTINTCLR */
  98         if (value)
  99             s->mask &= ~1u;
 100         break;
 101     case 8: /* PICENSET */
 102         s->pic_enable |= (value & 0x7fe00000);
 103         vpb_sic_update_pic(s);
 104         break;
 105     case 9: /* PICENCLR */
 106         s->pic_enable &= ~value;
 107         vpb_sic_update_pic(s);
 108         break;
 109     default:
 110         printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
 111         return;
 112     }
 113     vpb_sic_update(s);
 114 }
 115
 116 static CPUReadMemoryFunc *vpb_sic_readfn[] = {
 117    vpb_sic_read,
 118    vpb_sic_read,
 119    vpb_sic_read
 120 };
 121
 122 static CPUWriteMemoryFunc *vpb_sic_writefn[] = {
 123    vpb_sic_write,
 124    vpb_sic_write,
 125    vpb_sic_write
 126 };
 127
 128 static qemu_irq *vpb_sic_init(uint32_t base, qemu_irq *parent, int irq)
 129 {
 130     vpb_sic_state *s;
 131     qemu_irq *qi;
 132     int iomemtype;
 133
 134     s = (vpb_sic_state *)qemu_mallocz(sizeof(vpb_sic_state));
 135     if (!s)
 136         return NULL;
 137     qi = qemu_allocate_irqs(vpb_sic_set_irq, s, 32);
 138     s->base = base;
 139     s->parent = parent;
 140     s->irq = irq;
 141     iomemtype = cpu_register_io_memory(0, vpb_sic_readfn,
 142                                        vpb_sic_writefn, s);
 143     cpu_register_physical_memory(base, 0x00001000, iomemtype);
 144     /* ??? Save/restore.  */
 145     return qi;
 146 }
 147
 148 /* Board init.  */
 149
 150 /* The AB and PB boards both use the same core, just with different
 151    peripherans and expansion busses.  For now we emulate a subset of the
 152    PB peripherals and just change the board ID.  */
 153
 154 static void versatile_init(int ram_size, int vga_ram_size, int boot_device,
 155                      DisplayState *ds, const char **fd_filename, int snapshot,
 156                      const char *kernel_filename, const char *kernel_cmdline,
 157                      const char *initrd_filename, const char *cpu_model,
 158                      int board_id)
 159 {
 160     CPUState *env;
 161     qemu_irq *pic;
 162     qemu_irq *sic;
 163     void *scsi_hba;
 164     PCIBus *pci_bus;
 165     NICInfo *nd;
 166     int n;
 167     int done_smc = 0;
 168
 169     env = cpu_init();
 170     if (!cpu_model)
 171         cpu_model = "arm926";
 172     cpu_arm_set_model(env, cpu_model);
 173     /* ??? RAM shoud repeat to fill physical memory space.  */
 174     /* SDRAM at address zero.  */
 175     cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
 176
 177     arm_sysctl_init(0x10000000, 0x41007004);
 178     pic = arm_pic_init_cpu(env);
 179     pic = pl190_init(0x10140000, pic[0], pic[1]);
 180     sic = vpb_sic_init(0x10003000, pic, 31);
 181     pl050_init(0x10006000, sic[3], 0);
 182     pl050_init(0x10007000, sic[4], 1);
 183
 184     pci_bus = pci_vpb_init(sic, 27, 0);
 185     /* The Versatile PCI bridge does not provide access to PCI IO space,
 186        so many of the qemu PCI devices are not useable.  */
 187     for(n = 0; n < nb_nics; n++) {
 188         nd = &nd_table[n];
 189         if (!nd->model)
 190             nd->model = done_smc ? "rtl8139" : "smc91c111";
 191         if (strcmp(nd->model, "smc91c111") == 0) {
 192             smc91c111_init(nd, 0x10010000, sic[25]);
 193         } else {
 194             pci_nic_init(pci_bus, nd, -1);
 195         }
 196     }
 197     if (usb_enabled) {
 198         usb_ohci_init_pci(pci_bus, 3, -1);
 199     }
 200     scsi_hba = lsi_scsi_init(pci_bus, -1);
 201     for (n = 0; n < MAX_DISKS; n++) {
 202         if (bs_table[n]) {
 203             lsi_scsi_attach(scsi_hba, bs_table[n], n);
 204         }
 205     }
 206
 207     pl011_init(0x101f1000, pic[12], serial_hds[0]);
 208     pl011_init(0x101f2000, pic[13], serial_hds[1]);
 209     pl011_init(0x101f3000, pic[14], serial_hds[2]);
 210     pl011_init(0x10009000, sic[6], serial_hds[3]);
 211
 212     pl080_init(0x10130000, pic[17], 8);
 213     sp804_init(0x101e2000, pic[4]);
 214     sp804_init(0x101e3000, pic[5]);
 215
 216     /* The versatile/PB actually has a modified Color LCD controller
 217        that includes hardware cursor support from the PL111.  */
 218     pl110_init(ds, 0x10120000, pic[16], 1);
 219
 220     pl181_init(0x10005000, sd_bdrv, sic[22], sic[1]);
 221 #if 0
 222     /* Disabled because there's no way of specifying a block device.  */
 223     pl181_init(0x1000b000, NULL, sic, 23, 2);
 224 #endif
 225
 226     /* Memory map for Versatile/PB:  */
 227     /* 0x10000000 System registers.  */
 228     /* 0x10001000 PCI controller config registers.  */
 229     /* 0x10002000 Serial bus interface.  */
 230     /*  0x10003000 Secondary interrupt controller.  */
 231     /* 0x10004000 AACI (audio).  */
 232     /*  0x10005000 MMCI0.  */
 233     /*  0x10006000 KMI0 (keyboard).  */
 234     /*  0x10007000 KMI1 (mouse).  */
 235     /* 0x10008000 Character LCD Interface.  */
 236     /*  0x10009000 UART3.  */
 237     /* 0x1000a000 Smart card 1.  */
 238     /*  0x1000b000 MMCI1.  */
 239     /*  0x10010000 Ethernet.  */
 240     /* 0x10020000 USB.  */
 241     /* 0x10100000 SSMC.  */
 242     /* 0x10110000 MPMC.  */
 243     /*  0x10120000 CLCD Controller.  */
 244     /*  0x10130000 DMA Controller.  */
 245     /*  0x10140000 Vectored interrupt controller.  */
 246     /* 0x101d0000 AHB Monitor Interface.  */
 247     /* 0x101e0000 System Controller.  */
 248     /* 0x101e1000 Watchdog Interface.  */
 249     /* 0x101e2000 Timer 0/1.  */
 250     /* 0x101e3000 Timer 2/3.  */
 251     /* 0x101e4000 GPIO port 0.  */
 252     /* 0x101e5000 GPIO port 1.  */
 253     /* 0x101e6000 GPIO port 2.  */
 254     /* 0x101e7000 GPIO port 3.  */
 255     /* 0x101e8000 RTC.  */
 256     /* 0x101f0000 Smart card 0.  */
 257     /*  0x101f1000 UART0.  */
 258     /*  0x101f2000 UART1.  */
 259     /*  0x101f3000 UART2.  */
 260     /* 0x101f4000 SSPI.  */
 261
 262     arm_load_kernel(env, ram_size, kernel_filename, kernel_cmdline,
 263                     initrd_filename, board_id, 0x0);
 264 }
 265
 266 static void vpb_init(int ram_size, int vga_ram_size, int boot_device,
 267                      DisplayState *ds, const char **fd_filename, int snapshot,
 268                      const char *kernel_filename, const char *kernel_cmdline,
 269                      const char *initrd_filename, const char *cpu_model)
 270 {
 271     versatile_init(ram_size, vga_ram_size, boot_device,
 272                    ds, fd_filename, snapshot,
 273                    kernel_filename, kernel_cmdline,
 274                    initrd_filename, cpu_model, 0x183);
 275 }
 276
 277 static void vab_init(int ram_size, int vga_ram_size, int boot_device,
 278                      DisplayState *ds, const char **fd_filename, int snapshot,
 279                      const char *kernel_filename, const char *kernel_cmdline,
 280                      const char *initrd_filename, const char *cpu_model)
 281 {
 282     versatile_init(ram_size, vga_ram_size, boot_device,
 283                    ds, fd_filename, snapshot,
 284                    kernel_filename, kernel_cmdline,
 285                    initrd_filename, cpu_model, 0x25e);
 286 }
 287
 288 QEMUMachine versatilepb_machine = {
 289     "versatilepb",
 290     "ARM Versatile/PB (ARM926EJ-S)",
 291     vpb_init,
 292 };
 293
 294 QEMUMachine versatileab_machine = {
 295     "versatileab",
 296     "ARM Versatile/AB (ARM926EJ-S)",
 297     vab_init,
 298 };