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1 /*
2 * ARM Versatile Platform/Application Baseboard System emulation.
3 *
4 * Copyright (c) 2005-2007 CodeSourcery.
5 * Written by Paul Brook
6 *
7 * This code is licensed under the GPL.
8 */
9
10 #include "sysbus.h"
11 #include "arm-misc.h"
12 #include "devices.h"
13 #include "net.h"
14 #include "sysemu.h"
15 #include "pci.h"
16 #include "usb-ohci.h"
17 #include "boards.h"
18 #include "blockdev.h"
19 #include "exec-memory.h"
20
21 /* Primary interrupt controller. */
22
23 typedef struct vpb_sic_state
24 {
25 SysBusDevice busdev;
26 MemoryRegion iomem;
27 uint32_t level;
28 uint32_t mask;
29 uint32_t pic_enable;
30 qemu_irq parent[32];
31 int irq;
32 } vpb_sic_state;
33
34 static const VMStateDescription vmstate_vpb_sic = {
35 .name = "versatilepb_sic",
36 .version_id = 1,
37 .minimum_version_id = 1,
38 .fields = (VMStateField[]) {
39 VMSTATE_UINT32(level, vpb_sic_state),
40 VMSTATE_UINT32(mask, vpb_sic_state),
41 VMSTATE_UINT32(pic_enable, vpb_sic_state),
42 VMSTATE_END_OF_LIST()
43 }
44 };
45
46 static void vpb_sic_update(vpb_sic_state *s)
47 {
48 uint32_t flags;
49
50 flags = s->level & s->mask;
51 qemu_set_irq(s->parent[s->irq], flags != 0);
52 }
53
54 static void vpb_sic_update_pic(vpb_sic_state *s)
55 {
56 int i;
57 uint32_t mask;
58
59 for (i = 21; i <= 30; i++) {
60 mask = 1u << i;
61 if (!(s->pic_enable & mask))
62 continue;
63 qemu_set_irq(s->parent[i], (s->level & mask) != 0);
64 }
65 }
66
67 static void vpb_sic_set_irq(void *opaque, int irq, int level)
68 {
69 vpb_sic_state *s = (vpb_sic_state *)opaque;
70 if (level)
71 s->level |= 1u << irq;
72 else
73 s->level &= ~(1u << irq);
74 if (s->pic_enable & (1u << irq))
75 qemu_set_irq(s->parent[irq], level);
76 vpb_sic_update(s);
77 }
78
79 static uint64_t vpb_sic_read(void *opaque, target_phys_addr_t offset,
80 unsigned size)
81 {
82 vpb_sic_state *s = (vpb_sic_state *)opaque;
83
84 switch (offset >> 2) {
85 case 0: /* STATUS */
86 return s->level & s->mask;
87 case 1: /* RAWSTAT */
88 return s->level;
89 case 2: /* ENABLE */
90 return s->mask;
91 case 4: /* SOFTINT */
92 return s->level & 1;
93 case 8: /* PICENABLE */
94 return s->pic_enable;
95 default:
96 printf ("vpb_sic_read: Bad register offset 0x%x\n", (int)offset);
97 return 0;
98 }
99 }
100
101 static void vpb_sic_write(void *opaque, target_phys_addr_t offset,
102 uint64_t value, unsigned size)
103 {
104 vpb_sic_state *s = (vpb_sic_state *)opaque;
105
106 switch (offset >> 2) {
107 case 2: /* ENSET */
108 s->mask |= value;
109 break;
110 case 3: /* ENCLR */
111 s->mask &= ~value;
112 break;
113 case 4: /* SOFTINTSET */
114 if (value)
115 s->mask |= 1;
116 break;
117 case 5: /* SOFTINTCLR */
118 if (value)
119 s->mask &= ~1u;
120 break;
121 case 8: /* PICENSET */
122 s->pic_enable |= (value & 0x7fe00000);
123 vpb_sic_update_pic(s);
124 break;
125 case 9: /* PICENCLR */
126 s->pic_enable &= ~value;
127 vpb_sic_update_pic(s);
128 break;
129 default:
130 printf ("vpb_sic_write: Bad register offset 0x%x\n", (int)offset);
131 return;
132 }
133 vpb_sic_update(s);
134 }
135
136 static const MemoryRegionOps vpb_sic_ops = {
137 .read = vpb_sic_read,
138 .write = vpb_sic_write,
139 .endianness = DEVICE_NATIVE_ENDIAN,
140 };
141
142 static int vpb_sic_init(SysBusDevice *dev)
143 {
144 vpb_sic_state *s = FROM_SYSBUS(vpb_sic_state, dev);
145 int i;
146
147 qdev_init_gpio_in(&dev->qdev, vpb_sic_set_irq, 32);
148 for (i = 0; i < 32; i++) {
149 sysbus_init_irq(dev, &s->parent[i]);
150 }
151 s->irq = 31;
152 memory_region_init_io(&s->iomem, &vpb_sic_ops, s, "vpb-sic", 0x1000);
153 sysbus_init_mmio(dev, &s->iomem);
154 return 0;
155 }
156
157 /* Board init. */
158
159 /* The AB and PB boards both use the same core, just with different
160 peripherans and expansion busses. For now we emulate a subset of the
161 PB peripherals and just change the board ID. */
162
163 static struct arm_boot_info versatile_binfo;
164
165 static void versatile_init(ram_addr_t ram_size,
166 const char *boot_device,
167 const char *kernel_filename, const char *kernel_cmdline,
168 const char *initrd_filename, const char *cpu_model,
169 int board_id)
170 {
171 CPUState *env;
172 MemoryRegion *sysmem = get_system_memory();
173 MemoryRegion *ram = g_new(MemoryRegion, 1);
174 qemu_irq *cpu_pic;
175 qemu_irq pic[32];
176 qemu_irq sic[32];
177 DeviceState *dev, *sysctl;
178 SysBusDevice *busdev;
179 DeviceState *pl041;
180 PCIBus *pci_bus;
181 NICInfo *nd;
182 int n;
183 int done_smc = 0;
184
185 if (!cpu_model)
186 cpu_model = "arm926";
187 env = cpu_init(cpu_model);
188 if (!env) {
189 fprintf(stderr, "Unable to find CPU definition\n");
190 exit(1);
191 }
192 memory_region_init_ram(ram, "versatile.ram", ram_size);
193 vmstate_register_ram_global(ram);
194 /* ??? RAM should repeat to fill physical memory space. */
195 /* SDRAM at address zero. */
196 memory_region_add_subregion(sysmem, 0, ram);
197
198 sysctl = qdev_create(NULL, "realview_sysctl");
199 qdev_prop_set_uint32(sysctl, "sys_id", 0x41007004);
200 qdev_prop_set_uint32(sysctl, "proc_id", 0x02000000);
201 qdev_init_nofail(sysctl);
202 sysbus_mmio_map(sysbus_from_qdev(sysctl), 0, 0x10000000);
203
204 cpu_pic = arm_pic_init_cpu(env);
205 dev = sysbus_create_varargs("pl190", 0x10140000,
206 cpu_pic[0], cpu_pic[1], NULL);
207 for (n = 0; n < 32; n++) {
208 pic[n] = qdev_get_gpio_in(dev, n);
209 }
210 dev = sysbus_create_simple("versatilepb_sic", 0x10003000, NULL);
211 for (n = 0; n < 32; n++) {
212 sysbus_connect_irq(sysbus_from_qdev(dev), n, pic[n]);
213 sic[n] = qdev_get_gpio_in(dev, n);
214 }
215
216 sysbus_create_simple("pl050_keyboard", 0x10006000, sic[3]);
217 sysbus_create_simple("pl050_mouse", 0x10007000, sic[4]);
218
219 dev = qdev_create(NULL, "versatile_pci");
220 busdev = sysbus_from_qdev(dev);
221 qdev_init_nofail(dev);
222 sysbus_mmio_map(busdev, 0, 0x41000000); /* PCI self-config */
223 sysbus_mmio_map(busdev, 1, 0x42000000); /* PCI config */
224 sysbus_connect_irq(busdev, 0, sic[27]);
225 sysbus_connect_irq(busdev, 1, sic[28]);
226 sysbus_connect_irq(busdev, 2, sic[29]);
227 sysbus_connect_irq(busdev, 3, sic[30]);
228 pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci");
229
230 /* The Versatile PCI bridge does not provide access to PCI IO space,
231 so many of the qemu PCI devices are not useable. */
232 for(n = 0; n < nb_nics; n++) {
233 nd = &nd_table[n];
234
235 if (!done_smc && (!nd->model || strcmp(nd->model, "smc91c111") == 0)) {
236 smc91c111_init(nd, 0x10010000, sic[25]);
237 done_smc = 1;
238 } else {
239 pci_nic_init_nofail(nd, "rtl8139", NULL);
240 }
241 }
242 if (usb_enabled) {
243 usb_ohci_init_pci(pci_bus, -1);
244 }
245 n = drive_get_max_bus(IF_SCSI);
246 while (n >= 0) {
247 pci_create_simple(pci_bus, -1, "lsi53c895a");
248 n--;
249 }
250
251 sysbus_create_simple("pl011", 0x101f1000, pic[12]);
252 sysbus_create_simple("pl011", 0x101f2000, pic[13]);
253 sysbus_create_simple("pl011", 0x101f3000, pic[14]);
254 sysbus_create_simple("pl011", 0x10009000, sic[6]);
255
256 sysbus_create_simple("pl080", 0x10130000, pic[17]);
257 sysbus_create_simple("sp804", 0x101e2000, pic[4]);
258 sysbus_create_simple("sp804", 0x101e3000, pic[5]);
259
260 /* The versatile/PB actually has a modified Color LCD controller
261 that includes hardware cursor support from the PL111. */
262 dev = sysbus_create_simple("pl110_versatile", 0x10120000, pic[16]);
263 /* Wire up the mux control signals from the SYS_CLCD register */
264 qdev_connect_gpio_out(sysctl, 0, qdev_get_gpio_in(dev, 0));
265
266 sysbus_create_varargs("pl181", 0x10005000, sic[22], sic[1], NULL);
267 sysbus_create_varargs("pl181", 0x1000b000, sic[23], sic[2], NULL);
268
269 /* Add PL031 Real Time Clock. */
270 sysbus_create_simple("pl031", 0x101e8000, pic[10]);
271
272 /* Add PL041 AACI Interface to the LM4549 codec */
273 pl041 = qdev_create(NULL, "pl041");
274 qdev_prop_set_uint32(pl041, "nc_fifo_depth", 512);
275 qdev_init_nofail(pl041);
276 sysbus_mmio_map(sysbus_from_qdev(pl041), 0, 0x10004000);
277 sysbus_connect_irq(sysbus_from_qdev(pl041), 0, sic[24]);
278
279 /* Memory map for Versatile/PB: */
280 /* 0x10000000 System registers. */
281 /* 0x10001000 PCI controller config registers. */
282 /* 0x10002000 Serial bus interface. */
283 /* 0x10003000 Secondary interrupt controller. */
284 /* 0x10004000 AACI (audio). */
285 /* 0x10005000 MMCI0. */
286 /* 0x10006000 KMI0 (keyboard). */
287 /* 0x10007000 KMI1 (mouse). */
288 /* 0x10008000 Character LCD Interface. */
289 /* 0x10009000 UART3. */
290 /* 0x1000a000 Smart card 1. */
291 /* 0x1000b000 MMCI1. */
292 /* 0x10010000 Ethernet. */
293 /* 0x10020000 USB. */
294 /* 0x10100000 SSMC. */
295 /* 0x10110000 MPMC. */
296 /* 0x10120000 CLCD Controller. */
297 /* 0x10130000 DMA Controller. */
298 /* 0x10140000 Vectored interrupt controller. */
299 /* 0x101d0000 AHB Monitor Interface. */
300 /* 0x101e0000 System Controller. */
301 /* 0x101e1000 Watchdog Interface. */
302 /* 0x101e2000 Timer 0/1. */
303 /* 0x101e3000 Timer 2/3. */
304 /* 0x101e4000 GPIO port 0. */
305 /* 0x101e5000 GPIO port 1. */
306 /* 0x101e6000 GPIO port 2. */
307 /* 0x101e7000 GPIO port 3. */
308 /* 0x101e8000 RTC. */
309 /* 0x101f0000 Smart card 0. */
310 /* 0x101f1000 UART0. */
311 /* 0x101f2000 UART1. */
312 /* 0x101f3000 UART2. */
313 /* 0x101f4000 SSPI. */
314
315 versatile_binfo.ram_size = ram_size;
316 versatile_binfo.kernel_filename = kernel_filename;
317 versatile_binfo.kernel_cmdline = kernel_cmdline;
318 versatile_binfo.initrd_filename = initrd_filename;
319 versatile_binfo.board_id = board_id;
320 arm_load_kernel(env, &versatile_binfo);
321 }
322
323 static void vpb_init(ram_addr_t ram_size,
324 const char *boot_device,
325 const char *kernel_filename, const char *kernel_cmdline,
326 const char *initrd_filename, const char *cpu_model)
327 {
328 versatile_init(ram_size,
329 boot_device,
330 kernel_filename, kernel_cmdline,
331 initrd_filename, cpu_model, 0x183);
332 }
333
334 static void vab_init(ram_addr_t ram_size,
335 const char *boot_device,
336 const char *kernel_filename, const char *kernel_cmdline,
337 const char *initrd_filename, const char *cpu_model)
338 {
339 versatile_init(ram_size,
340 boot_device,
341 kernel_filename, kernel_cmdline,
342 initrd_filename, cpu_model, 0x25e);
343 }
344
345 static QEMUMachine versatilepb_machine = {
346 .name = "versatilepb",
347 .desc = "ARM Versatile/PB (ARM926EJ-S)",
348 .init = vpb_init,
349 .use_scsi = 1,
350 };
351
352 static QEMUMachine versatileab_machine = {
353 .name = "versatileab",
354 .desc = "ARM Versatile/AB (ARM926EJ-S)",
355 .init = vab_init,
356 .use_scsi = 1,
357 };
358
359 static void versatile_machine_init(void)
360 {
361 qemu_register_machine(&versatilepb_machine);
362 qemu_register_machine(&versatileab_machine);
363 }
364
365 machine_init(versatile_machine_init);
366
367 static void vpb_sic_class_init(ObjectClass *klass, void *data)
368 {
369 DeviceClass *dc = DEVICE_CLASS(klass);
370 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
371
372 k->init = vpb_sic_init;
373 dc->no_user = 1;
374 dc->vmsd = &vmstate_vpb_sic;
375 }
376
377 static TypeInfo vpb_sic_info = {
378 .name = "versatilepb_sic",
379 .parent = TYPE_SYS_BUS_DEVICE,
380 .instance_size = sizeof(vpb_sic_state),
381 .class_init = vpb_sic_class_init,
382 };
383
384 static void versatilepb_register_types(void)
385 {
386 type_register_static(&vpb_sic_info);
387 }
388
389 type_init(versatilepb_register_types)