2 * vfio based device assignment support
4 * Copyright Red Hat, Inc. 2012
7 * Alex Williamson <alex.williamson@redhat.com>
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
12 * Based on qemu-kvm device-assignment:
13 * Adapted for KVM by Qumranet.
14 * Copyright (c) 2007, Neocleus, Alex Novik (alex@neocleus.com)
15 * Copyright (c) 2007, Neocleus, Guy Zana (guy@neocleus.com)
16 * Copyright (C) 2008, Qumranet, Amit Shah (amit.shah@qumranet.com)
17 * Copyright (C) 2008, Red Hat, Amit Shah (amit.shah@redhat.com)
18 * Copyright (C) 2008, IBM, Muli Ben-Yehuda (muli@il.ibm.com)
21 #include <linux/vfio.h>
22 #include <sys/ioctl.h>
25 #include <sys/types.h>
29 #include "exec/address-spaces.h"
30 #include "exec/memory.h"
31 #include "hw/pci/msi.h"
32 #include "hw/pci/msix.h"
33 #include "hw/pci/pci.h"
34 #include "qemu-common.h"
35 #include "qemu/error-report.h"
36 #include "qemu/event_notifier.h"
37 #include "qemu/queue.h"
38 #include "qemu/range.h"
39 #include "sysemu/kvm.h"
40 #include "sysemu/sysemu.h"
42 #include "hw/vfio/vfio.h"
43 #include "hw/vfio/vfio-common.h"
47 typedef struct VFIOQuirk
{
49 struct VFIOPCIDevice
*vdev
;
50 QLIST_ENTRY(VFIOQuirk
) next
;
52 uint32_t base_offset
:TARGET_PAGE_BITS
;
53 uint32_t address_offset
:TARGET_PAGE_BITS
;
54 uint32_t address_size
:3;
57 uint32_t address_match
;
58 uint32_t address_mask
;
60 uint32_t address_val
:TARGET_PAGE_BITS
;
61 uint32_t data_offset
:TARGET_PAGE_BITS
;
70 typedef struct VFIOBAR
{
74 QLIST_HEAD(, VFIOQuirk
) quirks
;
77 typedef struct VFIOVGARegion
{
81 QLIST_HEAD(, VFIOQuirk
) quirks
;
84 typedef struct VFIOVGA
{
87 VFIOVGARegion region
[QEMU_PCI_VGA_NUM_REGIONS
];
90 typedef struct VFIOINTx
{
91 bool pending
; /* interrupt pending */
92 bool kvm_accel
; /* set when QEMU bypass through KVM enabled */
93 uint8_t pin
; /* which pin to pull for qemu_set_irq */
94 EventNotifier interrupt
; /* eventfd triggered on interrupt */
95 EventNotifier unmask
; /* eventfd for unmask on QEMU bypass */
96 PCIINTxRoute route
; /* routing info for QEMU bypass */
97 uint32_t mmap_timeout
; /* delay to re-enable mmaps after interrupt */
98 QEMUTimer
*mmap_timer
; /* enable mmaps after periods w/o interrupts */
101 typedef struct VFIOMSIVector
{
103 * Two interrupt paths are configured per vector. The first, is only used
104 * for interrupts injected via QEMU. This is typically the non-accel path,
105 * but may also be used when we want QEMU to handle masking and pending
106 * bits. The KVM path bypasses QEMU and is therefore higher performance,
107 * but requires masking at the device. virq is used to track the MSI route
108 * through KVM, thus kvm_interrupt is only available when virq is set to a
109 * valid (>= 0) value.
111 EventNotifier interrupt
;
112 EventNotifier kvm_interrupt
;
113 struct VFIOPCIDevice
*vdev
; /* back pointer to device */
125 /* Cache of MSI-X setup plus extra mmap and memory region for split BAR map */
126 typedef struct VFIOMSIXInfo
{
130 uint32_t table_offset
;
132 MemoryRegion mmap_mem
;
136 typedef struct VFIOPCIDevice
{
140 unsigned int config_size
;
141 uint8_t *emulated_config_bits
; /* QEMU emulated bits, little-endian */
142 off_t config_offset
; /* Offset of config space region within device fd */
143 unsigned int rom_size
;
144 off_t rom_offset
; /* Offset of ROM region within device fd */
147 VFIOMSIVector
*msi_vectors
;
149 int nr_vectors
; /* Number of MSI/MSIX vectors currently in use */
150 int interrupt
; /* Current interrupt type */
151 VFIOBAR bars
[PCI_NUM_REGIONS
- 1]; /* No ROM */
152 VFIOVGA vga
; /* 0xa0000, 0x3b0, 0x3c0 */
153 PCIHostDeviceAddress host
;
154 EventNotifier err_notifier
;
155 EventNotifier req_notifier
;
156 int (*resetfn
)(struct VFIOPCIDevice
*);
158 #define VFIO_FEATURE_ENABLE_VGA_BIT 0
159 #define VFIO_FEATURE_ENABLE_VGA (1 << VFIO_FEATURE_ENABLE_VGA_BIT)
160 #define VFIO_FEATURE_ENABLE_REQ_BIT 1
161 #define VFIO_FEATURE_ENABLE_REQ (1 << VFIO_FEATURE_ENABLE_REQ_BIT)
169 bool rom_read_failed
;
172 typedef struct VFIORomBlacklistEntry
{
175 } VFIORomBlacklistEntry
;
178 * List of device ids/vendor ids for which to disable
179 * option rom loading. This avoids the guest hangs during rom
180 * execution as noticed with the BCM 57810 card for lack of a
181 * more better way to handle such issues.
182 * The user can still override by specifying a romfile or
184 * Please see https://bugs.launchpad.net/qemu/+bug/1284874
185 * for an analysis of the 57810 card hang. When adding
186 * a new vendor id/device id combination below, please also add
187 * your card/environment details and information that could
188 * help in debugging to the bug tracking this issue
190 static const VFIORomBlacklistEntry romblacklist
[] = {
191 /* Broadcom BCM 57810 */
195 #define MSIX_CAP_LENGTH 12
197 static void vfio_disable_interrupts(VFIOPCIDevice
*vdev
);
198 static uint32_t vfio_pci_read_config(PCIDevice
*pdev
, uint32_t addr
, int len
);
199 static void vfio_pci_write_config(PCIDevice
*pdev
, uint32_t addr
,
200 uint32_t val
, int len
);
201 static void vfio_mmap_set_enabled(VFIOPCIDevice
*vdev
, bool enabled
);
204 * Disabling BAR mmaping can be slow, but toggling it around INTx can
205 * also be a huge overhead. We try to get the best of both worlds by
206 * waiting until an interrupt to disable mmaps (subsequent transitions
207 * to the same state are effectively no overhead). If the interrupt has
208 * been serviced and the time gap is long enough, we re-enable mmaps for
209 * performance. This works well for things like graphics cards, which
210 * may not use their interrupt at all and are penalized to an unusable
211 * level by read/write BAR traps. Other devices, like NICs, have more
212 * regular interrupts and see much better latency by staying in non-mmap
213 * mode. We therefore set the default mmap_timeout such that a ping
214 * is just enough to keep the mmap disabled. Users can experiment with
215 * other options with the x-intx-mmap-timeout-ms parameter (a value of
216 * zero disables the timer).
218 static void vfio_intx_mmap_enable(void *opaque
)
220 VFIOPCIDevice
*vdev
= opaque
;
222 if (vdev
->intx
.pending
) {
223 timer_mod(vdev
->intx
.mmap_timer
,
224 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
) + vdev
->intx
.mmap_timeout
);
228 vfio_mmap_set_enabled(vdev
, true);
231 static void vfio_intx_interrupt(void *opaque
)
233 VFIOPCIDevice
*vdev
= opaque
;
235 if (!event_notifier_test_and_clear(&vdev
->intx
.interrupt
)) {
239 trace_vfio_intx_interrupt(vdev
->vbasedev
.name
, 'A' + vdev
->intx
.pin
);
241 vdev
->intx
.pending
= true;
242 pci_irq_assert(&vdev
->pdev
);
243 vfio_mmap_set_enabled(vdev
, false);
244 if (vdev
->intx
.mmap_timeout
) {
245 timer_mod(vdev
->intx
.mmap_timer
,
246 qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL
) + vdev
->intx
.mmap_timeout
);
250 static void vfio_eoi(VFIODevice
*vbasedev
)
252 VFIOPCIDevice
*vdev
= container_of(vbasedev
, VFIOPCIDevice
, vbasedev
);
254 if (!vdev
->intx
.pending
) {
258 trace_vfio_eoi(vbasedev
->name
);
260 vdev
->intx
.pending
= false;
261 pci_irq_deassert(&vdev
->pdev
);
262 vfio_unmask_single_irqindex(vbasedev
, VFIO_PCI_INTX_IRQ_INDEX
);
265 static void vfio_enable_intx_kvm(VFIOPCIDevice
*vdev
)
268 struct kvm_irqfd irqfd
= {
269 .fd
= event_notifier_get_fd(&vdev
->intx
.interrupt
),
270 .gsi
= vdev
->intx
.route
.irq
,
271 .flags
= KVM_IRQFD_FLAG_RESAMPLE
,
273 struct vfio_irq_set
*irq_set
;
277 if (!VFIO_ALLOW_KVM_INTX
|| !kvm_irqfds_enabled() ||
278 vdev
->intx
.route
.mode
!= PCI_INTX_ENABLED
||
279 !kvm_resamplefds_enabled()) {
283 /* Get to a known interrupt state */
284 qemu_set_fd_handler(irqfd
.fd
, NULL
, NULL
, vdev
);
285 vfio_mask_single_irqindex(&vdev
->vbasedev
, VFIO_PCI_INTX_IRQ_INDEX
);
286 vdev
->intx
.pending
= false;
287 pci_irq_deassert(&vdev
->pdev
);
289 /* Get an eventfd for resample/unmask */
290 if (event_notifier_init(&vdev
->intx
.unmask
, 0)) {
291 error_report("vfio: Error: event_notifier_init failed eoi");
295 /* KVM triggers it, VFIO listens for it */
296 irqfd
.resamplefd
= event_notifier_get_fd(&vdev
->intx
.unmask
);
298 if (kvm_vm_ioctl(kvm_state
, KVM_IRQFD
, &irqfd
)) {
299 error_report("vfio: Error: Failed to setup resample irqfd: %m");
303 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
305 irq_set
= g_malloc0(argsz
);
306 irq_set
->argsz
= argsz
;
307 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
| VFIO_IRQ_SET_ACTION_UNMASK
;
308 irq_set
->index
= VFIO_PCI_INTX_IRQ_INDEX
;
311 pfd
= (int32_t *)&irq_set
->data
;
313 *pfd
= irqfd
.resamplefd
;
315 ret
= ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
318 error_report("vfio: Error: Failed to setup INTx unmask fd: %m");
323 vfio_unmask_single_irqindex(&vdev
->vbasedev
, VFIO_PCI_INTX_IRQ_INDEX
);
325 vdev
->intx
.kvm_accel
= true;
327 trace_vfio_enable_intx_kvm(vdev
->vbasedev
.name
);
332 irqfd
.flags
= KVM_IRQFD_FLAG_DEASSIGN
;
333 kvm_vm_ioctl(kvm_state
, KVM_IRQFD
, &irqfd
);
335 event_notifier_cleanup(&vdev
->intx
.unmask
);
337 qemu_set_fd_handler(irqfd
.fd
, vfio_intx_interrupt
, NULL
, vdev
);
338 vfio_unmask_single_irqindex(&vdev
->vbasedev
, VFIO_PCI_INTX_IRQ_INDEX
);
342 static void vfio_disable_intx_kvm(VFIOPCIDevice
*vdev
)
345 struct kvm_irqfd irqfd
= {
346 .fd
= event_notifier_get_fd(&vdev
->intx
.interrupt
),
347 .gsi
= vdev
->intx
.route
.irq
,
348 .flags
= KVM_IRQFD_FLAG_DEASSIGN
,
351 if (!vdev
->intx
.kvm_accel
) {
356 * Get to a known state, hardware masked, QEMU ready to accept new
357 * interrupts, QEMU IRQ de-asserted.
359 vfio_mask_single_irqindex(&vdev
->vbasedev
, VFIO_PCI_INTX_IRQ_INDEX
);
360 vdev
->intx
.pending
= false;
361 pci_irq_deassert(&vdev
->pdev
);
363 /* Tell KVM to stop listening for an INTx irqfd */
364 if (kvm_vm_ioctl(kvm_state
, KVM_IRQFD
, &irqfd
)) {
365 error_report("vfio: Error: Failed to disable INTx irqfd: %m");
368 /* We only need to close the eventfd for VFIO to cleanup the kernel side */
369 event_notifier_cleanup(&vdev
->intx
.unmask
);
371 /* QEMU starts listening for interrupt events. */
372 qemu_set_fd_handler(irqfd
.fd
, vfio_intx_interrupt
, NULL
, vdev
);
374 vdev
->intx
.kvm_accel
= false;
376 /* If we've missed an event, let it re-fire through QEMU */
377 vfio_unmask_single_irqindex(&vdev
->vbasedev
, VFIO_PCI_INTX_IRQ_INDEX
);
379 trace_vfio_disable_intx_kvm(vdev
->vbasedev
.name
);
383 static void vfio_update_irq(PCIDevice
*pdev
)
385 VFIOPCIDevice
*vdev
= DO_UPCAST(VFIOPCIDevice
, pdev
, pdev
);
388 if (vdev
->interrupt
!= VFIO_INT_INTx
) {
392 route
= pci_device_route_intx_to_irq(&vdev
->pdev
, vdev
->intx
.pin
);
394 if (!pci_intx_route_changed(&vdev
->intx
.route
, &route
)) {
395 return; /* Nothing changed */
398 trace_vfio_update_irq(vdev
->vbasedev
.name
,
399 vdev
->intx
.route
.irq
, route
.irq
);
401 vfio_disable_intx_kvm(vdev
);
403 vdev
->intx
.route
= route
;
405 if (route
.mode
!= PCI_INTX_ENABLED
) {
409 vfio_enable_intx_kvm(vdev
);
411 /* Re-enable the interrupt in cased we missed an EOI */
412 vfio_eoi(&vdev
->vbasedev
);
415 static int vfio_enable_intx(VFIOPCIDevice
*vdev
)
417 uint8_t pin
= vfio_pci_read_config(&vdev
->pdev
, PCI_INTERRUPT_PIN
, 1);
419 struct vfio_irq_set
*irq_set
;
426 vfio_disable_interrupts(vdev
);
428 vdev
->intx
.pin
= pin
- 1; /* Pin A (1) -> irq[0] */
429 pci_config_set_interrupt_pin(vdev
->pdev
.config
, pin
);
433 * Only conditional to avoid generating error messages on platforms
434 * where we won't actually use the result anyway.
436 if (kvm_irqfds_enabled() && kvm_resamplefds_enabled()) {
437 vdev
->intx
.route
= pci_device_route_intx_to_irq(&vdev
->pdev
,
442 ret
= event_notifier_init(&vdev
->intx
.interrupt
, 0);
444 error_report("vfio: Error: event_notifier_init failed");
448 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
450 irq_set
= g_malloc0(argsz
);
451 irq_set
->argsz
= argsz
;
452 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
| VFIO_IRQ_SET_ACTION_TRIGGER
;
453 irq_set
->index
= VFIO_PCI_INTX_IRQ_INDEX
;
456 pfd
= (int32_t *)&irq_set
->data
;
458 *pfd
= event_notifier_get_fd(&vdev
->intx
.interrupt
);
459 qemu_set_fd_handler(*pfd
, vfio_intx_interrupt
, NULL
, vdev
);
461 ret
= ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
464 error_report("vfio: Error: Failed to setup INTx fd: %m");
465 qemu_set_fd_handler(*pfd
, NULL
, NULL
, vdev
);
466 event_notifier_cleanup(&vdev
->intx
.interrupt
);
470 vfio_enable_intx_kvm(vdev
);
472 vdev
->interrupt
= VFIO_INT_INTx
;
474 trace_vfio_enable_intx(vdev
->vbasedev
.name
);
479 static void vfio_disable_intx(VFIOPCIDevice
*vdev
)
483 timer_del(vdev
->intx
.mmap_timer
);
484 vfio_disable_intx_kvm(vdev
);
485 vfio_disable_irqindex(&vdev
->vbasedev
, VFIO_PCI_INTX_IRQ_INDEX
);
486 vdev
->intx
.pending
= false;
487 pci_irq_deassert(&vdev
->pdev
);
488 vfio_mmap_set_enabled(vdev
, true);
490 fd
= event_notifier_get_fd(&vdev
->intx
.interrupt
);
491 qemu_set_fd_handler(fd
, NULL
, NULL
, vdev
);
492 event_notifier_cleanup(&vdev
->intx
.interrupt
);
494 vdev
->interrupt
= VFIO_INT_NONE
;
496 trace_vfio_disable_intx(vdev
->vbasedev
.name
);
502 static void vfio_msi_interrupt(void *opaque
)
504 VFIOMSIVector
*vector
= opaque
;
505 VFIOPCIDevice
*vdev
= vector
->vdev
;
506 int nr
= vector
- vdev
->msi_vectors
;
508 if (!event_notifier_test_and_clear(&vector
->interrupt
)) {
515 if (vdev
->interrupt
== VFIO_INT_MSIX
) {
516 msg
= msix_get_message(&vdev
->pdev
, nr
);
517 } else if (vdev
->interrupt
== VFIO_INT_MSI
) {
518 msg
= msi_get_message(&vdev
->pdev
, nr
);
523 trace_vfio_msi_interrupt(vdev
->vbasedev
.name
, nr
, msg
.address
, msg
.data
);
526 if (vdev
->interrupt
== VFIO_INT_MSIX
) {
527 msix_notify(&vdev
->pdev
, nr
);
528 } else if (vdev
->interrupt
== VFIO_INT_MSI
) {
529 msi_notify(&vdev
->pdev
, nr
);
531 error_report("vfio: MSI interrupt receieved, but not enabled?");
535 static int vfio_enable_vectors(VFIOPCIDevice
*vdev
, bool msix
)
537 struct vfio_irq_set
*irq_set
;
538 int ret
= 0, i
, argsz
;
541 argsz
= sizeof(*irq_set
) + (vdev
->nr_vectors
* sizeof(*fds
));
543 irq_set
= g_malloc0(argsz
);
544 irq_set
->argsz
= argsz
;
545 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
| VFIO_IRQ_SET_ACTION_TRIGGER
;
546 irq_set
->index
= msix
? VFIO_PCI_MSIX_IRQ_INDEX
: VFIO_PCI_MSI_IRQ_INDEX
;
548 irq_set
->count
= vdev
->nr_vectors
;
549 fds
= (int32_t *)&irq_set
->data
;
551 for (i
= 0; i
< vdev
->nr_vectors
; i
++) {
555 * MSI vs MSI-X - The guest has direct access to MSI mask and pending
556 * bits, therefore we always use the KVM signaling path when setup.
557 * MSI-X mask and pending bits are emulated, so we want to use the
558 * KVM signaling path only when configured and unmasked.
560 if (vdev
->msi_vectors
[i
].use
) {
561 if (vdev
->msi_vectors
[i
].virq
< 0 ||
562 (msix
&& msix_is_masked(&vdev
->pdev
, i
))) {
563 fd
= event_notifier_get_fd(&vdev
->msi_vectors
[i
].interrupt
);
565 fd
= event_notifier_get_fd(&vdev
->msi_vectors
[i
].kvm_interrupt
);
572 ret
= ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
579 static void vfio_add_kvm_msi_virq(VFIOMSIVector
*vector
, MSIMessage
*msg
,
584 if ((msix
&& !VFIO_ALLOW_KVM_MSIX
) ||
585 (!msix
&& !VFIO_ALLOW_KVM_MSI
) || !msg
) {
589 if (event_notifier_init(&vector
->kvm_interrupt
, 0)) {
593 virq
= kvm_irqchip_add_msi_route(kvm_state
, *msg
);
595 event_notifier_cleanup(&vector
->kvm_interrupt
);
599 if (kvm_irqchip_add_irqfd_notifier_gsi(kvm_state
, &vector
->kvm_interrupt
,
601 kvm_irqchip_release_virq(kvm_state
, virq
);
602 event_notifier_cleanup(&vector
->kvm_interrupt
);
609 static void vfio_remove_kvm_msi_virq(VFIOMSIVector
*vector
)
611 kvm_irqchip_remove_irqfd_notifier_gsi(kvm_state
, &vector
->kvm_interrupt
,
613 kvm_irqchip_release_virq(kvm_state
, vector
->virq
);
615 event_notifier_cleanup(&vector
->kvm_interrupt
);
618 static void vfio_update_kvm_msi_virq(VFIOMSIVector
*vector
, MSIMessage msg
)
620 kvm_irqchip_update_msi_route(kvm_state
, vector
->virq
, msg
);
623 static int vfio_msix_vector_do_use(PCIDevice
*pdev
, unsigned int nr
,
624 MSIMessage
*msg
, IOHandler
*handler
)
626 VFIOPCIDevice
*vdev
= DO_UPCAST(VFIOPCIDevice
, pdev
, pdev
);
627 VFIOMSIVector
*vector
;
630 trace_vfio_msix_vector_do_use(vdev
->vbasedev
.name
, nr
);
632 vector
= &vdev
->msi_vectors
[nr
];
637 if (event_notifier_init(&vector
->interrupt
, 0)) {
638 error_report("vfio: Error: event_notifier_init failed");
641 msix_vector_use(pdev
, nr
);
644 qemu_set_fd_handler(event_notifier_get_fd(&vector
->interrupt
),
645 handler
, NULL
, vector
);
648 * Attempt to enable route through KVM irqchip,
649 * default to userspace handling if unavailable.
651 if (vector
->virq
>= 0) {
653 vfio_remove_kvm_msi_virq(vector
);
655 vfio_update_kvm_msi_virq(vector
, *msg
);
658 vfio_add_kvm_msi_virq(vector
, msg
, true);
662 * We don't want to have the host allocate all possible MSI vectors
663 * for a device if they're not in use, so we shutdown and incrementally
664 * increase them as needed.
666 if (vdev
->nr_vectors
< nr
+ 1) {
667 vfio_disable_irqindex(&vdev
->vbasedev
, VFIO_PCI_MSIX_IRQ_INDEX
);
668 vdev
->nr_vectors
= nr
+ 1;
669 ret
= vfio_enable_vectors(vdev
, true);
671 error_report("vfio: failed to enable vectors, %d", ret
);
675 struct vfio_irq_set
*irq_set
;
678 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
680 irq_set
= g_malloc0(argsz
);
681 irq_set
->argsz
= argsz
;
682 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
|
683 VFIO_IRQ_SET_ACTION_TRIGGER
;
684 irq_set
->index
= VFIO_PCI_MSIX_IRQ_INDEX
;
687 pfd
= (int32_t *)&irq_set
->data
;
689 if (vector
->virq
>= 0) {
690 *pfd
= event_notifier_get_fd(&vector
->kvm_interrupt
);
692 *pfd
= event_notifier_get_fd(&vector
->interrupt
);
695 ret
= ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
698 error_report("vfio: failed to modify vector, %d", ret
);
705 static int vfio_msix_vector_use(PCIDevice
*pdev
,
706 unsigned int nr
, MSIMessage msg
)
708 return vfio_msix_vector_do_use(pdev
, nr
, &msg
, vfio_msi_interrupt
);
711 static void vfio_msix_vector_release(PCIDevice
*pdev
, unsigned int nr
)
713 VFIOPCIDevice
*vdev
= DO_UPCAST(VFIOPCIDevice
, pdev
, pdev
);
714 VFIOMSIVector
*vector
= &vdev
->msi_vectors
[nr
];
716 trace_vfio_msix_vector_release(vdev
->vbasedev
.name
, nr
);
719 * There are still old guests that mask and unmask vectors on every
720 * interrupt. If we're using QEMU bypass with a KVM irqfd, leave all of
721 * the KVM setup in place, simply switch VFIO to use the non-bypass
722 * eventfd. We'll then fire the interrupt through QEMU and the MSI-X
723 * core will mask the interrupt and set pending bits, allowing it to
724 * be re-asserted on unmask. Nothing to do if already using QEMU mode.
726 if (vector
->virq
>= 0) {
728 struct vfio_irq_set
*irq_set
;
731 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
733 irq_set
= g_malloc0(argsz
);
734 irq_set
->argsz
= argsz
;
735 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
|
736 VFIO_IRQ_SET_ACTION_TRIGGER
;
737 irq_set
->index
= VFIO_PCI_MSIX_IRQ_INDEX
;
740 pfd
= (int32_t *)&irq_set
->data
;
742 *pfd
= event_notifier_get_fd(&vector
->interrupt
);
744 ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
750 static void vfio_enable_msix(VFIOPCIDevice
*vdev
)
752 vfio_disable_interrupts(vdev
);
754 vdev
->msi_vectors
= g_malloc0(vdev
->msix
->entries
* sizeof(VFIOMSIVector
));
756 vdev
->interrupt
= VFIO_INT_MSIX
;
759 * Some communication channels between VF & PF or PF & fw rely on the
760 * physical state of the device and expect that enabling MSI-X from the
761 * guest enables the same on the host. When our guest is Linux, the
762 * guest driver call to pci_enable_msix() sets the enabling bit in the
763 * MSI-X capability, but leaves the vector table masked. We therefore
764 * can't rely on a vector_use callback (from request_irq() in the guest)
765 * to switch the physical device into MSI-X mode because that may come a
766 * long time after pci_enable_msix(). This code enables vector 0 with
767 * triggering to userspace, then immediately release the vector, leaving
768 * the physical device with no vectors enabled, but MSI-X enabled, just
769 * like the guest view.
771 vfio_msix_vector_do_use(&vdev
->pdev
, 0, NULL
, NULL
);
772 vfio_msix_vector_release(&vdev
->pdev
, 0);
774 if (msix_set_vector_notifiers(&vdev
->pdev
, vfio_msix_vector_use
,
775 vfio_msix_vector_release
, NULL
)) {
776 error_report("vfio: msix_set_vector_notifiers failed");
779 trace_vfio_enable_msix(vdev
->vbasedev
.name
);
782 static void vfio_enable_msi(VFIOPCIDevice
*vdev
)
786 vfio_disable_interrupts(vdev
);
788 vdev
->nr_vectors
= msi_nr_vectors_allocated(&vdev
->pdev
);
790 vdev
->msi_vectors
= g_malloc0(vdev
->nr_vectors
* sizeof(VFIOMSIVector
));
792 for (i
= 0; i
< vdev
->nr_vectors
; i
++) {
793 VFIOMSIVector
*vector
= &vdev
->msi_vectors
[i
];
794 MSIMessage msg
= msi_get_message(&vdev
->pdev
, i
);
800 if (event_notifier_init(&vector
->interrupt
, 0)) {
801 error_report("vfio: Error: event_notifier_init failed");
804 qemu_set_fd_handler(event_notifier_get_fd(&vector
->interrupt
),
805 vfio_msi_interrupt
, NULL
, vector
);
808 * Attempt to enable route through KVM irqchip,
809 * default to userspace handling if unavailable.
811 vfio_add_kvm_msi_virq(vector
, &msg
, false);
814 /* Set interrupt type prior to possible interrupts */
815 vdev
->interrupt
= VFIO_INT_MSI
;
817 ret
= vfio_enable_vectors(vdev
, false);
820 error_report("vfio: Error: Failed to setup MSI fds: %m");
821 } else if (ret
!= vdev
->nr_vectors
) {
822 error_report("vfio: Error: Failed to enable %d "
823 "MSI vectors, retry with %d", vdev
->nr_vectors
, ret
);
826 for (i
= 0; i
< vdev
->nr_vectors
; i
++) {
827 VFIOMSIVector
*vector
= &vdev
->msi_vectors
[i
];
828 if (vector
->virq
>= 0) {
829 vfio_remove_kvm_msi_virq(vector
);
831 qemu_set_fd_handler(event_notifier_get_fd(&vector
->interrupt
),
833 event_notifier_cleanup(&vector
->interrupt
);
836 g_free(vdev
->msi_vectors
);
838 if (ret
> 0 && ret
!= vdev
->nr_vectors
) {
839 vdev
->nr_vectors
= ret
;
842 vdev
->nr_vectors
= 0;
845 * Failing to setup MSI doesn't really fall within any specification.
846 * Let's try leaving interrupts disabled and hope the guest figures
847 * out to fall back to INTx for this device.
849 error_report("vfio: Error: Failed to enable MSI");
850 vdev
->interrupt
= VFIO_INT_NONE
;
855 trace_vfio_enable_msi(vdev
->vbasedev
.name
, vdev
->nr_vectors
);
858 static void vfio_disable_msi_common(VFIOPCIDevice
*vdev
)
862 for (i
= 0; i
< vdev
->nr_vectors
; i
++) {
863 VFIOMSIVector
*vector
= &vdev
->msi_vectors
[i
];
864 if (vdev
->msi_vectors
[i
].use
) {
865 if (vector
->virq
>= 0) {
866 vfio_remove_kvm_msi_virq(vector
);
868 qemu_set_fd_handler(event_notifier_get_fd(&vector
->interrupt
),
870 event_notifier_cleanup(&vector
->interrupt
);
874 g_free(vdev
->msi_vectors
);
875 vdev
->msi_vectors
= NULL
;
876 vdev
->nr_vectors
= 0;
877 vdev
->interrupt
= VFIO_INT_NONE
;
879 vfio_enable_intx(vdev
);
882 static void vfio_disable_msix(VFIOPCIDevice
*vdev
)
886 msix_unset_vector_notifiers(&vdev
->pdev
);
889 * MSI-X will only release vectors if MSI-X is still enabled on the
890 * device, check through the rest and release it ourselves if necessary.
892 for (i
= 0; i
< vdev
->nr_vectors
; i
++) {
893 if (vdev
->msi_vectors
[i
].use
) {
894 vfio_msix_vector_release(&vdev
->pdev
, i
);
895 msix_vector_unuse(&vdev
->pdev
, i
);
899 if (vdev
->nr_vectors
) {
900 vfio_disable_irqindex(&vdev
->vbasedev
, VFIO_PCI_MSIX_IRQ_INDEX
);
903 vfio_disable_msi_common(vdev
);
905 trace_vfio_disable_msix(vdev
->vbasedev
.name
);
908 static void vfio_disable_msi(VFIOPCIDevice
*vdev
)
910 vfio_disable_irqindex(&vdev
->vbasedev
, VFIO_PCI_MSI_IRQ_INDEX
);
911 vfio_disable_msi_common(vdev
);
913 trace_vfio_disable_msi(vdev
->vbasedev
.name
);
916 static void vfio_update_msi(VFIOPCIDevice
*vdev
)
920 for (i
= 0; i
< vdev
->nr_vectors
; i
++) {
921 VFIOMSIVector
*vector
= &vdev
->msi_vectors
[i
];
924 if (!vector
->use
|| vector
->virq
< 0) {
928 msg
= msi_get_message(&vdev
->pdev
, i
);
929 vfio_update_kvm_msi_virq(vector
, msg
);
933 static void vfio_pci_load_rom(VFIOPCIDevice
*vdev
)
935 struct vfio_region_info reg_info
= {
936 .argsz
= sizeof(reg_info
),
937 .index
= VFIO_PCI_ROM_REGION_INDEX
943 if (ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_GET_REGION_INFO
, ®_info
)) {
944 error_report("vfio: Error getting ROM info: %m");
948 trace_vfio_pci_load_rom(vdev
->vbasedev
.name
, (unsigned long)reg_info
.size
,
949 (unsigned long)reg_info
.offset
,
950 (unsigned long)reg_info
.flags
);
952 vdev
->rom_size
= size
= reg_info
.size
;
953 vdev
->rom_offset
= reg_info
.offset
;
955 if (!vdev
->rom_size
) {
956 vdev
->rom_read_failed
= true;
957 error_report("vfio-pci: Cannot read device rom at "
958 "%s", vdev
->vbasedev
.name
);
959 error_printf("Device option ROM contents are probably invalid "
960 "(check dmesg).\nSkip option ROM probe with rombar=0, "
961 "or load from file with romfile=\n");
965 vdev
->rom
= g_malloc(size
);
966 memset(vdev
->rom
, 0xff, size
);
969 bytes
= pread(vdev
->vbasedev
.fd
, vdev
->rom
+ off
,
970 size
, vdev
->rom_offset
+ off
);
973 } else if (bytes
> 0) {
977 if (errno
== EINTR
|| errno
== EAGAIN
) {
980 error_report("vfio: Error reading device ROM: %m");
986 static uint64_t vfio_rom_read(void *opaque
, hwaddr addr
, unsigned size
)
988 VFIOPCIDevice
*vdev
= opaque
;
997 /* Load the ROM lazily when the guest tries to read it */
998 if (unlikely(!vdev
->rom
&& !vdev
->rom_read_failed
)) {
999 vfio_pci_load_rom(vdev
);
1002 memcpy(&val
, vdev
->rom
+ addr
,
1003 (addr
< vdev
->rom_size
) ? MIN(size
, vdev
->rom_size
- addr
) : 0);
1010 data
= le16_to_cpu(val
.word
);
1013 data
= le32_to_cpu(val
.dword
);
1016 hw_error("vfio: unsupported read size, %d bytes\n", size
);
1020 trace_vfio_rom_read(vdev
->vbasedev
.name
, addr
, size
, data
);
1025 static void vfio_rom_write(void *opaque
, hwaddr addr
,
1026 uint64_t data
, unsigned size
)
1030 static const MemoryRegionOps vfio_rom_ops
= {
1031 .read
= vfio_rom_read
,
1032 .write
= vfio_rom_write
,
1033 .endianness
= DEVICE_LITTLE_ENDIAN
,
1036 static bool vfio_blacklist_opt_rom(VFIOPCIDevice
*vdev
)
1038 PCIDevice
*pdev
= &vdev
->pdev
;
1039 uint16_t vendor_id
, device_id
;
1042 vendor_id
= pci_get_word(pdev
->config
+ PCI_VENDOR_ID
);
1043 device_id
= pci_get_word(pdev
->config
+ PCI_DEVICE_ID
);
1045 while (count
< ARRAY_SIZE(romblacklist
)) {
1046 if (romblacklist
[count
].vendor_id
== vendor_id
&&
1047 romblacklist
[count
].device_id
== device_id
) {
1056 static void vfio_pci_size_rom(VFIOPCIDevice
*vdev
)
1058 uint32_t orig
, size
= cpu_to_le32((uint32_t)PCI_ROM_ADDRESS_MASK
);
1059 off_t offset
= vdev
->config_offset
+ PCI_ROM_ADDRESS
;
1060 DeviceState
*dev
= DEVICE(vdev
);
1062 int fd
= vdev
->vbasedev
.fd
;
1064 if (vdev
->pdev
.romfile
|| !vdev
->pdev
.rom_bar
) {
1065 /* Since pci handles romfile, just print a message and return */
1066 if (vfio_blacklist_opt_rom(vdev
) && vdev
->pdev
.romfile
) {
1067 error_printf("Warning : Device at %04x:%02x:%02x.%x "
1068 "is known to cause system instability issues during "
1069 "option rom execution. "
1070 "Proceeding anyway since user specified romfile\n",
1071 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1072 vdev
->host
.function
);
1078 * Use the same size ROM BAR as the physical device. The contents
1079 * will get filled in later when the guest tries to read it.
1081 if (pread(fd
, &orig
, 4, offset
) != 4 ||
1082 pwrite(fd
, &size
, 4, offset
) != 4 ||
1083 pread(fd
, &size
, 4, offset
) != 4 ||
1084 pwrite(fd
, &orig
, 4, offset
) != 4) {
1085 error_report("%s(%04x:%02x:%02x.%x) failed: %m",
1086 __func__
, vdev
->host
.domain
, vdev
->host
.bus
,
1087 vdev
->host
.slot
, vdev
->host
.function
);
1091 size
= ~(le32_to_cpu(size
) & PCI_ROM_ADDRESS_MASK
) + 1;
1097 if (vfio_blacklist_opt_rom(vdev
)) {
1098 if (dev
->opts
&& qemu_opt_get(dev
->opts
, "rombar")) {
1099 error_printf("Warning : Device at %04x:%02x:%02x.%x "
1100 "is known to cause system instability issues during "
1101 "option rom execution. "
1102 "Proceeding anyway since user specified non zero value for "
1104 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1105 vdev
->host
.function
);
1107 error_printf("Warning : Rom loading for device at "
1108 "%04x:%02x:%02x.%x has been disabled due to "
1109 "system instability issues. "
1110 "Specify rombar=1 or romfile to force\n",
1111 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1112 vdev
->host
.function
);
1117 trace_vfio_pci_size_rom(vdev
->vbasedev
.name
, size
);
1119 snprintf(name
, sizeof(name
), "vfio[%04x:%02x:%02x.%x].rom",
1120 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
1121 vdev
->host
.function
);
1123 memory_region_init_io(&vdev
->pdev
.rom
, OBJECT(vdev
),
1124 &vfio_rom_ops
, vdev
, name
, size
);
1126 pci_register_bar(&vdev
->pdev
, PCI_ROM_SLOT
,
1127 PCI_BASE_ADDRESS_SPACE_MEMORY
, &vdev
->pdev
.rom
);
1129 vdev
->pdev
.has_rom
= true;
1130 vdev
->rom_read_failed
= false;
1133 static void vfio_vga_write(void *opaque
, hwaddr addr
,
1134 uint64_t data
, unsigned size
)
1136 VFIOVGARegion
*region
= opaque
;
1137 VFIOVGA
*vga
= container_of(region
, VFIOVGA
, region
[region
->nr
]);
1144 off_t offset
= vga
->fd_offset
+ region
->offset
+ addr
;
1151 buf
.word
= cpu_to_le16(data
);
1154 buf
.dword
= cpu_to_le32(data
);
1157 hw_error("vfio: unsupported write size, %d bytes", size
);
1161 if (pwrite(vga
->fd
, &buf
, size
, offset
) != size
) {
1162 error_report("%s(,0x%"HWADDR_PRIx
", 0x%"PRIx64
", %d) failed: %m",
1163 __func__
, region
->offset
+ addr
, data
, size
);
1166 trace_vfio_vga_write(region
->offset
+ addr
, data
, size
);
1169 static uint64_t vfio_vga_read(void *opaque
, hwaddr addr
, unsigned size
)
1171 VFIOVGARegion
*region
= opaque
;
1172 VFIOVGA
*vga
= container_of(region
, VFIOVGA
, region
[region
->nr
]);
1180 off_t offset
= vga
->fd_offset
+ region
->offset
+ addr
;
1182 if (pread(vga
->fd
, &buf
, size
, offset
) != size
) {
1183 error_report("%s(,0x%"HWADDR_PRIx
", %d) failed: %m",
1184 __func__
, region
->offset
+ addr
, size
);
1185 return (uint64_t)-1;
1193 data
= le16_to_cpu(buf
.word
);
1196 data
= le32_to_cpu(buf
.dword
);
1199 hw_error("vfio: unsupported read size, %d bytes", size
);
1203 trace_vfio_vga_read(region
->offset
+ addr
, size
, data
);
1208 static const MemoryRegionOps vfio_vga_ops
= {
1209 .read
= vfio_vga_read
,
1210 .write
= vfio_vga_write
,
1211 .endianness
= DEVICE_LITTLE_ENDIAN
,
1215 * Device specific quirks
1218 /* Is range1 fully contained within range2? */
1219 static bool vfio_range_contained(uint64_t first1
, uint64_t len1
,
1220 uint64_t first2
, uint64_t len2
) {
1221 return (first1
>= first2
&& first1
+ len1
<= first2
+ len2
);
1224 static bool vfio_flags_enabled(uint8_t flags
, uint8_t mask
)
1226 return (mask
&& (flags
& mask
) == mask
);
1229 static uint64_t vfio_generic_window_quirk_read(void *opaque
,
1230 hwaddr addr
, unsigned size
)
1232 VFIOQuirk
*quirk
= opaque
;
1233 VFIOPCIDevice
*vdev
= quirk
->vdev
;
1236 if (vfio_flags_enabled(quirk
->data
.flags
, quirk
->data
.read_flags
) &&
1237 ranges_overlap(addr
, size
,
1238 quirk
->data
.data_offset
, quirk
->data
.data_size
)) {
1239 hwaddr offset
= addr
- quirk
->data
.data_offset
;
1241 if (!vfio_range_contained(addr
, size
, quirk
->data
.data_offset
,
1242 quirk
->data
.data_size
)) {
1243 hw_error("%s: window data read not fully contained: %s",
1244 __func__
, memory_region_name(&quirk
->mem
));
1247 data
= vfio_pci_read_config(&vdev
->pdev
,
1248 quirk
->data
.address_val
+ offset
, size
);
1250 trace_vfio_generic_window_quirk_read(memory_region_name(&quirk
->mem
),
1251 vdev
->vbasedev
.name
,
1255 data
= vfio_region_read(&vdev
->bars
[quirk
->data
.bar
].region
,
1256 addr
+ quirk
->data
.base_offset
, size
);
1262 static void vfio_generic_window_quirk_write(void *opaque
, hwaddr addr
,
1263 uint64_t data
, unsigned size
)
1265 VFIOQuirk
*quirk
= opaque
;
1266 VFIOPCIDevice
*vdev
= quirk
->vdev
;
1268 if (ranges_overlap(addr
, size
,
1269 quirk
->data
.address_offset
, quirk
->data
.address_size
)) {
1271 if (addr
!= quirk
->data
.address_offset
) {
1272 hw_error("%s: offset write into address window: %s",
1273 __func__
, memory_region_name(&quirk
->mem
));
1276 if ((data
& ~quirk
->data
.address_mask
) == quirk
->data
.address_match
) {
1277 quirk
->data
.flags
|= quirk
->data
.write_flags
|
1278 quirk
->data
.read_flags
;
1279 quirk
->data
.address_val
= data
& quirk
->data
.address_mask
;
1281 quirk
->data
.flags
&= ~(quirk
->data
.write_flags
|
1282 quirk
->data
.read_flags
);
1286 if (vfio_flags_enabled(quirk
->data
.flags
, quirk
->data
.write_flags
) &&
1287 ranges_overlap(addr
, size
,
1288 quirk
->data
.data_offset
, quirk
->data
.data_size
)) {
1289 hwaddr offset
= addr
- quirk
->data
.data_offset
;
1291 if (!vfio_range_contained(addr
, size
, quirk
->data
.data_offset
,
1292 quirk
->data
.data_size
)) {
1293 hw_error("%s: window data write not fully contained: %s",
1294 __func__
, memory_region_name(&quirk
->mem
));
1297 vfio_pci_write_config(&vdev
->pdev
,
1298 quirk
->data
.address_val
+ offset
, data
, size
);
1299 trace_vfio_generic_window_quirk_write(memory_region_name(&quirk
->mem
),
1300 vdev
->vbasedev
.name
,
1306 vfio_region_write(&vdev
->bars
[quirk
->data
.bar
].region
,
1307 addr
+ quirk
->data
.base_offset
, data
, size
);
1310 static const MemoryRegionOps vfio_generic_window_quirk
= {
1311 .read
= vfio_generic_window_quirk_read
,
1312 .write
= vfio_generic_window_quirk_write
,
1313 .endianness
= DEVICE_LITTLE_ENDIAN
,
1316 static uint64_t vfio_generic_quirk_read(void *opaque
,
1317 hwaddr addr
, unsigned size
)
1319 VFIOQuirk
*quirk
= opaque
;
1320 VFIOPCIDevice
*vdev
= quirk
->vdev
;
1321 hwaddr base
= quirk
->data
.address_match
& TARGET_PAGE_MASK
;
1322 hwaddr offset
= quirk
->data
.address_match
& ~TARGET_PAGE_MASK
;
1325 if (vfio_flags_enabled(quirk
->data
.flags
, quirk
->data
.read_flags
) &&
1326 ranges_overlap(addr
, size
, offset
, quirk
->data
.address_mask
+ 1)) {
1327 if (!vfio_range_contained(addr
, size
, offset
,
1328 quirk
->data
.address_mask
+ 1)) {
1329 hw_error("%s: read not fully contained: %s",
1330 __func__
, memory_region_name(&quirk
->mem
));
1333 data
= vfio_pci_read_config(&vdev
->pdev
, addr
- offset
, size
);
1335 trace_vfio_generic_quirk_read(memory_region_name(&quirk
->mem
),
1336 vdev
->vbasedev
.name
, quirk
->data
.bar
,
1337 addr
+ base
, size
, data
);
1339 data
= vfio_region_read(&vdev
->bars
[quirk
->data
.bar
].region
,
1346 static void vfio_generic_quirk_write(void *opaque
, hwaddr addr
,
1347 uint64_t data
, unsigned size
)
1349 VFIOQuirk
*quirk
= opaque
;
1350 VFIOPCIDevice
*vdev
= quirk
->vdev
;
1351 hwaddr base
= quirk
->data
.address_match
& TARGET_PAGE_MASK
;
1352 hwaddr offset
= quirk
->data
.address_match
& ~TARGET_PAGE_MASK
;
1354 if (vfio_flags_enabled(quirk
->data
.flags
, quirk
->data
.write_flags
) &&
1355 ranges_overlap(addr
, size
, offset
, quirk
->data
.address_mask
+ 1)) {
1356 if (!vfio_range_contained(addr
, size
, offset
,
1357 quirk
->data
.address_mask
+ 1)) {
1358 hw_error("%s: write not fully contained: %s",
1359 __func__
, memory_region_name(&quirk
->mem
));
1362 vfio_pci_write_config(&vdev
->pdev
, addr
- offset
, data
, size
);
1364 trace_vfio_generic_quirk_write(memory_region_name(&quirk
->mem
),
1365 vdev
->vbasedev
.name
, quirk
->data
.bar
,
1366 addr
+ base
, data
, size
);
1368 vfio_region_write(&vdev
->bars
[quirk
->data
.bar
].region
,
1369 addr
+ base
, data
, size
);
1373 static const MemoryRegionOps vfio_generic_quirk
= {
1374 .read
= vfio_generic_quirk_read
,
1375 .write
= vfio_generic_quirk_write
,
1376 .endianness
= DEVICE_LITTLE_ENDIAN
,
1379 #define PCI_VENDOR_ID_ATI 0x1002
1382 * Radeon HD cards (HD5450 & HD7850) report the upper byte of the I/O port BAR
1383 * through VGA register 0x3c3. On newer cards, the I/O port BAR is always
1384 * BAR4 (older cards like the X550 used BAR1, but we don't care to support
1385 * those). Note that on bare metal, a read of 0x3c3 doesn't always return the
1386 * I/O port BAR address. Originally this was coded to return the virtual BAR
1387 * address only if the physical register read returns the actual BAR address,
1388 * but users have reported greater success if we return the virtual address
1391 static uint64_t vfio_ati_3c3_quirk_read(void *opaque
,
1392 hwaddr addr
, unsigned size
)
1394 VFIOQuirk
*quirk
= opaque
;
1395 VFIOPCIDevice
*vdev
= quirk
->vdev
;
1396 uint64_t data
= vfio_pci_read_config(&vdev
->pdev
,
1397 PCI_BASE_ADDRESS_0
+ (4 * 4) + 1,
1399 trace_vfio_ati_3c3_quirk_read(data
);
1404 static const MemoryRegionOps vfio_ati_3c3_quirk
= {
1405 .read
= vfio_ati_3c3_quirk_read
,
1406 .endianness
= DEVICE_LITTLE_ENDIAN
,
1409 static void vfio_vga_probe_ati_3c3_quirk(VFIOPCIDevice
*vdev
)
1411 PCIDevice
*pdev
= &vdev
->pdev
;
1414 if (pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_ATI
) {
1419 * As long as the BAR is >= 256 bytes it will be aligned such that the
1420 * lower byte is always zero. Filter out anything else, if it exists.
1422 if (!vdev
->bars
[4].ioport
|| vdev
->bars
[4].region
.size
< 256) {
1426 quirk
= g_malloc0(sizeof(*quirk
));
1429 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
), &vfio_ati_3c3_quirk
, quirk
,
1430 "vfio-ati-3c3-quirk", 1);
1431 memory_region_add_subregion(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].mem
,
1432 3 /* offset 3 bytes from 0x3c0 */, &quirk
->mem
);
1434 QLIST_INSERT_HEAD(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].quirks
,
1437 trace_vfio_vga_probe_ati_3c3_quirk(vdev
->vbasedev
.name
);
1441 * Newer ATI/AMD devices, including HD5450 and HD7850, have a window to PCI
1442 * config space through MMIO BAR2 at offset 0x4000. Nothing seems to access
1443 * the MMIO space directly, but a window to this space is provided through
1444 * I/O port BAR4. Offset 0x0 is the address register and offset 0x4 is the
1445 * data register. When the address is programmed to a range of 0x4000-0x4fff
1446 * PCI configuration space is available. Experimentation seems to indicate
1447 * that only read-only access is provided, but we drop writes when the window
1448 * is enabled to config space nonetheless.
1450 static void vfio_probe_ati_bar4_window_quirk(VFIOPCIDevice
*vdev
, int nr
)
1452 PCIDevice
*pdev
= &vdev
->pdev
;
1455 if (!vdev
->has_vga
|| nr
!= 4 ||
1456 pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_ATI
) {
1460 quirk
= g_malloc0(sizeof(*quirk
));
1462 quirk
->data
.address_size
= 4;
1463 quirk
->data
.data_offset
= 4;
1464 quirk
->data
.data_size
= 4;
1465 quirk
->data
.address_match
= 0x4000;
1466 quirk
->data
.address_mask
= PCIE_CONFIG_SPACE_SIZE
- 1;
1467 quirk
->data
.bar
= nr
;
1468 quirk
->data
.read_flags
= quirk
->data
.write_flags
= 1;
1470 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
),
1471 &vfio_generic_window_quirk
, quirk
,
1472 "vfio-ati-bar4-window-quirk", 8);
1473 memory_region_add_subregion_overlap(&vdev
->bars
[nr
].region
.mem
,
1474 quirk
->data
.base_offset
, &quirk
->mem
, 1);
1476 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
1478 trace_vfio_probe_ati_bar4_window_quirk(vdev
->vbasedev
.name
);
1481 #define PCI_VENDOR_ID_REALTEK 0x10ec
1484 * RTL8168 devices have a backdoor that can access the MSI-X table. At BAR2
1485 * offset 0x70 there is a dword data register, offset 0x74 is a dword address
1486 * register. According to the Linux r8169 driver, the MSI-X table is addressed
1487 * when the "type" portion of the address register is set to 0x1. This appears
1488 * to be bits 16:30. Bit 31 is both a write indicator and some sort of
1489 * "address latched" indicator. Bits 12:15 are a mask field, which we can
1490 * ignore because the MSI-X table should always be accessed as a dword (full
1491 * mask). Bits 0:11 is offset within the type.
1495 * Read from MSI-X table offset 0
1496 * vfio: vfio_bar_write(0000:05:00.0:BAR2+0x74, 0x1f000, 4) // store read addr
1497 * vfio: vfio_bar_read(0000:05:00.0:BAR2+0x74, 4) = 0x8001f000 // latch
1498 * vfio: vfio_bar_read(0000:05:00.0:BAR2+0x70, 4) = 0xfee00398 // read data
1500 * Write 0xfee00000 to MSI-X table offset 0
1501 * vfio: vfio_bar_write(0000:05:00.0:BAR2+0x70, 0xfee00000, 4) // write data
1502 * vfio: vfio_bar_write(0000:05:00.0:BAR2+0x74, 0x8001f000, 4) // do write
1503 * vfio: vfio_bar_read(0000:05:00.0:BAR2+0x74, 4) = 0x1f000 // complete
1506 static uint64_t vfio_rtl8168_window_quirk_read(void *opaque
,
1507 hwaddr addr
, unsigned size
)
1509 VFIOQuirk
*quirk
= opaque
;
1510 VFIOPCIDevice
*vdev
= quirk
->vdev
;
1513 case 4: /* address */
1514 if (quirk
->data
.flags
) {
1515 trace_vfio_rtl8168_window_quirk_read_fake(
1516 memory_region_name(&quirk
->mem
),
1517 vdev
->vbasedev
.name
);
1519 return quirk
->data
.address_match
^ 0x80000000U
;
1523 if (quirk
->data
.flags
) {
1526 trace_vfio_rtl8168_window_quirk_read_table(
1527 memory_region_name(&quirk
->mem
),
1528 vdev
->vbasedev
.name
);
1530 if (!(vdev
->pdev
.cap_present
& QEMU_PCI_CAP_MSIX
)) {
1534 memory_region_dispatch_read(&vdev
->pdev
.msix_table_mmio
,
1535 (hwaddr
)(quirk
->data
.address_match
1539 MEMTXATTRS_UNSPECIFIED
);
1544 trace_vfio_rtl8168_window_quirk_read_direct(memory_region_name(&quirk
->mem
),
1545 vdev
->vbasedev
.name
);
1547 return vfio_region_read(&vdev
->bars
[quirk
->data
.bar
].region
,
1551 static void vfio_rtl8168_window_quirk_write(void *opaque
, hwaddr addr
,
1552 uint64_t data
, unsigned size
)
1554 VFIOQuirk
*quirk
= opaque
;
1555 VFIOPCIDevice
*vdev
= quirk
->vdev
;
1558 case 4: /* address */
1559 if ((data
& 0x7fff0000) == 0x10000) {
1560 if (data
& 0x80000000U
&&
1561 vdev
->pdev
.cap_present
& QEMU_PCI_CAP_MSIX
) {
1563 trace_vfio_rtl8168_window_quirk_write_table(
1564 memory_region_name(&quirk
->mem
),
1565 vdev
->vbasedev
.name
);
1567 memory_region_dispatch_write(&vdev
->pdev
.msix_table_mmio
,
1568 (hwaddr
)(data
& 0xfff),
1569 (uint64_t)quirk
->data
.address_mask
,
1570 size
, MEMTXATTRS_UNSPECIFIED
);
1573 quirk
->data
.flags
= 1;
1574 quirk
->data
.address_match
= data
;
1578 quirk
->data
.flags
= 0;
1581 quirk
->data
.address_mask
= data
;
1585 trace_vfio_rtl8168_window_quirk_write_direct(
1586 memory_region_name(&quirk
->mem
),
1587 vdev
->vbasedev
.name
);
1589 vfio_region_write(&vdev
->bars
[quirk
->data
.bar
].region
,
1590 addr
+ 0x70, data
, size
);
1593 static const MemoryRegionOps vfio_rtl8168_window_quirk
= {
1594 .read
= vfio_rtl8168_window_quirk_read
,
1595 .write
= vfio_rtl8168_window_quirk_write
,
1597 .min_access_size
= 4,
1598 .max_access_size
= 4,
1601 .endianness
= DEVICE_LITTLE_ENDIAN
,
1604 static void vfio_probe_rtl8168_bar2_window_quirk(VFIOPCIDevice
*vdev
, int nr
)
1606 PCIDevice
*pdev
= &vdev
->pdev
;
1609 if (pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_REALTEK
||
1610 pci_get_word(pdev
->config
+ PCI_DEVICE_ID
) != 0x8168 || nr
!= 2) {
1614 quirk
= g_malloc0(sizeof(*quirk
));
1616 quirk
->data
.bar
= nr
;
1618 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
), &vfio_rtl8168_window_quirk
,
1619 quirk
, "vfio-rtl8168-window-quirk", 8);
1620 memory_region_add_subregion_overlap(&vdev
->bars
[nr
].region
.mem
,
1621 0x70, &quirk
->mem
, 1);
1623 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
1625 trace_vfio_probe_rtl8168_bar2_window_quirk(vdev
->vbasedev
.name
);
1628 * Trap the BAR2 MMIO window to config space as well.
1630 static void vfio_probe_ati_bar2_4000_quirk(VFIOPCIDevice
*vdev
, int nr
)
1632 PCIDevice
*pdev
= &vdev
->pdev
;
1635 /* Only enable on newer devices where BAR2 is 64bit */
1636 if (!vdev
->has_vga
|| nr
!= 2 || !vdev
->bars
[2].mem64
||
1637 pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_ATI
) {
1641 quirk
= g_malloc0(sizeof(*quirk
));
1643 quirk
->data
.flags
= quirk
->data
.read_flags
= quirk
->data
.write_flags
= 1;
1644 quirk
->data
.address_match
= 0x4000;
1645 quirk
->data
.address_mask
= PCIE_CONFIG_SPACE_SIZE
- 1;
1646 quirk
->data
.bar
= nr
;
1648 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
), &vfio_generic_quirk
, quirk
,
1649 "vfio-ati-bar2-4000-quirk",
1650 TARGET_PAGE_ALIGN(quirk
->data
.address_mask
+ 1));
1651 memory_region_add_subregion_overlap(&vdev
->bars
[nr
].region
.mem
,
1652 quirk
->data
.address_match
& TARGET_PAGE_MASK
,
1655 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
1657 trace_vfio_probe_ati_bar2_4000_quirk(vdev
->vbasedev
.name
);
1661 * Older ATI/AMD cards like the X550 have a similar window to that above.
1662 * I/O port BAR1 provides a window to a mirror of PCI config space located
1663 * in BAR2 at offset 0xf00. We don't care to support such older cards, but
1664 * note it for future reference.
1667 #define PCI_VENDOR_ID_NVIDIA 0x10de
1670 * Nvidia has several different methods to get to config space, the
1671 * nouveu project has several of these documented here:
1672 * https://github.com/pathscale/envytools/tree/master/hwdocs
1674 * The first quirk is actually not documented in envytools and is found
1675 * on 10de:01d1 (NVIDIA Corporation G72 [GeForce 7300 LE]). This is an
1676 * NV46 chipset. The backdoor uses the legacy VGA I/O ports to access
1677 * the mirror of PCI config space found at BAR0 offset 0x1800. The access
1678 * sequence first writes 0x338 to I/O port 0x3d4. The target offset is
1679 * then written to 0x3d0. Finally 0x538 is written for a read and 0x738
1680 * is written for a write to 0x3d4. The BAR0 offset is then accessible
1681 * through 0x3d0. This quirk doesn't seem to be necessary on newer cards
1682 * that use the I/O port BAR5 window but it doesn't hurt to leave it.
1692 static uint64_t vfio_nvidia_3d0_quirk_read(void *opaque
,
1693 hwaddr addr
, unsigned size
)
1695 VFIOQuirk
*quirk
= opaque
;
1696 VFIOPCIDevice
*vdev
= quirk
->vdev
;
1697 PCIDevice
*pdev
= &vdev
->pdev
;
1698 uint64_t data
= vfio_vga_read(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
],
1699 addr
+ quirk
->data
.base_offset
, size
);
1701 if (quirk
->data
.flags
== NV_3D0_READ
&& addr
== quirk
->data
.data_offset
) {
1702 data
= vfio_pci_read_config(pdev
, quirk
->data
.address_val
, size
);
1703 trace_vfio_nvidia_3d0_quirk_read(size
, data
);
1706 quirk
->data
.flags
= NV_3D0_NONE
;
1711 static void vfio_nvidia_3d0_quirk_write(void *opaque
, hwaddr addr
,
1712 uint64_t data
, unsigned size
)
1714 VFIOQuirk
*quirk
= opaque
;
1715 VFIOPCIDevice
*vdev
= quirk
->vdev
;
1716 PCIDevice
*pdev
= &vdev
->pdev
;
1718 switch (quirk
->data
.flags
) {
1720 if (addr
== quirk
->data
.address_offset
&& data
== 0x338) {
1721 quirk
->data
.flags
= NV_3D0_SELECT
;
1725 quirk
->data
.flags
= NV_3D0_NONE
;
1726 if (addr
== quirk
->data
.data_offset
&&
1727 (data
& ~quirk
->data
.address_mask
) == quirk
->data
.address_match
) {
1728 quirk
->data
.flags
= NV_3D0_WINDOW
;
1729 quirk
->data
.address_val
= data
& quirk
->data
.address_mask
;
1733 quirk
->data
.flags
= NV_3D0_NONE
;
1734 if (addr
== quirk
->data
.address_offset
) {
1735 if (data
== 0x538) {
1736 quirk
->data
.flags
= NV_3D0_READ
;
1737 } else if (data
== 0x738) {
1738 quirk
->data
.flags
= NV_3D0_WRITE
;
1743 quirk
->data
.flags
= NV_3D0_NONE
;
1744 if (addr
== quirk
->data
.data_offset
) {
1745 vfio_pci_write_config(pdev
, quirk
->data
.address_val
, data
, size
);
1746 trace_vfio_nvidia_3d0_quirk_write(data
, size
);
1752 vfio_vga_write(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
],
1753 addr
+ quirk
->data
.base_offset
, data
, size
);
1756 static const MemoryRegionOps vfio_nvidia_3d0_quirk
= {
1757 .read
= vfio_nvidia_3d0_quirk_read
,
1758 .write
= vfio_nvidia_3d0_quirk_write
,
1759 .endianness
= DEVICE_LITTLE_ENDIAN
,
1762 static void vfio_vga_probe_nvidia_3d0_quirk(VFIOPCIDevice
*vdev
)
1764 PCIDevice
*pdev
= &vdev
->pdev
;
1767 if (pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_NVIDIA
||
1768 !vdev
->bars
[1].region
.size
) {
1772 quirk
= g_malloc0(sizeof(*quirk
));
1774 quirk
->data
.base_offset
= 0x10;
1775 quirk
->data
.address_offset
= 4;
1776 quirk
->data
.address_size
= 2;
1777 quirk
->data
.address_match
= 0x1800;
1778 quirk
->data
.address_mask
= PCI_CONFIG_SPACE_SIZE
- 1;
1779 quirk
->data
.data_offset
= 0;
1780 quirk
->data
.data_size
= 4;
1782 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
), &vfio_nvidia_3d0_quirk
,
1783 quirk
, "vfio-nvidia-3d0-quirk", 6);
1784 memory_region_add_subregion(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].mem
,
1785 quirk
->data
.base_offset
, &quirk
->mem
);
1787 QLIST_INSERT_HEAD(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].quirks
,
1790 trace_vfio_vga_probe_nvidia_3d0_quirk(vdev
->vbasedev
.name
);
1794 * The second quirk is documented in envytools. The I/O port BAR5 is just
1795 * a set of address/data ports to the MMIO BARs. The BAR we care about is
1796 * again BAR0. This backdoor is apparently a bit newer than the one above
1797 * so we need to not only trap 256 bytes @0x1800, but all of PCI config
1798 * space, including extended space is available at the 4k @0x88000.
1801 NV_BAR5_ADDRESS
= 0x1,
1802 NV_BAR5_ENABLE
= 0x2,
1803 NV_BAR5_MASTER
= 0x4,
1804 NV_BAR5_VALID
= 0x7,
1807 static void vfio_nvidia_bar5_window_quirk_write(void *opaque
, hwaddr addr
,
1808 uint64_t data
, unsigned size
)
1810 VFIOQuirk
*quirk
= opaque
;
1815 quirk
->data
.flags
|= NV_BAR5_MASTER
;
1817 quirk
->data
.flags
&= ~NV_BAR5_MASTER
;
1822 quirk
->data
.flags
|= NV_BAR5_ENABLE
;
1824 quirk
->data
.flags
&= ~NV_BAR5_ENABLE
;
1828 if (quirk
->data
.flags
& NV_BAR5_MASTER
) {
1829 if ((data
& ~0xfff) == 0x88000) {
1830 quirk
->data
.flags
|= NV_BAR5_ADDRESS
;
1831 quirk
->data
.address_val
= data
& 0xfff;
1832 } else if ((data
& ~0xff) == 0x1800) {
1833 quirk
->data
.flags
|= NV_BAR5_ADDRESS
;
1834 quirk
->data
.address_val
= data
& 0xff;
1836 quirk
->data
.flags
&= ~NV_BAR5_ADDRESS
;
1842 vfio_generic_window_quirk_write(opaque
, addr
, data
, size
);
1845 static const MemoryRegionOps vfio_nvidia_bar5_window_quirk
= {
1846 .read
= vfio_generic_window_quirk_read
,
1847 .write
= vfio_nvidia_bar5_window_quirk_write
,
1848 .valid
.min_access_size
= 4,
1849 .endianness
= DEVICE_LITTLE_ENDIAN
,
1852 static void vfio_probe_nvidia_bar5_window_quirk(VFIOPCIDevice
*vdev
, int nr
)
1854 PCIDevice
*pdev
= &vdev
->pdev
;
1857 if (!vdev
->has_vga
|| nr
!= 5 ||
1858 pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_NVIDIA
) {
1862 quirk
= g_malloc0(sizeof(*quirk
));
1864 quirk
->data
.read_flags
= quirk
->data
.write_flags
= NV_BAR5_VALID
;
1865 quirk
->data
.address_offset
= 0x8;
1866 quirk
->data
.address_size
= 0; /* actually 4, but avoids generic code */
1867 quirk
->data
.data_offset
= 0xc;
1868 quirk
->data
.data_size
= 4;
1869 quirk
->data
.bar
= nr
;
1871 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
),
1872 &vfio_nvidia_bar5_window_quirk
, quirk
,
1873 "vfio-nvidia-bar5-window-quirk", 16);
1874 memory_region_add_subregion_overlap(&vdev
->bars
[nr
].region
.mem
,
1877 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
1879 trace_vfio_probe_nvidia_bar5_window_quirk(vdev
->vbasedev
.name
);
1882 static void vfio_nvidia_88000_quirk_write(void *opaque
, hwaddr addr
,
1883 uint64_t data
, unsigned size
)
1885 VFIOQuirk
*quirk
= opaque
;
1886 VFIOPCIDevice
*vdev
= quirk
->vdev
;
1887 PCIDevice
*pdev
= &vdev
->pdev
;
1888 hwaddr base
= quirk
->data
.address_match
& TARGET_PAGE_MASK
;
1890 vfio_generic_quirk_write(opaque
, addr
, data
, size
);
1893 * Nvidia seems to acknowledge MSI interrupts by writing 0xff to the
1894 * MSI capability ID register. Both the ID and next register are
1895 * read-only, so we allow writes covering either of those to real hw.
1896 * NB - only fixed for the 0x88000 MMIO window.
1898 if ((pdev
->cap_present
& QEMU_PCI_CAP_MSI
) &&
1899 vfio_range_contained(addr
, size
, pdev
->msi_cap
, PCI_MSI_FLAGS
)) {
1900 vfio_region_write(&vdev
->bars
[quirk
->data
.bar
].region
,
1901 addr
+ base
, data
, size
);
1905 static const MemoryRegionOps vfio_nvidia_88000_quirk
= {
1906 .read
= vfio_generic_quirk_read
,
1907 .write
= vfio_nvidia_88000_quirk_write
,
1908 .endianness
= DEVICE_LITTLE_ENDIAN
,
1912 * Finally, BAR0 itself. We want to redirect any accesses to either
1913 * 0x1800 or 0x88000 through the PCI config space access functions.
1915 * NB - quirk at a page granularity or else they don't seem to work when
1918 * Here's offset 0x88000...
1920 static void vfio_probe_nvidia_bar0_88000_quirk(VFIOPCIDevice
*vdev
, int nr
)
1922 PCIDevice
*pdev
= &vdev
->pdev
;
1924 uint16_t vendor
, class;
1926 vendor
= pci_get_word(pdev
->config
+ PCI_VENDOR_ID
);
1927 class = pci_get_word(pdev
->config
+ PCI_CLASS_DEVICE
);
1929 if (nr
!= 0 || vendor
!= PCI_VENDOR_ID_NVIDIA
||
1930 class != PCI_CLASS_DISPLAY_VGA
) {
1934 quirk
= g_malloc0(sizeof(*quirk
));
1936 quirk
->data
.flags
= quirk
->data
.read_flags
= quirk
->data
.write_flags
= 1;
1937 quirk
->data
.address_match
= 0x88000;
1938 quirk
->data
.address_mask
= PCIE_CONFIG_SPACE_SIZE
- 1;
1939 quirk
->data
.bar
= nr
;
1941 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
), &vfio_nvidia_88000_quirk
,
1942 quirk
, "vfio-nvidia-bar0-88000-quirk",
1943 TARGET_PAGE_ALIGN(quirk
->data
.address_mask
+ 1));
1944 memory_region_add_subregion_overlap(&vdev
->bars
[nr
].region
.mem
,
1945 quirk
->data
.address_match
& TARGET_PAGE_MASK
,
1948 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
1950 trace_vfio_probe_nvidia_bar0_88000_quirk(vdev
->vbasedev
.name
);
1954 * And here's the same for BAR0 offset 0x1800...
1956 static void vfio_probe_nvidia_bar0_1800_quirk(VFIOPCIDevice
*vdev
, int nr
)
1958 PCIDevice
*pdev
= &vdev
->pdev
;
1961 if (!vdev
->has_vga
|| nr
!= 0 ||
1962 pci_get_word(pdev
->config
+ PCI_VENDOR_ID
) != PCI_VENDOR_ID_NVIDIA
) {
1966 /* Log the chipset ID */
1967 trace_vfio_probe_nvidia_bar0_1800_quirk_id(
1968 (unsigned int)(vfio_region_read(&vdev
->bars
[0].region
, 0, 4) >> 20)
1971 quirk
= g_malloc0(sizeof(*quirk
));
1973 quirk
->data
.flags
= quirk
->data
.read_flags
= quirk
->data
.write_flags
= 1;
1974 quirk
->data
.address_match
= 0x1800;
1975 quirk
->data
.address_mask
= PCI_CONFIG_SPACE_SIZE
- 1;
1976 quirk
->data
.bar
= nr
;
1978 memory_region_init_io(&quirk
->mem
, OBJECT(vdev
), &vfio_generic_quirk
, quirk
,
1979 "vfio-nvidia-bar0-1800-quirk",
1980 TARGET_PAGE_ALIGN(quirk
->data
.address_mask
+ 1));
1981 memory_region_add_subregion_overlap(&vdev
->bars
[nr
].region
.mem
,
1982 quirk
->data
.address_match
& TARGET_PAGE_MASK
,
1985 QLIST_INSERT_HEAD(&vdev
->bars
[nr
].quirks
, quirk
, next
);
1987 trace_vfio_probe_nvidia_bar0_1800_quirk(vdev
->vbasedev
.name
);
1991 * TODO - Some Nvidia devices provide config access to their companion HDA
1992 * device and even to their parent bridge via these config space mirrors.
1993 * Add quirks for those regions.
1997 * Common quirk probe entry points.
1999 static void vfio_vga_quirk_setup(VFIOPCIDevice
*vdev
)
2001 vfio_vga_probe_ati_3c3_quirk(vdev
);
2002 vfio_vga_probe_nvidia_3d0_quirk(vdev
);
2005 static void vfio_vga_quirk_teardown(VFIOPCIDevice
*vdev
)
2010 for (i
= 0; i
< ARRAY_SIZE(vdev
->vga
.region
); i
++) {
2011 QLIST_FOREACH(quirk
, &vdev
->vga
.region
[i
].quirks
, next
) {
2012 memory_region_del_subregion(&vdev
->vga
.region
[i
].mem
, &quirk
->mem
);
2017 static void vfio_vga_quirk_free(VFIOPCIDevice
*vdev
)
2021 for (i
= 0; i
< ARRAY_SIZE(vdev
->vga
.region
); i
++) {
2022 while (!QLIST_EMPTY(&vdev
->vga
.region
[i
].quirks
)) {
2023 VFIOQuirk
*quirk
= QLIST_FIRST(&vdev
->vga
.region
[i
].quirks
);
2024 object_unparent(OBJECT(&quirk
->mem
));
2025 QLIST_REMOVE(quirk
, next
);
2031 static void vfio_bar_quirk_setup(VFIOPCIDevice
*vdev
, int nr
)
2033 vfio_probe_ati_bar4_window_quirk(vdev
, nr
);
2034 vfio_probe_ati_bar2_4000_quirk(vdev
, nr
);
2035 vfio_probe_nvidia_bar5_window_quirk(vdev
, nr
);
2036 vfio_probe_nvidia_bar0_88000_quirk(vdev
, nr
);
2037 vfio_probe_nvidia_bar0_1800_quirk(vdev
, nr
);
2038 vfio_probe_rtl8168_bar2_window_quirk(vdev
, nr
);
2041 static void vfio_bar_quirk_teardown(VFIOPCIDevice
*vdev
, int nr
)
2043 VFIOBAR
*bar
= &vdev
->bars
[nr
];
2046 QLIST_FOREACH(quirk
, &bar
->quirks
, next
) {
2047 memory_region_del_subregion(&bar
->region
.mem
, &quirk
->mem
);
2051 static void vfio_bar_quirk_free(VFIOPCIDevice
*vdev
, int nr
)
2053 VFIOBAR
*bar
= &vdev
->bars
[nr
];
2055 while (!QLIST_EMPTY(&bar
->quirks
)) {
2056 VFIOQuirk
*quirk
= QLIST_FIRST(&bar
->quirks
);
2057 object_unparent(OBJECT(&quirk
->mem
));
2058 QLIST_REMOVE(quirk
, next
);
2066 static uint32_t vfio_pci_read_config(PCIDevice
*pdev
, uint32_t addr
, int len
)
2068 VFIOPCIDevice
*vdev
= DO_UPCAST(VFIOPCIDevice
, pdev
, pdev
);
2069 uint32_t emu_bits
= 0, emu_val
= 0, phys_val
= 0, val
;
2071 memcpy(&emu_bits
, vdev
->emulated_config_bits
+ addr
, len
);
2072 emu_bits
= le32_to_cpu(emu_bits
);
2075 emu_val
= pci_default_read_config(pdev
, addr
, len
);
2078 if (~emu_bits
& (0xffffffffU
>> (32 - len
* 8))) {
2081 ret
= pread(vdev
->vbasedev
.fd
, &phys_val
, len
,
2082 vdev
->config_offset
+ addr
);
2084 error_report("%s(%04x:%02x:%02x.%x, 0x%x, 0x%x) failed: %m",
2085 __func__
, vdev
->host
.domain
, vdev
->host
.bus
,
2086 vdev
->host
.slot
, vdev
->host
.function
, addr
, len
);
2089 phys_val
= le32_to_cpu(phys_val
);
2092 val
= (emu_val
& emu_bits
) | (phys_val
& ~emu_bits
);
2094 trace_vfio_pci_read_config(vdev
->vbasedev
.name
, addr
, len
, val
);
2099 static void vfio_pci_write_config(PCIDevice
*pdev
, uint32_t addr
,
2100 uint32_t val
, int len
)
2102 VFIOPCIDevice
*vdev
= DO_UPCAST(VFIOPCIDevice
, pdev
, pdev
);
2103 uint32_t val_le
= cpu_to_le32(val
);
2105 trace_vfio_pci_write_config(vdev
->vbasedev
.name
, addr
, val
, len
);
2107 /* Write everything to VFIO, let it filter out what we can't write */
2108 if (pwrite(vdev
->vbasedev
.fd
, &val_le
, len
, vdev
->config_offset
+ addr
)
2110 error_report("%s(%04x:%02x:%02x.%x, 0x%x, 0x%x, 0x%x) failed: %m",
2111 __func__
, vdev
->host
.domain
, vdev
->host
.bus
,
2112 vdev
->host
.slot
, vdev
->host
.function
, addr
, val
, len
);
2115 /* MSI/MSI-X Enabling/Disabling */
2116 if (pdev
->cap_present
& QEMU_PCI_CAP_MSI
&&
2117 ranges_overlap(addr
, len
, pdev
->msi_cap
, vdev
->msi_cap_size
)) {
2118 int is_enabled
, was_enabled
= msi_enabled(pdev
);
2120 pci_default_write_config(pdev
, addr
, val
, len
);
2122 is_enabled
= msi_enabled(pdev
);
2126 vfio_enable_msi(vdev
);
2130 vfio_disable_msi(vdev
);
2132 vfio_update_msi(vdev
);
2135 } else if (pdev
->cap_present
& QEMU_PCI_CAP_MSIX
&&
2136 ranges_overlap(addr
, len
, pdev
->msix_cap
, MSIX_CAP_LENGTH
)) {
2137 int is_enabled
, was_enabled
= msix_enabled(pdev
);
2139 pci_default_write_config(pdev
, addr
, val
, len
);
2141 is_enabled
= msix_enabled(pdev
);
2143 if (!was_enabled
&& is_enabled
) {
2144 vfio_enable_msix(vdev
);
2145 } else if (was_enabled
&& !is_enabled
) {
2146 vfio_disable_msix(vdev
);
2149 /* Write everything to QEMU to keep emulated bits correct */
2150 pci_default_write_config(pdev
, addr
, val
, len
);
2157 static void vfio_disable_interrupts(VFIOPCIDevice
*vdev
)
2160 * More complicated than it looks. Disabling MSI/X transitions the
2161 * device to INTx mode (if supported). Therefore we need to first
2162 * disable MSI/X and then cleanup by disabling INTx.
2164 if (vdev
->interrupt
== VFIO_INT_MSIX
) {
2165 vfio_disable_msix(vdev
);
2166 } else if (vdev
->interrupt
== VFIO_INT_MSI
) {
2167 vfio_disable_msi(vdev
);
2170 if (vdev
->interrupt
== VFIO_INT_INTx
) {
2171 vfio_disable_intx(vdev
);
2175 static int vfio_setup_msi(VFIOPCIDevice
*vdev
, int pos
)
2178 bool msi_64bit
, msi_maskbit
;
2181 if (pread(vdev
->vbasedev
.fd
, &ctrl
, sizeof(ctrl
),
2182 vdev
->config_offset
+ pos
+ PCI_CAP_FLAGS
) != sizeof(ctrl
)) {
2185 ctrl
= le16_to_cpu(ctrl
);
2187 msi_64bit
= !!(ctrl
& PCI_MSI_FLAGS_64BIT
);
2188 msi_maskbit
= !!(ctrl
& PCI_MSI_FLAGS_MASKBIT
);
2189 entries
= 1 << ((ctrl
& PCI_MSI_FLAGS_QMASK
) >> 1);
2191 trace_vfio_setup_msi(vdev
->vbasedev
.name
, pos
);
2193 ret
= msi_init(&vdev
->pdev
, pos
, entries
, msi_64bit
, msi_maskbit
);
2195 if (ret
== -ENOTSUP
) {
2198 error_report("vfio: msi_init failed");
2201 vdev
->msi_cap_size
= 0xa + (msi_maskbit
? 0xa : 0) + (msi_64bit
? 0x4 : 0);
2207 * We don't have any control over how pci_add_capability() inserts
2208 * capabilities into the chain. In order to setup MSI-X we need a
2209 * MemoryRegion for the BAR. In order to setup the BAR and not
2210 * attempt to mmap the MSI-X table area, which VFIO won't allow, we
2211 * need to first look for where the MSI-X table lives. So we
2212 * unfortunately split MSI-X setup across two functions.
2214 static int vfio_early_setup_msix(VFIOPCIDevice
*vdev
)
2218 uint32_t table
, pba
;
2219 int fd
= vdev
->vbasedev
.fd
;
2221 pos
= pci_find_capability(&vdev
->pdev
, PCI_CAP_ID_MSIX
);
2226 if (pread(fd
, &ctrl
, sizeof(ctrl
),
2227 vdev
->config_offset
+ pos
+ PCI_CAP_FLAGS
) != sizeof(ctrl
)) {
2231 if (pread(fd
, &table
, sizeof(table
),
2232 vdev
->config_offset
+ pos
+ PCI_MSIX_TABLE
) != sizeof(table
)) {
2236 if (pread(fd
, &pba
, sizeof(pba
),
2237 vdev
->config_offset
+ pos
+ PCI_MSIX_PBA
) != sizeof(pba
)) {
2241 ctrl
= le16_to_cpu(ctrl
);
2242 table
= le32_to_cpu(table
);
2243 pba
= le32_to_cpu(pba
);
2245 vdev
->msix
= g_malloc0(sizeof(*(vdev
->msix
)));
2246 vdev
->msix
->table_bar
= table
& PCI_MSIX_FLAGS_BIRMASK
;
2247 vdev
->msix
->table_offset
= table
& ~PCI_MSIX_FLAGS_BIRMASK
;
2248 vdev
->msix
->pba_bar
= pba
& PCI_MSIX_FLAGS_BIRMASK
;
2249 vdev
->msix
->pba_offset
= pba
& ~PCI_MSIX_FLAGS_BIRMASK
;
2250 vdev
->msix
->entries
= (ctrl
& PCI_MSIX_FLAGS_QSIZE
) + 1;
2253 * Test the size of the pba_offset variable and catch if it extends outside
2254 * of the specified BAR. If it is the case, we need to apply a hardware
2255 * specific quirk if the device is known or we have a broken configuration.
2257 if (vdev
->msix
->pba_offset
>=
2258 vdev
->bars
[vdev
->msix
->pba_bar
].region
.size
) {
2260 PCIDevice
*pdev
= &vdev
->pdev
;
2261 uint16_t vendor
= pci_get_word(pdev
->config
+ PCI_VENDOR_ID
);
2262 uint16_t device
= pci_get_word(pdev
->config
+ PCI_DEVICE_ID
);
2265 * Chelsio T5 Virtual Function devices are encoded as 0x58xx for T5
2266 * adapters. The T5 hardware returns an incorrect value of 0x8000 for
2267 * the VF PBA offset while the BAR itself is only 8k. The correct value
2268 * is 0x1000, so we hard code that here.
2270 if (vendor
== PCI_VENDOR_ID_CHELSIO
&& (device
& 0xff00) == 0x5800) {
2271 vdev
->msix
->pba_offset
= 0x1000;
2273 error_report("vfio: Hardware reports invalid configuration, "
2274 "MSIX PBA outside of specified BAR");
2279 trace_vfio_early_setup_msix(vdev
->vbasedev
.name
, pos
,
2280 vdev
->msix
->table_bar
,
2281 vdev
->msix
->table_offset
,
2282 vdev
->msix
->entries
);
2287 static int vfio_setup_msix(VFIOPCIDevice
*vdev
, int pos
)
2291 ret
= msix_init(&vdev
->pdev
, vdev
->msix
->entries
,
2292 &vdev
->bars
[vdev
->msix
->table_bar
].region
.mem
,
2293 vdev
->msix
->table_bar
, vdev
->msix
->table_offset
,
2294 &vdev
->bars
[vdev
->msix
->pba_bar
].region
.mem
,
2295 vdev
->msix
->pba_bar
, vdev
->msix
->pba_offset
, pos
);
2297 if (ret
== -ENOTSUP
) {
2300 error_report("vfio: msix_init failed");
2307 static void vfio_teardown_msi(VFIOPCIDevice
*vdev
)
2309 msi_uninit(&vdev
->pdev
);
2312 msix_uninit(&vdev
->pdev
,
2313 &vdev
->bars
[vdev
->msix
->table_bar
].region
.mem
,
2314 &vdev
->bars
[vdev
->msix
->pba_bar
].region
.mem
);
2321 static void vfio_mmap_set_enabled(VFIOPCIDevice
*vdev
, bool enabled
)
2325 for (i
= 0; i
< PCI_ROM_SLOT
; i
++) {
2326 VFIOBAR
*bar
= &vdev
->bars
[i
];
2328 if (!bar
->region
.size
) {
2332 memory_region_set_enabled(&bar
->region
.mmap_mem
, enabled
);
2333 if (vdev
->msix
&& vdev
->msix
->table_bar
== i
) {
2334 memory_region_set_enabled(&vdev
->msix
->mmap_mem
, enabled
);
2339 static void vfio_unregister_bar(VFIOPCIDevice
*vdev
, int nr
)
2341 VFIOBAR
*bar
= &vdev
->bars
[nr
];
2343 if (!bar
->region
.size
) {
2347 vfio_bar_quirk_teardown(vdev
, nr
);
2349 memory_region_del_subregion(&bar
->region
.mem
, &bar
->region
.mmap_mem
);
2351 if (vdev
->msix
&& vdev
->msix
->table_bar
== nr
) {
2352 memory_region_del_subregion(&bar
->region
.mem
, &vdev
->msix
->mmap_mem
);
2356 static void vfio_unmap_bar(VFIOPCIDevice
*vdev
, int nr
)
2358 VFIOBAR
*bar
= &vdev
->bars
[nr
];
2360 if (!bar
->region
.size
) {
2364 vfio_bar_quirk_free(vdev
, nr
);
2366 munmap(bar
->region
.mmap
, memory_region_size(&bar
->region
.mmap_mem
));
2368 if (vdev
->msix
&& vdev
->msix
->table_bar
== nr
) {
2369 munmap(vdev
->msix
->mmap
, memory_region_size(&vdev
->msix
->mmap_mem
));
2373 static void vfio_map_bar(VFIOPCIDevice
*vdev
, int nr
)
2375 VFIOBAR
*bar
= &vdev
->bars
[nr
];
2376 uint64_t size
= bar
->region
.size
;
2382 /* Skip both unimplemented BARs and the upper half of 64bit BARS. */
2387 snprintf(name
, sizeof(name
), "VFIO %04x:%02x:%02x.%x BAR %d",
2388 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
2389 vdev
->host
.function
, nr
);
2391 /* Determine what type of BAR this is for registration */
2392 ret
= pread(vdev
->vbasedev
.fd
, &pci_bar
, sizeof(pci_bar
),
2393 vdev
->config_offset
+ PCI_BASE_ADDRESS_0
+ (4 * nr
));
2394 if (ret
!= sizeof(pci_bar
)) {
2395 error_report("vfio: Failed to read BAR %d (%m)", nr
);
2399 pci_bar
= le32_to_cpu(pci_bar
);
2400 bar
->ioport
= (pci_bar
& PCI_BASE_ADDRESS_SPACE_IO
);
2401 bar
->mem64
= bar
->ioport
? 0 : (pci_bar
& PCI_BASE_ADDRESS_MEM_TYPE_64
);
2402 type
= pci_bar
& (bar
->ioport
? ~PCI_BASE_ADDRESS_IO_MASK
:
2403 ~PCI_BASE_ADDRESS_MEM_MASK
);
2405 /* A "slow" read/write mapping underlies all BARs */
2406 memory_region_init_io(&bar
->region
.mem
, OBJECT(vdev
), &vfio_region_ops
,
2408 pci_register_bar(&vdev
->pdev
, nr
, type
, &bar
->region
.mem
);
2411 * We can't mmap areas overlapping the MSIX vector table, so we
2412 * potentially insert a direct-mapped subregion before and after it.
2414 if (vdev
->msix
&& vdev
->msix
->table_bar
== nr
) {
2415 size
= vdev
->msix
->table_offset
& qemu_real_host_page_mask
;
2418 strncat(name
, " mmap", sizeof(name
) - strlen(name
) - 1);
2419 if (vfio_mmap_region(OBJECT(vdev
), &bar
->region
, &bar
->region
.mem
,
2420 &bar
->region
.mmap_mem
, &bar
->region
.mmap
,
2422 error_report("%s unsupported. Performance may be slow", name
);
2425 if (vdev
->msix
&& vdev
->msix
->table_bar
== nr
) {
2428 start
= REAL_HOST_PAGE_ALIGN((uint64_t)vdev
->msix
->table_offset
+
2429 (vdev
->msix
->entries
*
2430 PCI_MSIX_ENTRY_SIZE
));
2432 size
= start
< bar
->region
.size
? bar
->region
.size
- start
: 0;
2433 strncat(name
, " msix-hi", sizeof(name
) - strlen(name
) - 1);
2434 /* VFIOMSIXInfo contains another MemoryRegion for this mapping */
2435 if (vfio_mmap_region(OBJECT(vdev
), &bar
->region
, &bar
->region
.mem
,
2436 &vdev
->msix
->mmap_mem
,
2437 &vdev
->msix
->mmap
, size
, start
, name
)) {
2438 error_report("%s unsupported. Performance may be slow", name
);
2442 vfio_bar_quirk_setup(vdev
, nr
);
2445 static void vfio_map_bars(VFIOPCIDevice
*vdev
)
2449 for (i
= 0; i
< PCI_ROM_SLOT
; i
++) {
2450 vfio_map_bar(vdev
, i
);
2453 if (vdev
->has_vga
) {
2454 memory_region_init_io(&vdev
->vga
.region
[QEMU_PCI_VGA_MEM
].mem
,
2455 OBJECT(vdev
), &vfio_vga_ops
,
2456 &vdev
->vga
.region
[QEMU_PCI_VGA_MEM
],
2457 "vfio-vga-mmio@0xa0000",
2458 QEMU_PCI_VGA_MEM_SIZE
);
2459 memory_region_init_io(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
].mem
,
2460 OBJECT(vdev
), &vfio_vga_ops
,
2461 &vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
],
2462 "vfio-vga-io@0x3b0",
2463 QEMU_PCI_VGA_IO_LO_SIZE
);
2464 memory_region_init_io(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].mem
,
2465 OBJECT(vdev
), &vfio_vga_ops
,
2466 &vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
],
2467 "vfio-vga-io@0x3c0",
2468 QEMU_PCI_VGA_IO_HI_SIZE
);
2470 pci_register_vga(&vdev
->pdev
, &vdev
->vga
.region
[QEMU_PCI_VGA_MEM
].mem
,
2471 &vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
].mem
,
2472 &vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].mem
);
2473 vfio_vga_quirk_setup(vdev
);
2477 static void vfio_unregister_bars(VFIOPCIDevice
*vdev
)
2481 for (i
= 0; i
< PCI_ROM_SLOT
; i
++) {
2482 vfio_unregister_bar(vdev
, i
);
2485 if (vdev
->has_vga
) {
2486 vfio_vga_quirk_teardown(vdev
);
2487 pci_unregister_vga(&vdev
->pdev
);
2491 static void vfio_unmap_bars(VFIOPCIDevice
*vdev
)
2495 for (i
= 0; i
< PCI_ROM_SLOT
; i
++) {
2496 vfio_unmap_bar(vdev
, i
);
2499 if (vdev
->has_vga
) {
2500 vfio_vga_quirk_free(vdev
);
2507 static uint8_t vfio_std_cap_max_size(PCIDevice
*pdev
, uint8_t pos
)
2509 uint8_t tmp
, next
= 0xff;
2511 for (tmp
= pdev
->config
[PCI_CAPABILITY_LIST
]; tmp
;
2512 tmp
= pdev
->config
[tmp
+ 1]) {
2513 if (tmp
> pos
&& tmp
< next
) {
2521 static void vfio_set_word_bits(uint8_t *buf
, uint16_t val
, uint16_t mask
)
2523 pci_set_word(buf
, (pci_get_word(buf
) & ~mask
) | val
);
2526 static void vfio_add_emulated_word(VFIOPCIDevice
*vdev
, int pos
,
2527 uint16_t val
, uint16_t mask
)
2529 vfio_set_word_bits(vdev
->pdev
.config
+ pos
, val
, mask
);
2530 vfio_set_word_bits(vdev
->pdev
.wmask
+ pos
, ~mask
, mask
);
2531 vfio_set_word_bits(vdev
->emulated_config_bits
+ pos
, mask
, mask
);
2534 static void vfio_set_long_bits(uint8_t *buf
, uint32_t val
, uint32_t mask
)
2536 pci_set_long(buf
, (pci_get_long(buf
) & ~mask
) | val
);
2539 static void vfio_add_emulated_long(VFIOPCIDevice
*vdev
, int pos
,
2540 uint32_t val
, uint32_t mask
)
2542 vfio_set_long_bits(vdev
->pdev
.config
+ pos
, val
, mask
);
2543 vfio_set_long_bits(vdev
->pdev
.wmask
+ pos
, ~mask
, mask
);
2544 vfio_set_long_bits(vdev
->emulated_config_bits
+ pos
, mask
, mask
);
2547 static int vfio_setup_pcie_cap(VFIOPCIDevice
*vdev
, int pos
, uint8_t size
)
2552 flags
= pci_get_word(vdev
->pdev
.config
+ pos
+ PCI_CAP_FLAGS
);
2553 type
= (flags
& PCI_EXP_FLAGS_TYPE
) >> 4;
2555 if (type
!= PCI_EXP_TYPE_ENDPOINT
&&
2556 type
!= PCI_EXP_TYPE_LEG_END
&&
2557 type
!= PCI_EXP_TYPE_RC_END
) {
2559 error_report("vfio: Assignment of PCIe type 0x%x "
2560 "devices is not currently supported", type
);
2564 if (!pci_bus_is_express(vdev
->pdev
.bus
)) {
2566 * Use express capability as-is on PCI bus. It doesn't make much
2567 * sense to even expose, but some drivers (ex. tg3) depend on it
2568 * and guests don't seem to be particular about it. We'll need
2569 * to revist this or force express devices to express buses if we
2570 * ever expose an IOMMU to the guest.
2572 } else if (pci_bus_is_root(vdev
->pdev
.bus
)) {
2574 * On a Root Complex bus Endpoints become Root Complex Integrated
2575 * Endpoints, which changes the type and clears the LNK & LNK2 fields.
2577 if (type
== PCI_EXP_TYPE_ENDPOINT
) {
2578 vfio_add_emulated_word(vdev
, pos
+ PCI_CAP_FLAGS
,
2579 PCI_EXP_TYPE_RC_END
<< 4,
2580 PCI_EXP_FLAGS_TYPE
);
2582 /* Link Capabilities, Status, and Control goes away */
2583 if (size
> PCI_EXP_LNKCTL
) {
2584 vfio_add_emulated_long(vdev
, pos
+ PCI_EXP_LNKCAP
, 0, ~0);
2585 vfio_add_emulated_word(vdev
, pos
+ PCI_EXP_LNKCTL
, 0, ~0);
2586 vfio_add_emulated_word(vdev
, pos
+ PCI_EXP_LNKSTA
, 0, ~0);
2588 #ifndef PCI_EXP_LNKCAP2
2589 #define PCI_EXP_LNKCAP2 44
2591 #ifndef PCI_EXP_LNKSTA2
2592 #define PCI_EXP_LNKSTA2 50
2594 /* Link 2 Capabilities, Status, and Control goes away */
2595 if (size
> PCI_EXP_LNKCAP2
) {
2596 vfio_add_emulated_long(vdev
, pos
+ PCI_EXP_LNKCAP2
, 0, ~0);
2597 vfio_add_emulated_word(vdev
, pos
+ PCI_EXP_LNKCTL2
, 0, ~0);
2598 vfio_add_emulated_word(vdev
, pos
+ PCI_EXP_LNKSTA2
, 0, ~0);
2602 } else if (type
== PCI_EXP_TYPE_LEG_END
) {
2604 * Legacy endpoints don't belong on the root complex. Windows
2605 * seems to be happier with devices if we skip the capability.
2612 * Convert Root Complex Integrated Endpoints to regular endpoints.
2613 * These devices don't support LNK/LNK2 capabilities, so make them up.
2615 if (type
== PCI_EXP_TYPE_RC_END
) {
2616 vfio_add_emulated_word(vdev
, pos
+ PCI_CAP_FLAGS
,
2617 PCI_EXP_TYPE_ENDPOINT
<< 4,
2618 PCI_EXP_FLAGS_TYPE
);
2619 vfio_add_emulated_long(vdev
, pos
+ PCI_EXP_LNKCAP
,
2620 PCI_EXP_LNK_MLW_1
| PCI_EXP_LNK_LS_25
, ~0);
2621 vfio_add_emulated_word(vdev
, pos
+ PCI_EXP_LNKCTL
, 0, ~0);
2624 /* Mark the Link Status bits as emulated to allow virtual negotiation */
2625 vfio_add_emulated_word(vdev
, pos
+ PCI_EXP_LNKSTA
,
2626 pci_get_word(vdev
->pdev
.config
+ pos
+
2628 PCI_EXP_LNKCAP_MLW
| PCI_EXP_LNKCAP_SLS
);
2631 pos
= pci_add_capability(&vdev
->pdev
, PCI_CAP_ID_EXP
, pos
, size
);
2633 vdev
->pdev
.exp
.exp_cap
= pos
;
2639 static void vfio_check_pcie_flr(VFIOPCIDevice
*vdev
, uint8_t pos
)
2641 uint32_t cap
= pci_get_long(vdev
->pdev
.config
+ pos
+ PCI_EXP_DEVCAP
);
2643 if (cap
& PCI_EXP_DEVCAP_FLR
) {
2644 trace_vfio_check_pcie_flr(vdev
->vbasedev
.name
);
2645 vdev
->has_flr
= true;
2649 static void vfio_check_pm_reset(VFIOPCIDevice
*vdev
, uint8_t pos
)
2651 uint16_t csr
= pci_get_word(vdev
->pdev
.config
+ pos
+ PCI_PM_CTRL
);
2653 if (!(csr
& PCI_PM_CTRL_NO_SOFT_RESET
)) {
2654 trace_vfio_check_pm_reset(vdev
->vbasedev
.name
);
2655 vdev
->has_pm_reset
= true;
2659 static void vfio_check_af_flr(VFIOPCIDevice
*vdev
, uint8_t pos
)
2661 uint8_t cap
= pci_get_byte(vdev
->pdev
.config
+ pos
+ PCI_AF_CAP
);
2663 if ((cap
& PCI_AF_CAP_TP
) && (cap
& PCI_AF_CAP_FLR
)) {
2664 trace_vfio_check_af_flr(vdev
->vbasedev
.name
);
2665 vdev
->has_flr
= true;
2669 static int vfio_add_std_cap(VFIOPCIDevice
*vdev
, uint8_t pos
)
2671 PCIDevice
*pdev
= &vdev
->pdev
;
2672 uint8_t cap_id
, next
, size
;
2675 cap_id
= pdev
->config
[pos
];
2676 next
= pdev
->config
[pos
+ 1];
2679 * If it becomes important to configure capabilities to their actual
2680 * size, use this as the default when it's something we don't recognize.
2681 * Since QEMU doesn't actually handle many of the config accesses,
2682 * exact size doesn't seem worthwhile.
2684 size
= vfio_std_cap_max_size(pdev
, pos
);
2687 * pci_add_capability always inserts the new capability at the head
2688 * of the chain. Therefore to end up with a chain that matches the
2689 * physical device, we insert from the end by making this recursive.
2690 * This is also why we pre-caclulate size above as cached config space
2691 * will be changed as we unwind the stack.
2694 ret
= vfio_add_std_cap(vdev
, next
);
2699 /* Begin the rebuild, use QEMU emulated list bits */
2700 pdev
->config
[PCI_CAPABILITY_LIST
] = 0;
2701 vdev
->emulated_config_bits
[PCI_CAPABILITY_LIST
] = 0xff;
2702 vdev
->emulated_config_bits
[PCI_STATUS
] |= PCI_STATUS_CAP_LIST
;
2705 /* Use emulated next pointer to allow dropping caps */
2706 pci_set_byte(vdev
->emulated_config_bits
+ pos
+ 1, 0xff);
2709 case PCI_CAP_ID_MSI
:
2710 ret
= vfio_setup_msi(vdev
, pos
);
2712 case PCI_CAP_ID_EXP
:
2713 vfio_check_pcie_flr(vdev
, pos
);
2714 ret
= vfio_setup_pcie_cap(vdev
, pos
, size
);
2716 case PCI_CAP_ID_MSIX
:
2717 ret
= vfio_setup_msix(vdev
, pos
);
2720 vfio_check_pm_reset(vdev
, pos
);
2722 ret
= pci_add_capability(pdev
, cap_id
, pos
, size
);
2725 vfio_check_af_flr(vdev
, pos
);
2726 ret
= pci_add_capability(pdev
, cap_id
, pos
, size
);
2729 ret
= pci_add_capability(pdev
, cap_id
, pos
, size
);
2734 error_report("vfio: %04x:%02x:%02x.%x Error adding PCI capability "
2735 "0x%x[0x%x]@0x%x: %d", vdev
->host
.domain
,
2736 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
,
2737 cap_id
, size
, pos
, ret
);
2744 static int vfio_add_capabilities(VFIOPCIDevice
*vdev
)
2746 PCIDevice
*pdev
= &vdev
->pdev
;
2748 if (!(pdev
->config
[PCI_STATUS
] & PCI_STATUS_CAP_LIST
) ||
2749 !pdev
->config
[PCI_CAPABILITY_LIST
]) {
2750 return 0; /* Nothing to add */
2753 return vfio_add_std_cap(vdev
, pdev
->config
[PCI_CAPABILITY_LIST
]);
2756 static void vfio_pci_pre_reset(VFIOPCIDevice
*vdev
)
2758 PCIDevice
*pdev
= &vdev
->pdev
;
2761 vfio_disable_interrupts(vdev
);
2763 /* Make sure the device is in D0 */
2768 pmcsr
= vfio_pci_read_config(pdev
, vdev
->pm_cap
+ PCI_PM_CTRL
, 2);
2769 state
= pmcsr
& PCI_PM_CTRL_STATE_MASK
;
2771 pmcsr
&= ~PCI_PM_CTRL_STATE_MASK
;
2772 vfio_pci_write_config(pdev
, vdev
->pm_cap
+ PCI_PM_CTRL
, pmcsr
, 2);
2773 /* vfio handles the necessary delay here */
2774 pmcsr
= vfio_pci_read_config(pdev
, vdev
->pm_cap
+ PCI_PM_CTRL
, 2);
2775 state
= pmcsr
& PCI_PM_CTRL_STATE_MASK
;
2777 error_report("vfio: Unable to power on device, stuck in D%d",
2784 * Stop any ongoing DMA by disconecting I/O, MMIO, and bus master.
2785 * Also put INTx Disable in known state.
2787 cmd
= vfio_pci_read_config(pdev
, PCI_COMMAND
, 2);
2788 cmd
&= ~(PCI_COMMAND_IO
| PCI_COMMAND_MEMORY
| PCI_COMMAND_MASTER
|
2789 PCI_COMMAND_INTX_DISABLE
);
2790 vfio_pci_write_config(pdev
, PCI_COMMAND
, cmd
, 2);
2793 static void vfio_pci_post_reset(VFIOPCIDevice
*vdev
)
2795 vfio_enable_intx(vdev
);
2798 static bool vfio_pci_host_match(PCIHostDeviceAddress
*host1
,
2799 PCIHostDeviceAddress
*host2
)
2801 return (host1
->domain
== host2
->domain
&& host1
->bus
== host2
->bus
&&
2802 host1
->slot
== host2
->slot
&& host1
->function
== host2
->function
);
2805 static int vfio_pci_hot_reset(VFIOPCIDevice
*vdev
, bool single
)
2808 struct vfio_pci_hot_reset_info
*info
;
2809 struct vfio_pci_dependent_device
*devices
;
2810 struct vfio_pci_hot_reset
*reset
;
2815 trace_vfio_pci_hot_reset(vdev
->vbasedev
.name
, single
? "one" : "multi");
2817 vfio_pci_pre_reset(vdev
);
2818 vdev
->vbasedev
.needs_reset
= false;
2820 info
= g_malloc0(sizeof(*info
));
2821 info
->argsz
= sizeof(*info
);
2823 ret
= ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO
, info
);
2824 if (ret
&& errno
!= ENOSPC
) {
2826 if (!vdev
->has_pm_reset
) {
2827 error_report("vfio: Cannot reset device %04x:%02x:%02x.%x, "
2828 "no available reset mechanism.", vdev
->host
.domain
,
2829 vdev
->host
.bus
, vdev
->host
.slot
, vdev
->host
.function
);
2834 count
= info
->count
;
2835 info
= g_realloc(info
, sizeof(*info
) + (count
* sizeof(*devices
)));
2836 info
->argsz
= sizeof(*info
) + (count
* sizeof(*devices
));
2837 devices
= &info
->devices
[0];
2839 ret
= ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_GET_PCI_HOT_RESET_INFO
, info
);
2842 error_report("vfio: hot reset info failed: %m");
2846 trace_vfio_pci_hot_reset_has_dep_devices(vdev
->vbasedev
.name
);
2848 /* Verify that we have all the groups required */
2849 for (i
= 0; i
< info
->count
; i
++) {
2850 PCIHostDeviceAddress host
;
2852 VFIODevice
*vbasedev_iter
;
2854 host
.domain
= devices
[i
].segment
;
2855 host
.bus
= devices
[i
].bus
;
2856 host
.slot
= PCI_SLOT(devices
[i
].devfn
);
2857 host
.function
= PCI_FUNC(devices
[i
].devfn
);
2859 trace_vfio_pci_hot_reset_dep_devices(host
.domain
,
2860 host
.bus
, host
.slot
, host
.function
, devices
[i
].group_id
);
2862 if (vfio_pci_host_match(&host
, &vdev
->host
)) {
2866 QLIST_FOREACH(group
, &vfio_group_list
, next
) {
2867 if (group
->groupid
== devices
[i
].group_id
) {
2873 if (!vdev
->has_pm_reset
) {
2874 error_report("vfio: Cannot reset device %s, "
2875 "depends on group %d which is not owned.",
2876 vdev
->vbasedev
.name
, devices
[i
].group_id
);
2882 /* Prep dependent devices for reset and clear our marker. */
2883 QLIST_FOREACH(vbasedev_iter
, &group
->device_list
, next
) {
2884 if (vbasedev_iter
->type
!= VFIO_DEVICE_TYPE_PCI
) {
2887 tmp
= container_of(vbasedev_iter
, VFIOPCIDevice
, vbasedev
);
2888 if (vfio_pci_host_match(&host
, &tmp
->host
)) {
2893 vfio_pci_pre_reset(tmp
);
2894 tmp
->vbasedev
.needs_reset
= false;
2901 if (!single
&& !multi
) {
2906 /* Determine how many group fds need to be passed */
2908 QLIST_FOREACH(group
, &vfio_group_list
, next
) {
2909 for (i
= 0; i
< info
->count
; i
++) {
2910 if (group
->groupid
== devices
[i
].group_id
) {
2917 reset
= g_malloc0(sizeof(*reset
) + (count
* sizeof(*fds
)));
2918 reset
->argsz
= sizeof(*reset
) + (count
* sizeof(*fds
));
2919 fds
= &reset
->group_fds
[0];
2921 /* Fill in group fds */
2922 QLIST_FOREACH(group
, &vfio_group_list
, next
) {
2923 for (i
= 0; i
< info
->count
; i
++) {
2924 if (group
->groupid
== devices
[i
].group_id
) {
2925 fds
[reset
->count
++] = group
->fd
;
2932 ret
= ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_PCI_HOT_RESET
, reset
);
2935 trace_vfio_pci_hot_reset_result(vdev
->vbasedev
.name
,
2936 ret
? "%m" : "Success");
2939 /* Re-enable INTx on affected devices */
2940 for (i
= 0; i
< info
->count
; i
++) {
2941 PCIHostDeviceAddress host
;
2943 VFIODevice
*vbasedev_iter
;
2945 host
.domain
= devices
[i
].segment
;
2946 host
.bus
= devices
[i
].bus
;
2947 host
.slot
= PCI_SLOT(devices
[i
].devfn
);
2948 host
.function
= PCI_FUNC(devices
[i
].devfn
);
2950 if (vfio_pci_host_match(&host
, &vdev
->host
)) {
2954 QLIST_FOREACH(group
, &vfio_group_list
, next
) {
2955 if (group
->groupid
== devices
[i
].group_id
) {
2964 QLIST_FOREACH(vbasedev_iter
, &group
->device_list
, next
) {
2965 if (vbasedev_iter
->type
!= VFIO_DEVICE_TYPE_PCI
) {
2968 tmp
= container_of(vbasedev_iter
, VFIOPCIDevice
, vbasedev
);
2969 if (vfio_pci_host_match(&host
, &tmp
->host
)) {
2970 vfio_pci_post_reset(tmp
);
2976 vfio_pci_post_reset(vdev
);
2983 * We want to differentiate hot reset of mulitple in-use devices vs hot reset
2984 * of a single in-use device. VFIO_DEVICE_RESET will already handle the case
2985 * of doing hot resets when there is only a single device per bus. The in-use
2986 * here refers to how many VFIODevices are affected. A hot reset that affects
2987 * multiple devices, but only a single in-use device, means that we can call
2988 * it from our bus ->reset() callback since the extent is effectively a single
2989 * device. This allows us to make use of it in the hotplug path. When there
2990 * are multiple in-use devices, we can only trigger the hot reset during a
2991 * system reset and thus from our reset handler. We separate _one vs _multi
2992 * here so that we don't overlap and do a double reset on the system reset
2993 * path where both our reset handler and ->reset() callback are used. Calling
2994 * _one() will only do a hot reset for the one in-use devices case, calling
2995 * _multi() will do nothing if a _one() would have been sufficient.
2997 static int vfio_pci_hot_reset_one(VFIOPCIDevice
*vdev
)
2999 return vfio_pci_hot_reset(vdev
, true);
3002 static int vfio_pci_hot_reset_multi(VFIODevice
*vbasedev
)
3004 VFIOPCIDevice
*vdev
= container_of(vbasedev
, VFIOPCIDevice
, vbasedev
);
3005 return vfio_pci_hot_reset(vdev
, false);
3008 static void vfio_pci_compute_needs_reset(VFIODevice
*vbasedev
)
3010 VFIOPCIDevice
*vdev
= container_of(vbasedev
, VFIOPCIDevice
, vbasedev
);
3011 if (!vbasedev
->reset_works
|| (!vdev
->has_flr
&& vdev
->has_pm_reset
)) {
3012 vbasedev
->needs_reset
= true;
3016 static VFIODeviceOps vfio_pci_ops
= {
3017 .vfio_compute_needs_reset
= vfio_pci_compute_needs_reset
,
3018 .vfio_hot_reset_multi
= vfio_pci_hot_reset_multi
,
3019 .vfio_eoi
= vfio_eoi
,
3022 static int vfio_populate_device(VFIOPCIDevice
*vdev
)
3024 VFIODevice
*vbasedev
= &vdev
->vbasedev
;
3025 struct vfio_region_info reg_info
= { .argsz
= sizeof(reg_info
) };
3026 struct vfio_irq_info irq_info
= { .argsz
= sizeof(irq_info
) };
3029 /* Sanity check device */
3030 if (!(vbasedev
->flags
& VFIO_DEVICE_FLAGS_PCI
)) {
3031 error_report("vfio: Um, this isn't a PCI device");
3035 if (vbasedev
->num_regions
< VFIO_PCI_CONFIG_REGION_INDEX
+ 1) {
3036 error_report("vfio: unexpected number of io regions %u",
3037 vbasedev
->num_regions
);
3041 if (vbasedev
->num_irqs
< VFIO_PCI_MSIX_IRQ_INDEX
+ 1) {
3042 error_report("vfio: unexpected number of irqs %u", vbasedev
->num_irqs
);
3046 for (i
= VFIO_PCI_BAR0_REGION_INDEX
; i
< VFIO_PCI_ROM_REGION_INDEX
; i
++) {
3049 ret
= ioctl(vbasedev
->fd
, VFIO_DEVICE_GET_REGION_INFO
, ®_info
);
3051 error_report("vfio: Error getting region %d info: %m", i
);
3055 trace_vfio_populate_device_region(vbasedev
->name
, i
,
3056 (unsigned long)reg_info
.size
,
3057 (unsigned long)reg_info
.offset
,
3058 (unsigned long)reg_info
.flags
);
3060 vdev
->bars
[i
].region
.vbasedev
= vbasedev
;
3061 vdev
->bars
[i
].region
.flags
= reg_info
.flags
;
3062 vdev
->bars
[i
].region
.size
= reg_info
.size
;
3063 vdev
->bars
[i
].region
.fd_offset
= reg_info
.offset
;
3064 vdev
->bars
[i
].region
.nr
= i
;
3065 QLIST_INIT(&vdev
->bars
[i
].quirks
);
3068 reg_info
.index
= VFIO_PCI_CONFIG_REGION_INDEX
;
3070 ret
= ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_GET_REGION_INFO
, ®_info
);
3072 error_report("vfio: Error getting config info: %m");
3076 trace_vfio_populate_device_config(vdev
->vbasedev
.name
,
3077 (unsigned long)reg_info
.size
,
3078 (unsigned long)reg_info
.offset
,
3079 (unsigned long)reg_info
.flags
);
3081 vdev
->config_size
= reg_info
.size
;
3082 if (vdev
->config_size
== PCI_CONFIG_SPACE_SIZE
) {
3083 vdev
->pdev
.cap_present
&= ~QEMU_PCI_CAP_EXPRESS
;
3085 vdev
->config_offset
= reg_info
.offset
;
3087 if ((vdev
->features
& VFIO_FEATURE_ENABLE_VGA
) &&
3088 vbasedev
->num_regions
> VFIO_PCI_VGA_REGION_INDEX
) {
3089 struct vfio_region_info vga_info
= {
3090 .argsz
= sizeof(vga_info
),
3091 .index
= VFIO_PCI_VGA_REGION_INDEX
,
3094 ret
= ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_GET_REGION_INFO
, &vga_info
);
3097 "vfio: Device does not support requested feature x-vga");
3101 if (!(vga_info
.flags
& VFIO_REGION_INFO_FLAG_READ
) ||
3102 !(vga_info
.flags
& VFIO_REGION_INFO_FLAG_WRITE
) ||
3103 vga_info
.size
< 0xbffff + 1) {
3104 error_report("vfio: Unexpected VGA info, flags 0x%lx, size 0x%lx",
3105 (unsigned long)vga_info
.flags
,
3106 (unsigned long)vga_info
.size
);
3110 vdev
->vga
.fd_offset
= vga_info
.offset
;
3111 vdev
->vga
.fd
= vdev
->vbasedev
.fd
;
3113 vdev
->vga
.region
[QEMU_PCI_VGA_MEM
].offset
= QEMU_PCI_VGA_MEM_BASE
;
3114 vdev
->vga
.region
[QEMU_PCI_VGA_MEM
].nr
= QEMU_PCI_VGA_MEM
;
3115 QLIST_INIT(&vdev
->vga
.region
[QEMU_PCI_VGA_MEM
].quirks
);
3117 vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
].offset
= QEMU_PCI_VGA_IO_LO_BASE
;
3118 vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
].nr
= QEMU_PCI_VGA_IO_LO
;
3119 QLIST_INIT(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_LO
].quirks
);
3121 vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].offset
= QEMU_PCI_VGA_IO_HI_BASE
;
3122 vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].nr
= QEMU_PCI_VGA_IO_HI
;
3123 QLIST_INIT(&vdev
->vga
.region
[QEMU_PCI_VGA_IO_HI
].quirks
);
3125 vdev
->has_vga
= true;
3128 irq_info
.index
= VFIO_PCI_ERR_IRQ_INDEX
;
3130 ret
= ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_GET_IRQ_INFO
, &irq_info
);
3132 /* This can fail for an old kernel or legacy PCI dev */
3133 trace_vfio_populate_device_get_irq_info_failure();
3135 } else if (irq_info
.count
== 1) {
3136 vdev
->pci_aer
= true;
3138 error_report("vfio: %s "
3139 "Could not enable error recovery for the device",
3147 static void vfio_put_device(VFIOPCIDevice
*vdev
)
3149 g_free(vdev
->vbasedev
.name
);
3151 object_unparent(OBJECT(&vdev
->msix
->mmap_mem
));
3155 vfio_put_base_device(&vdev
->vbasedev
);
3158 static void vfio_err_notifier_handler(void *opaque
)
3160 VFIOPCIDevice
*vdev
= opaque
;
3162 if (!event_notifier_test_and_clear(&vdev
->err_notifier
)) {
3167 * TBD. Retrieve the error details and decide what action
3168 * needs to be taken. One of the actions could be to pass
3169 * the error to the guest and have the guest driver recover
3170 * from the error. This requires that PCIe capabilities be
3171 * exposed to the guest. For now, we just terminate the
3172 * guest to contain the error.
3175 error_report("%s(%04x:%02x:%02x.%x) Unrecoverable error detected. "
3176 "Please collect any data possible and then kill the guest",
3177 __func__
, vdev
->host
.domain
, vdev
->host
.bus
,
3178 vdev
->host
.slot
, vdev
->host
.function
);
3180 vm_stop(RUN_STATE_INTERNAL_ERROR
);
3184 * Registers error notifier for devices supporting error recovery.
3185 * If we encounter a failure in this function, we report an error
3186 * and continue after disabling error recovery support for the
3189 static void vfio_register_err_notifier(VFIOPCIDevice
*vdev
)
3193 struct vfio_irq_set
*irq_set
;
3196 if (!vdev
->pci_aer
) {
3200 if (event_notifier_init(&vdev
->err_notifier
, 0)) {
3201 error_report("vfio: Unable to init event notifier for error detection");
3202 vdev
->pci_aer
= false;
3206 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
3208 irq_set
= g_malloc0(argsz
);
3209 irq_set
->argsz
= argsz
;
3210 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
|
3211 VFIO_IRQ_SET_ACTION_TRIGGER
;
3212 irq_set
->index
= VFIO_PCI_ERR_IRQ_INDEX
;
3215 pfd
= (int32_t *)&irq_set
->data
;
3217 *pfd
= event_notifier_get_fd(&vdev
->err_notifier
);
3218 qemu_set_fd_handler(*pfd
, vfio_err_notifier_handler
, NULL
, vdev
);
3220 ret
= ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
3222 error_report("vfio: Failed to set up error notification");
3223 qemu_set_fd_handler(*pfd
, NULL
, NULL
, vdev
);
3224 event_notifier_cleanup(&vdev
->err_notifier
);
3225 vdev
->pci_aer
= false;
3230 static void vfio_unregister_err_notifier(VFIOPCIDevice
*vdev
)
3233 struct vfio_irq_set
*irq_set
;
3237 if (!vdev
->pci_aer
) {
3241 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
3243 irq_set
= g_malloc0(argsz
);
3244 irq_set
->argsz
= argsz
;
3245 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
|
3246 VFIO_IRQ_SET_ACTION_TRIGGER
;
3247 irq_set
->index
= VFIO_PCI_ERR_IRQ_INDEX
;
3250 pfd
= (int32_t *)&irq_set
->data
;
3253 ret
= ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_SET_IRQS
, irq_set
);
3255 error_report("vfio: Failed to de-assign error fd: %m");
3258 qemu_set_fd_handler(event_notifier_get_fd(&vdev
->err_notifier
),
3260 event_notifier_cleanup(&vdev
->err_notifier
);
3263 static void vfio_req_notifier_handler(void *opaque
)
3265 VFIOPCIDevice
*vdev
= opaque
;
3267 if (!event_notifier_test_and_clear(&vdev
->req_notifier
)) {
3271 qdev_unplug(&vdev
->pdev
.qdev
, NULL
);
3274 static void vfio_register_req_notifier(VFIOPCIDevice
*vdev
)
3276 struct vfio_irq_info irq_info
= { .argsz
= sizeof(irq_info
),
3277 .index
= VFIO_PCI_REQ_IRQ_INDEX
};
3279 struct vfio_irq_set
*irq_set
;
3282 if (!(vdev
->features
& VFIO_FEATURE_ENABLE_REQ
)) {
3286 if (ioctl(vdev
->vbasedev
.fd
,
3287 VFIO_DEVICE_GET_IRQ_INFO
, &irq_info
) < 0 || irq_info
.count
< 1) {
3291 if (event_notifier_init(&vdev
->req_notifier
, 0)) {
3292 error_report("vfio: Unable to init event notifier for device request");
3296 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
3298 irq_set
= g_malloc0(argsz
);
3299 irq_set
->argsz
= argsz
;
3300 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
|
3301 VFIO_IRQ_SET_ACTION_TRIGGER
;
3302 irq_set
->index
= VFIO_PCI_REQ_IRQ_INDEX
;
3305 pfd
= (int32_t *)&irq_set
->data
;
3307 *pfd
= event_notifier_get_fd(&vdev
->req_notifier
);
3308 qemu_set_fd_handler(*pfd
, vfio_req_notifier_handler
, NULL
, vdev
);
3310 if (ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_SET_IRQS
, irq_set
)) {
3311 error_report("vfio: Failed to set up device request notification");
3312 qemu_set_fd_handler(*pfd
, NULL
, NULL
, vdev
);
3313 event_notifier_cleanup(&vdev
->req_notifier
);
3315 vdev
->req_enabled
= true;
3321 static void vfio_unregister_req_notifier(VFIOPCIDevice
*vdev
)
3324 struct vfio_irq_set
*irq_set
;
3327 if (!vdev
->req_enabled
) {
3331 argsz
= sizeof(*irq_set
) + sizeof(*pfd
);
3333 irq_set
= g_malloc0(argsz
);
3334 irq_set
->argsz
= argsz
;
3335 irq_set
->flags
= VFIO_IRQ_SET_DATA_EVENTFD
|
3336 VFIO_IRQ_SET_ACTION_TRIGGER
;
3337 irq_set
->index
= VFIO_PCI_REQ_IRQ_INDEX
;
3340 pfd
= (int32_t *)&irq_set
->data
;
3343 if (ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_SET_IRQS
, irq_set
)) {
3344 error_report("vfio: Failed to de-assign device request fd: %m");
3347 qemu_set_fd_handler(event_notifier_get_fd(&vdev
->req_notifier
),
3349 event_notifier_cleanup(&vdev
->req_notifier
);
3351 vdev
->req_enabled
= false;
3355 * AMD Radeon PCI config reset, based on Linux:
3356 * drivers/gpu/drm/radeon/ci_smc.c:ci_is_smc_running()
3357 * drivers/gpu/drm/radeon/radeon_device.c:radeon_pci_config_reset
3358 * drivers/gpu/drm/radeon/ci_smc.c:ci_reset_smc()
3359 * drivers/gpu/drm/radeon/ci_smc.c:ci_stop_smc_clock()
3360 * IDs: include/drm/drm_pciids.h
3361 * Registers: http://cgit.freedesktop.org/~agd5f/linux/commit/?id=4e2aa447f6f0
3363 * Bonaire and Hawaii GPUs do not respond to a bus reset. This is a bug in the
3364 * hardware that should be fixed on future ASICs. The symptom of this is that
3365 * once the accerlated driver loads, Windows guests will bsod on subsequent
3366 * attmpts to load the driver, such as after VM reset or shutdown/restart. To
3367 * work around this, we do an AMD specific PCI config reset, followed by an SMC
3368 * reset. The PCI config reset only works if SMC firmware is running, so we
3369 * have a dependency on the state of the device as to whether this reset will
3370 * be effective. There are still cases where we won't be able to kick the
3371 * device into working, but this greatly improves the usability overall. The
3372 * config reset magic is relatively common on AMD GPUs, but the setup and SMC
3373 * poking is largely ASIC specific.
3375 static bool vfio_radeon_smc_is_running(VFIOPCIDevice
*vdev
)
3380 * Registers 200h and 204h are index and data registers for acessing
3381 * indirect configuration registers within the device.
3383 vfio_region_write(&vdev
->bars
[5].region
, 0x200, 0x80000004, 4);
3384 clk
= vfio_region_read(&vdev
->bars
[5].region
, 0x204, 4);
3385 vfio_region_write(&vdev
->bars
[5].region
, 0x200, 0x80000370, 4);
3386 pc_c
= vfio_region_read(&vdev
->bars
[5].region
, 0x204, 4);
3388 return (!(clk
& 1) && (0x20100 <= pc_c
));
3392 * The scope of a config reset is controlled by a mode bit in the misc register
3393 * and a fuse, exposed as a bit in another register. The fuse is the default
3394 * (0 = GFX, 1 = whole GPU), the misc bit is a toggle, with the forumula
3395 * scope = !(misc ^ fuse), where the resulting scope is defined the same as
3396 * the fuse. A truth table therefore tells us that if misc == fuse, we need
3397 * to flip the value of the bit in the misc register.
3399 static void vfio_radeon_set_gfx_only_reset(VFIOPCIDevice
*vdev
)
3401 uint32_t misc
, fuse
;
3404 vfio_region_write(&vdev
->bars
[5].region
, 0x200, 0xc00c0000, 4);
3405 fuse
= vfio_region_read(&vdev
->bars
[5].region
, 0x204, 4);
3408 vfio_region_write(&vdev
->bars
[5].region
, 0x200, 0xc0000010, 4);
3409 misc
= vfio_region_read(&vdev
->bars
[5].region
, 0x204, 4);
3413 vfio_region_write(&vdev
->bars
[5].region
, 0x204, misc
^ 2, 4);
3414 vfio_region_read(&vdev
->bars
[5].region
, 0x204, 4); /* flush */
3418 static int vfio_radeon_reset(VFIOPCIDevice
*vdev
)
3420 PCIDevice
*pdev
= &vdev
->pdev
;
3424 /* Defer to a kernel implemented reset */
3425 if (vdev
->vbasedev
.reset_works
) {
3429 /* Enable only memory BAR access */
3430 vfio_pci_write_config(pdev
, PCI_COMMAND
, PCI_COMMAND_MEMORY
, 2);
3432 /* Reset only works if SMC firmware is loaded and running */
3433 if (!vfio_radeon_smc_is_running(vdev
)) {
3438 /* Make sure only the GFX function is reset */
3439 vfio_radeon_set_gfx_only_reset(vdev
);
3441 /* AMD PCI config reset */
3442 vfio_pci_write_config(pdev
, 0x7c, 0x39d5e86b, 4);
3445 /* Read back the memory size to make sure we're out of reset */
3446 for (i
= 0; i
< 100000; i
++) {
3447 if (vfio_region_read(&vdev
->bars
[5].region
, 0x5428, 4) != 0xffffffff) {
3454 vfio_region_write(&vdev
->bars
[5].region
, 0x200, 0x80000000, 4);
3455 data
= vfio_region_read(&vdev
->bars
[5].region
, 0x204, 4);
3457 vfio_region_write(&vdev
->bars
[5].region
, 0x204, data
, 4);
3459 /* Disable SMC clock */
3460 vfio_region_write(&vdev
->bars
[5].region
, 0x200, 0x80000004, 4);
3461 data
= vfio_region_read(&vdev
->bars
[5].region
, 0x204, 4);
3463 vfio_region_write(&vdev
->bars
[5].region
, 0x204, data
, 4);
3466 /* Restore PCI command register */
3467 vfio_pci_write_config(pdev
, PCI_COMMAND
, 0, 2);
3472 static void vfio_setup_resetfn(VFIOPCIDevice
*vdev
)
3474 PCIDevice
*pdev
= &vdev
->pdev
;
3475 uint16_t vendor
, device
;
3477 vendor
= pci_get_word(pdev
->config
+ PCI_VENDOR_ID
);
3478 device
= pci_get_word(pdev
->config
+ PCI_DEVICE_ID
);
3484 case 0x6649: /* Bonaire [FirePro W5100] */
3487 case 0x6658: /* Bonaire XTX [Radeon R7 260X] */
3488 case 0x665c: /* Bonaire XT [Radeon HD 7790/8770 / R9 260 OEM] */
3489 case 0x665d: /* Bonaire [Radeon R7 200 Series] */
3491 case 0x67A0: /* Hawaii XT GL [FirePro W9100] */
3492 case 0x67A1: /* Hawaii PRO GL [FirePro W8100] */
3497 case 0x67B0: /* Hawaii XT [Radeon R9 290X] */
3498 case 0x67B1: /* Hawaii PRO [Radeon R9 290] */
3503 vdev
->resetfn
= vfio_radeon_reset
;
3510 static int vfio_initfn(PCIDevice
*pdev
)
3512 VFIOPCIDevice
*vdev
= DO_UPCAST(VFIOPCIDevice
, pdev
, pdev
);
3513 VFIODevice
*vbasedev_iter
;
3515 char path
[PATH_MAX
], iommu_group_path
[PATH_MAX
], *group_name
;
3521 /* Check that the host device exists */
3522 snprintf(path
, sizeof(path
),
3523 "/sys/bus/pci/devices/%04x:%02x:%02x.%01x/",
3524 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
3525 vdev
->host
.function
);
3526 if (stat(path
, &st
) < 0) {
3527 error_report("vfio: error: no such host device: %s", path
);
3531 vdev
->vbasedev
.ops
= &vfio_pci_ops
;
3533 vdev
->vbasedev
.type
= VFIO_DEVICE_TYPE_PCI
;
3534 vdev
->vbasedev
.name
= g_strdup_printf("%04x:%02x:%02x.%01x",
3535 vdev
->host
.domain
, vdev
->host
.bus
,
3536 vdev
->host
.slot
, vdev
->host
.function
);
3538 strncat(path
, "iommu_group", sizeof(path
) - strlen(path
) - 1);
3540 len
= readlink(path
, iommu_group_path
, sizeof(path
));
3541 if (len
<= 0 || len
>= sizeof(path
)) {
3542 error_report("vfio: error no iommu_group for device");
3543 return len
< 0 ? -errno
: -ENAMETOOLONG
;
3546 iommu_group_path
[len
] = 0;
3547 group_name
= basename(iommu_group_path
);
3549 if (sscanf(group_name
, "%d", &groupid
) != 1) {
3550 error_report("vfio: error reading %s: %m", path
);
3554 trace_vfio_initfn(vdev
->vbasedev
.name
, groupid
);
3556 group
= vfio_get_group(groupid
, pci_device_iommu_address_space(pdev
));
3558 error_report("vfio: failed to get group %d", groupid
);
3562 snprintf(path
, sizeof(path
), "%04x:%02x:%02x.%01x",
3563 vdev
->host
.domain
, vdev
->host
.bus
, vdev
->host
.slot
,
3564 vdev
->host
.function
);
3566 QLIST_FOREACH(vbasedev_iter
, &group
->device_list
, next
) {
3567 if (strcmp(vbasedev_iter
->name
, vdev
->vbasedev
.name
) == 0) {
3568 error_report("vfio: error: device %s is already attached", path
);
3569 vfio_put_group(group
);
3574 ret
= vfio_get_device(group
, path
, &vdev
->vbasedev
);
3576 error_report("vfio: failed to get device %s", path
);
3577 vfio_put_group(group
);
3581 ret
= vfio_populate_device(vdev
);
3586 /* Get a copy of config space */
3587 ret
= pread(vdev
->vbasedev
.fd
, vdev
->pdev
.config
,
3588 MIN(pci_config_size(&vdev
->pdev
), vdev
->config_size
),
3589 vdev
->config_offset
);
3590 if (ret
< (int)MIN(pci_config_size(&vdev
->pdev
), vdev
->config_size
)) {
3591 ret
= ret
< 0 ? -errno
: -EFAULT
;
3592 error_report("vfio: Failed to read device config space");
3596 /* vfio emulates a lot for us, but some bits need extra love */
3597 vdev
->emulated_config_bits
= g_malloc0(vdev
->config_size
);
3599 /* QEMU can choose to expose the ROM or not */
3600 memset(vdev
->emulated_config_bits
+ PCI_ROM_ADDRESS
, 0xff, 4);
3602 /* QEMU can change multi-function devices to single function, or reverse */
3603 vdev
->emulated_config_bits
[PCI_HEADER_TYPE
] =
3604 PCI_HEADER_TYPE_MULTI_FUNCTION
;
3606 /* Restore or clear multifunction, this is always controlled by QEMU */
3607 if (vdev
->pdev
.cap_present
& QEMU_PCI_CAP_MULTIFUNCTION
) {
3608 vdev
->pdev
.config
[PCI_HEADER_TYPE
] |= PCI_HEADER_TYPE_MULTI_FUNCTION
;
3610 vdev
->pdev
.config
[PCI_HEADER_TYPE
] &= ~PCI_HEADER_TYPE_MULTI_FUNCTION
;
3614 * Clear host resource mapping info. If we choose not to register a
3615 * BAR, such as might be the case with the option ROM, we can get
3616 * confusing, unwritable, residual addresses from the host here.
3618 memset(&vdev
->pdev
.config
[PCI_BASE_ADDRESS_0
], 0, 24);
3619 memset(&vdev
->pdev
.config
[PCI_ROM_ADDRESS
], 0, 4);
3621 vfio_pci_size_rom(vdev
);
3623 ret
= vfio_early_setup_msix(vdev
);
3628 vfio_map_bars(vdev
);
3630 ret
= vfio_add_capabilities(vdev
);
3635 /* QEMU emulates all of MSI & MSIX */
3636 if (pdev
->cap_present
& QEMU_PCI_CAP_MSIX
) {
3637 memset(vdev
->emulated_config_bits
+ pdev
->msix_cap
, 0xff,
3641 if (pdev
->cap_present
& QEMU_PCI_CAP_MSI
) {
3642 memset(vdev
->emulated_config_bits
+ pdev
->msi_cap
, 0xff,
3643 vdev
->msi_cap_size
);
3646 if (vfio_pci_read_config(&vdev
->pdev
, PCI_INTERRUPT_PIN
, 1)) {
3647 vdev
->intx
.mmap_timer
= timer_new_ms(QEMU_CLOCK_VIRTUAL
,
3648 vfio_intx_mmap_enable
, vdev
);
3649 pci_device_set_intx_routing_notifier(&vdev
->pdev
, vfio_update_irq
);
3650 ret
= vfio_enable_intx(vdev
);
3656 vfio_register_err_notifier(vdev
);
3657 vfio_register_req_notifier(vdev
);
3658 vfio_setup_resetfn(vdev
);
3663 pci_device_set_intx_routing_notifier(&vdev
->pdev
, NULL
);
3664 vfio_teardown_msi(vdev
);
3665 vfio_unregister_bars(vdev
);
3669 static void vfio_instance_finalize(Object
*obj
)
3671 PCIDevice
*pci_dev
= PCI_DEVICE(obj
);
3672 VFIOPCIDevice
*vdev
= DO_UPCAST(VFIOPCIDevice
, pdev
, pci_dev
);
3673 VFIOGroup
*group
= vdev
->vbasedev
.group
;
3675 vfio_unmap_bars(vdev
);
3676 g_free(vdev
->emulated_config_bits
);
3678 vfio_put_device(vdev
);
3679 vfio_put_group(group
);
3682 static void vfio_exitfn(PCIDevice
*pdev
)
3684 VFIOPCIDevice
*vdev
= DO_UPCAST(VFIOPCIDevice
, pdev
, pdev
);
3686 vfio_unregister_req_notifier(vdev
);
3687 vfio_unregister_err_notifier(vdev
);
3688 pci_device_set_intx_routing_notifier(&vdev
->pdev
, NULL
);
3689 vfio_disable_interrupts(vdev
);
3690 if (vdev
->intx
.mmap_timer
) {
3691 timer_free(vdev
->intx
.mmap_timer
);
3693 vfio_teardown_msi(vdev
);
3694 vfio_unregister_bars(vdev
);
3697 static void vfio_pci_reset(DeviceState
*dev
)
3699 PCIDevice
*pdev
= DO_UPCAST(PCIDevice
, qdev
, dev
);
3700 VFIOPCIDevice
*vdev
= DO_UPCAST(VFIOPCIDevice
, pdev
, pdev
);
3702 trace_vfio_pci_reset(vdev
->vbasedev
.name
);
3704 vfio_pci_pre_reset(vdev
);
3706 if (vdev
->resetfn
&& !vdev
->resetfn(vdev
)) {
3710 if (vdev
->vbasedev
.reset_works
&&
3711 (vdev
->has_flr
|| !vdev
->has_pm_reset
) &&
3712 !ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_RESET
)) {
3713 trace_vfio_pci_reset_flr(vdev
->vbasedev
.name
);
3717 /* See if we can do our own bus reset */
3718 if (!vfio_pci_hot_reset_one(vdev
)) {
3722 /* If nothing else works and the device supports PM reset, use it */
3723 if (vdev
->vbasedev
.reset_works
&& vdev
->has_pm_reset
&&
3724 !ioctl(vdev
->vbasedev
.fd
, VFIO_DEVICE_RESET
)) {
3725 trace_vfio_pci_reset_pm(vdev
->vbasedev
.name
);
3730 vfio_pci_post_reset(vdev
);
3733 static void vfio_instance_init(Object
*obj
)
3735 PCIDevice
*pci_dev
= PCI_DEVICE(obj
);
3736 VFIOPCIDevice
*vdev
= DO_UPCAST(VFIOPCIDevice
, pdev
, PCI_DEVICE(obj
));
3738 device_add_bootindex_property(obj
, &vdev
->bootindex
,
3740 &pci_dev
->qdev
, NULL
);
3743 static Property vfio_pci_dev_properties
[] = {
3744 DEFINE_PROP_PCI_HOST_DEVADDR("host", VFIOPCIDevice
, host
),
3745 DEFINE_PROP_UINT32("x-intx-mmap-timeout-ms", VFIOPCIDevice
,
3746 intx
.mmap_timeout
, 1100),
3747 DEFINE_PROP_BIT("x-vga", VFIOPCIDevice
, features
,
3748 VFIO_FEATURE_ENABLE_VGA_BIT
, false),
3749 DEFINE_PROP_BIT("x-req", VFIOPCIDevice
, features
,
3750 VFIO_FEATURE_ENABLE_REQ_BIT
, true),
3751 DEFINE_PROP_BOOL("x-mmap", VFIOPCIDevice
, vbasedev
.allow_mmap
, true),
3753 * TODO - support passed fds... is this necessary?
3754 * DEFINE_PROP_STRING("vfiofd", VFIOPCIDevice, vfiofd_name),
3755 * DEFINE_PROP_STRING("vfiogroupfd, VFIOPCIDevice, vfiogroupfd_name),
3757 DEFINE_PROP_END_OF_LIST(),
3760 static const VMStateDescription vfio_pci_vmstate
= {
3765 static void vfio_pci_dev_class_init(ObjectClass
*klass
, void *data
)
3767 DeviceClass
*dc
= DEVICE_CLASS(klass
);
3768 PCIDeviceClass
*pdc
= PCI_DEVICE_CLASS(klass
);
3770 dc
->reset
= vfio_pci_reset
;
3771 dc
->props
= vfio_pci_dev_properties
;
3772 dc
->vmsd
= &vfio_pci_vmstate
;
3773 dc
->desc
= "VFIO-based PCI device assignment";
3774 set_bit(DEVICE_CATEGORY_MISC
, dc
->categories
);
3775 pdc
->init
= vfio_initfn
;
3776 pdc
->exit
= vfio_exitfn
;
3777 pdc
->config_read
= vfio_pci_read_config
;
3778 pdc
->config_write
= vfio_pci_write_config
;
3779 pdc
->is_express
= 1; /* We might be */
3782 static const TypeInfo vfio_pci_dev_info
= {
3784 .parent
= TYPE_PCI_DEVICE
,
3785 .instance_size
= sizeof(VFIOPCIDevice
),
3786 .class_init
= vfio_pci_dev_class_init
,
3787 .instance_init
= vfio_instance_init
,
3788 .instance_finalize
= vfio_instance_finalize
,
3791 static void register_vfio_pci_dev_type(void)
3793 type_register_static(&vfio_pci_dev_info
);
3796 type_init(register_vfio_pci_dev_type
)