2 * vfio based device assignment support - PCI devices
4 * Copyright Red Hat, Inc. 2012-2015
7 * Alex Williamson <alex.williamson@redhat.com>
9 * This work is licensed under the terms of the GNU GPL, version 2. See
10 * the COPYING file in the top-level directory.
12 #ifndef HW_VFIO_VFIO_PCI_H
13 #define HW_VFIO_VFIO_PCI_H
15 #include "qemu-common.h"
16 #include "exec/memory.h"
17 #include "hw/pci/pci.h"
18 #include "hw/vfio/vfio-common.h"
19 #include "qemu/event_notifier.h"
20 #include "qemu/queue.h"
21 #include "qemu/timer.h"
23 #define PCI_ANY_ID (~0)
27 typedef struct VFIOQuirk
{
28 QLIST_ENTRY(VFIOQuirk
) next
;
34 typedef struct VFIOBAR
{
41 QLIST_HEAD(, VFIOQuirk
) quirks
;
44 typedef struct VFIOVGARegion
{
48 QLIST_HEAD(, VFIOQuirk
) quirks
;
51 typedef struct VFIOVGA
{
54 VFIOVGARegion region
[QEMU_PCI_VGA_NUM_REGIONS
];
57 typedef struct VFIOINTx
{
58 bool pending
; /* interrupt pending */
59 bool kvm_accel
; /* set when QEMU bypass through KVM enabled */
60 uint8_t pin
; /* which pin to pull for qemu_set_irq */
61 EventNotifier interrupt
; /* eventfd triggered on interrupt */
62 EventNotifier unmask
; /* eventfd for unmask on QEMU bypass */
63 PCIINTxRoute route
; /* routing info for QEMU bypass */
64 uint32_t mmap_timeout
; /* delay to re-enable mmaps after interrupt */
65 QEMUTimer
*mmap_timer
; /* enable mmaps after periods w/o interrupts */
68 typedef struct VFIOMSIVector
{
70 * Two interrupt paths are configured per vector. The first, is only used
71 * for interrupts injected via QEMU. This is typically the non-accel path,
72 * but may also be used when we want QEMU to handle masking and pending
73 * bits. The KVM path bypasses QEMU and is therefore higher performance,
74 * but requires masking at the device. virq is used to track the MSI route
75 * through KVM, thus kvm_interrupt is only available when virq is set to a
78 EventNotifier interrupt
;
79 EventNotifier kvm_interrupt
;
80 struct VFIOPCIDevice
*vdev
; /* back pointer to device */
92 /* Cache of MSI-X setup */
93 typedef struct VFIOMSIXInfo
{
97 uint32_t table_offset
;
99 unsigned long *pending
;
102 typedef struct VFIOPCIDevice
{
106 unsigned int config_size
;
107 uint8_t *emulated_config_bits
; /* QEMU emulated bits, little-endian */
108 off_t config_offset
; /* Offset of config space region within device fd */
109 unsigned int rom_size
;
110 off_t rom_offset
; /* Offset of ROM region within device fd */
113 VFIOMSIVector
*msi_vectors
;
115 int nr_vectors
; /* Number of MSI/MSIX vectors currently in use */
116 int interrupt
; /* Current interrupt type */
117 VFIOBAR bars
[PCI_NUM_REGIONS
- 1]; /* No ROM */
118 VFIOVGA
*vga
; /* 0xa0000, 0x3b0, 0x3c0 */
120 PCIHostDeviceAddress host
;
121 EventNotifier err_notifier
;
122 EventNotifier req_notifier
;
123 int (*resetfn
)(struct VFIOPCIDevice
*);
126 uint32_t sub_vendor_id
;
127 uint32_t sub_device_id
;
129 #define VFIO_FEATURE_ENABLE_VGA_BIT 0
130 #define VFIO_FEATURE_ENABLE_VGA (1 << VFIO_FEATURE_ENABLE_VGA_BIT)
131 #define VFIO_FEATURE_ENABLE_REQ_BIT 1
132 #define VFIO_FEATURE_ENABLE_REQ (1 << VFIO_FEATURE_ENABLE_REQ_BIT)
133 #define VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT 2
134 #define VFIO_FEATURE_ENABLE_IGD_OPREGION \
135 (1 << VFIO_FEATURE_ENABLE_IGD_OPREGION_BIT)
139 OffAutoPCIBAR msix_relo
;
141 uint8_t nv_gpudirect_clique
;
146 bool rom_read_failed
;
150 bool no_geforce_quirks
;
154 uint32_t vfio_pci_read_config(PCIDevice
*pdev
, uint32_t addr
, int len
);
155 void vfio_pci_write_config(PCIDevice
*pdev
,
156 uint32_t addr
, uint32_t val
, int len
);
158 uint64_t vfio_vga_read(void *opaque
, hwaddr addr
, unsigned size
);
159 void vfio_vga_write(void *opaque
, hwaddr addr
, uint64_t data
, unsigned size
);
161 bool vfio_blacklist_opt_rom(VFIOPCIDevice
*vdev
);
162 void vfio_vga_quirk_setup(VFIOPCIDevice
*vdev
);
163 void vfio_vga_quirk_exit(VFIOPCIDevice
*vdev
);
164 void vfio_vga_quirk_finalize(VFIOPCIDevice
*vdev
);
165 void vfio_bar_quirk_setup(VFIOPCIDevice
*vdev
, int nr
);
166 void vfio_bar_quirk_exit(VFIOPCIDevice
*vdev
, int nr
);
167 void vfio_bar_quirk_finalize(VFIOPCIDevice
*vdev
, int nr
);
168 void vfio_setup_resetfn_quirk(VFIOPCIDevice
*vdev
);
169 int vfio_add_virt_caps(VFIOPCIDevice
*vdev
, Error
**errp
);
171 extern const PropertyInfo qdev_prop_nv_gpudirect_clique
;
173 int vfio_populate_vga(VFIOPCIDevice
*vdev
, Error
**errp
);
175 int vfio_pci_igd_opregion_init(VFIOPCIDevice
*vdev
,
176 struct vfio_region_info
*info
,
179 int vfio_display_probe(VFIOPCIDevice
*vdev
, Error
**errp
);
180 void vfio_display_finalize(VFIOPCIDevice
*vdev
);
182 #endif /* HW_VFIO_VFIO_PCI_H */