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[qemu.git] / hw / vmware_vga.c
1 /*
2 * QEMU VMware-SVGA "chipset".
3 *
4 * Copyright (c) 2007 Andrzej Zaborowski <balrog@zabor.org>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw.h"
25 #include "console.h"
26 #include "pci.h"
27
28 #define VERBOSE
29 #define EMBED_STDVGA
30 #undef DIRECT_VRAM
31 #define HW_RECT_ACCEL
32 #define HW_FILL_ACCEL
33 #define HW_MOUSE_ACCEL
34
35 #ifdef EMBED_STDVGA
36 # include "vga_int.h"
37 #endif
38
39 struct vmsvga_state_s {
40 #ifdef EMBED_STDVGA
41 VGA_STATE_COMMON
42 #endif
43
44 int width;
45 int height;
46 int invalidated;
47 int depth;
48 int bypp;
49 int enable;
50 int config;
51 struct {
52 int id;
53 int x;
54 int y;
55 int on;
56 } cursor;
57
58 #ifndef EMBED_STDVGA
59 DisplayState *ds;
60 QEMUConsole *console;
61 int vram_size;
62 ram_addr_t vram_offset;
63 #endif
64 uint8_t *vram;
65 target_phys_addr_t vram_base;
66
67 int index;
68 int scratch_size;
69 uint32_t *scratch;
70 int new_width;
71 int new_height;
72 uint32_t guest;
73 uint32_t svgaid;
74 uint32_t wred;
75 uint32_t wgreen;
76 uint32_t wblue;
77 int syncing;
78 int fb_size;
79
80 union {
81 uint32_t *fifo;
82 struct __attribute__((__packed__)) {
83 uint32_t min;
84 uint32_t max;
85 uint32_t next_cmd;
86 uint32_t stop;
87 /* Add registers here when adding capabilities. */
88 uint32_t fifo[0];
89 } *cmd;
90 };
91
92 #define REDRAW_FIFO_LEN 512
93 struct vmsvga_rect_s {
94 int x, y, w, h;
95 } redraw_fifo[REDRAW_FIFO_LEN];
96 int redraw_fifo_first, redraw_fifo_last;
97 };
98
99 struct pci_vmsvga_state_s {
100 PCIDevice card;
101 struct vmsvga_state_s chip;
102 };
103
104 #define SVGA_MAGIC 0x900000UL
105 #define SVGA_MAKE_ID(ver) (SVGA_MAGIC << 8 | (ver))
106 #define SVGA_ID_0 SVGA_MAKE_ID(0)
107 #define SVGA_ID_1 SVGA_MAKE_ID(1)
108 #define SVGA_ID_2 SVGA_MAKE_ID(2)
109
110 #define SVGA_LEGACY_BASE_PORT 0x4560
111 #define SVGA_INDEX_PORT 0x0
112 #define SVGA_VALUE_PORT 0x1
113 #define SVGA_BIOS_PORT 0x2
114
115 #define SVGA_VERSION_2
116
117 #ifdef SVGA_VERSION_2
118 # define SVGA_ID SVGA_ID_2
119 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
120 # define SVGA_IO_MUL 1
121 # define SVGA_FIFO_SIZE 0x10000
122 # define SVGA_MEM_BASE 0xe0000000
123 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA2
124 #else
125 # define SVGA_ID SVGA_ID_1
126 # define SVGA_IO_BASE SVGA_LEGACY_BASE_PORT
127 # define SVGA_IO_MUL 4
128 # define SVGA_FIFO_SIZE 0x10000
129 # define SVGA_MEM_BASE 0xe0000000
130 # define SVGA_PCI_DEVICE_ID PCI_DEVICE_ID_VMWARE_SVGA
131 #endif
132
133 enum {
134 /* ID 0, 1 and 2 registers */
135 SVGA_REG_ID = 0,
136 SVGA_REG_ENABLE = 1,
137 SVGA_REG_WIDTH = 2,
138 SVGA_REG_HEIGHT = 3,
139 SVGA_REG_MAX_WIDTH = 4,
140 SVGA_REG_MAX_HEIGHT = 5,
141 SVGA_REG_DEPTH = 6,
142 SVGA_REG_BITS_PER_PIXEL = 7, /* Current bpp in the guest */
143 SVGA_REG_PSEUDOCOLOR = 8,
144 SVGA_REG_RED_MASK = 9,
145 SVGA_REG_GREEN_MASK = 10,
146 SVGA_REG_BLUE_MASK = 11,
147 SVGA_REG_BYTES_PER_LINE = 12,
148 SVGA_REG_FB_START = 13,
149 SVGA_REG_FB_OFFSET = 14,
150 SVGA_REG_VRAM_SIZE = 15,
151 SVGA_REG_FB_SIZE = 16,
152
153 /* ID 1 and 2 registers */
154 SVGA_REG_CAPABILITIES = 17,
155 SVGA_REG_MEM_START = 18, /* Memory for command FIFO */
156 SVGA_REG_MEM_SIZE = 19,
157 SVGA_REG_CONFIG_DONE = 20, /* Set when memory area configured */
158 SVGA_REG_SYNC = 21, /* Write to force synchronization */
159 SVGA_REG_BUSY = 22, /* Read to check if sync is done */
160 SVGA_REG_GUEST_ID = 23, /* Set guest OS identifier */
161 SVGA_REG_CURSOR_ID = 24, /* ID of cursor */
162 SVGA_REG_CURSOR_X = 25, /* Set cursor X position */
163 SVGA_REG_CURSOR_Y = 26, /* Set cursor Y position */
164 SVGA_REG_CURSOR_ON = 27, /* Turn cursor on/off */
165 SVGA_REG_HOST_BITS_PER_PIXEL = 28, /* Current bpp in the host */
166 SVGA_REG_SCRATCH_SIZE = 29, /* Number of scratch registers */
167 SVGA_REG_MEM_REGS = 30, /* Number of FIFO registers */
168 SVGA_REG_NUM_DISPLAYS = 31, /* Number of guest displays */
169 SVGA_REG_PITCHLOCK = 32, /* Fixed pitch for all modes */
170
171 SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
172 SVGA_PALETTE_END = SVGA_PALETTE_BASE + 767,
173 SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
174 };
175
176 #define SVGA_CAP_NONE 0
177 #define SVGA_CAP_RECT_FILL (1 << 0)
178 #define SVGA_CAP_RECT_COPY (1 << 1)
179 #define SVGA_CAP_RECT_PAT_FILL (1 << 2)
180 #define SVGA_CAP_LEGACY_OFFSCREEN (1 << 3)
181 #define SVGA_CAP_RASTER_OP (1 << 4)
182 #define SVGA_CAP_CURSOR (1 << 5)
183 #define SVGA_CAP_CURSOR_BYPASS (1 << 6)
184 #define SVGA_CAP_CURSOR_BYPASS_2 (1 << 7)
185 #define SVGA_CAP_8BIT_EMULATION (1 << 8)
186 #define SVGA_CAP_ALPHA_CURSOR (1 << 9)
187 #define SVGA_CAP_GLYPH (1 << 10)
188 #define SVGA_CAP_GLYPH_CLIPPING (1 << 11)
189 #define SVGA_CAP_OFFSCREEN_1 (1 << 12)
190 #define SVGA_CAP_ALPHA_BLEND (1 << 13)
191 #define SVGA_CAP_3D (1 << 14)
192 #define SVGA_CAP_EXTENDED_FIFO (1 << 15)
193 #define SVGA_CAP_MULTIMON (1 << 16)
194 #define SVGA_CAP_PITCHLOCK (1 << 17)
195
196 /*
197 * FIFO offsets (seen as an array of 32-bit words)
198 */
199 enum {
200 /*
201 * The original defined FIFO offsets
202 */
203 SVGA_FIFO_MIN = 0,
204 SVGA_FIFO_MAX, /* The distance from MIN to MAX must be at least 10K */
205 SVGA_FIFO_NEXT_CMD,
206 SVGA_FIFO_STOP,
207
208 /*
209 * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
210 */
211 SVGA_FIFO_CAPABILITIES = 4,
212 SVGA_FIFO_FLAGS,
213 SVGA_FIFO_FENCE,
214 SVGA_FIFO_3D_HWVERSION,
215 SVGA_FIFO_PITCHLOCK,
216 };
217
218 #define SVGA_FIFO_CAP_NONE 0
219 #define SVGA_FIFO_CAP_FENCE (1 << 0)
220 #define SVGA_FIFO_CAP_ACCELFRONT (1 << 1)
221 #define SVGA_FIFO_CAP_PITCHLOCK (1 << 2)
222
223 #define SVGA_FIFO_FLAG_NONE 0
224 #define SVGA_FIFO_FLAG_ACCELFRONT (1 << 0)
225
226 /* These values can probably be changed arbitrarily. */
227 #define SVGA_SCRATCH_SIZE 0x8000
228 #define SVGA_MAX_WIDTH 2360
229 #define SVGA_MAX_HEIGHT 1770
230
231 #ifdef VERBOSE
232 # define GUEST_OS_BASE 0x5001
233 static const char *vmsvga_guest_id[] = {
234 [0x00 ... 0x15] = "an unknown OS",
235 [0x00] = "Dos",
236 [0x01] = "Windows 3.1",
237 [0x02] = "Windows 95",
238 [0x03] = "Windows 98",
239 [0x04] = "Windows ME",
240 [0x05] = "Windows NT",
241 [0x06] = "Windows 2000",
242 [0x07] = "Linux",
243 [0x08] = "OS/2",
244 [0x0a] = "BSD",
245 [0x0b] = "Whistler",
246 [0x15] = "Windows 2003",
247 };
248 #endif
249
250 enum {
251 SVGA_CMD_INVALID_CMD = 0,
252 SVGA_CMD_UPDATE = 1,
253 SVGA_CMD_RECT_FILL = 2,
254 SVGA_CMD_RECT_COPY = 3,
255 SVGA_CMD_DEFINE_BITMAP = 4,
256 SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
257 SVGA_CMD_DEFINE_PIXMAP = 6,
258 SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
259 SVGA_CMD_RECT_BITMAP_FILL = 8,
260 SVGA_CMD_RECT_PIXMAP_FILL = 9,
261 SVGA_CMD_RECT_BITMAP_COPY = 10,
262 SVGA_CMD_RECT_PIXMAP_COPY = 11,
263 SVGA_CMD_FREE_OBJECT = 12,
264 SVGA_CMD_RECT_ROP_FILL = 13,
265 SVGA_CMD_RECT_ROP_COPY = 14,
266 SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
267 SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
268 SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
269 SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
270 SVGA_CMD_DEFINE_CURSOR = 19,
271 SVGA_CMD_DISPLAY_CURSOR = 20,
272 SVGA_CMD_MOVE_CURSOR = 21,
273 SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
274 SVGA_CMD_DRAW_GLYPH = 23,
275 SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
276 SVGA_CMD_UPDATE_VERBOSE = 25,
277 SVGA_CMD_SURFACE_FILL = 26,
278 SVGA_CMD_SURFACE_COPY = 27,
279 SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
280 SVGA_CMD_FRONT_ROP_FILL = 29,
281 SVGA_CMD_FENCE = 30,
282 };
283
284 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
285 enum {
286 SVGA_CURSOR_ON_HIDE = 0,
287 SVGA_CURSOR_ON_SHOW = 1,
288 SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
289 SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
290 };
291
292 static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
293 int x, int y, int w, int h)
294 {
295 #ifndef DIRECT_VRAM
296 int line;
297 int bypl;
298 int width;
299 int start;
300 uint8_t *src;
301 uint8_t *dst;
302
303 if (x + w > s->width) {
304 fprintf(stderr, "%s: update width too large x: %d, w: %d\n",
305 __FUNCTION__, x, w);
306 x = MIN(x, s->width);
307 w = s->width - x;
308 }
309
310 if (y + h > s->height) {
311 fprintf(stderr, "%s: update height too large y: %d, h: %d\n",
312 __FUNCTION__, y, h);
313 y = MIN(y, s->height);
314 h = s->height - y;
315 }
316
317 line = h;
318 bypl = s->bypp * s->width;
319 width = s->bypp * w;
320 start = s->bypp * x + bypl * y;
321 src = s->vram + start;
322 dst = ds_get_data(s->ds) + start;
323
324 for (; line > 0; line --, src += bypl, dst += bypl)
325 memcpy(dst, src, width);
326 #endif
327
328 dpy_update(s->ds, x, y, w, h);
329 }
330
331 static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
332 {
333 #ifndef DIRECT_VRAM
334 memcpy(ds_get_data(s->ds), s->vram, s->bypp * s->width * s->height);
335 #endif
336
337 dpy_update(s->ds, 0, 0, s->width, s->height);
338 }
339
340 #ifdef DIRECT_VRAM
341 # define vmsvga_update_rect_delayed vmsvga_update_rect
342 #else
343 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
344 int x, int y, int w, int h)
345 {
346 struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
347 s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
348 rect->x = x;
349 rect->y = y;
350 rect->w = w;
351 rect->h = h;
352 }
353 #endif
354
355 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
356 {
357 struct vmsvga_rect_s *rect;
358 if (s->invalidated) {
359 s->redraw_fifo_first = s->redraw_fifo_last;
360 return;
361 }
362 /* Overlapping region updates can be optimised out here - if someone
363 * knows a smart algorithm to do that, please share. */
364 while (s->redraw_fifo_first != s->redraw_fifo_last) {
365 rect = &s->redraw_fifo[s->redraw_fifo_first ++];
366 s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
367 vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
368 }
369 }
370
371 #ifdef HW_RECT_ACCEL
372 static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
373 int x0, int y0, int x1, int y1, int w, int h)
374 {
375 # ifdef DIRECT_VRAM
376 uint8_t *vram = ds_get_data(s->ds);
377 # else
378 uint8_t *vram = s->vram;
379 # endif
380 int bypl = s->bypp * s->width;
381 int width = s->bypp * w;
382 int line = h;
383 uint8_t *ptr[2];
384
385 # ifdef DIRECT_VRAM
386 if (s->ds->dpy_copy)
387 qemu_console_copy(s->console, x0, y0, x1, y1, w, h);
388 else
389 # endif
390 {
391 if (y1 > y0) {
392 ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1);
393 ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1);
394 for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl)
395 memmove(ptr[1], ptr[0], width);
396 } else {
397 ptr[0] = vram + s->bypp * x0 + bypl * y0;
398 ptr[1] = vram + s->bypp * x1 + bypl * y1;
399 for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl)
400 memmove(ptr[1], ptr[0], width);
401 }
402 }
403
404 vmsvga_update_rect_delayed(s, x1, y1, w, h);
405 }
406 #endif
407
408 #ifdef HW_FILL_ACCEL
409 static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
410 uint32_t c, int x, int y, int w, int h)
411 {
412 # ifdef DIRECT_VRAM
413 uint8_t *vram = ds_get_data(s->ds);
414 # else
415 uint8_t *vram = s->vram;
416 # endif
417 int bypp = s->bypp;
418 int bypl = bypp * s->width;
419 int width = bypp * w;
420 int line = h;
421 int column;
422 uint8_t *fst = vram + bypp * x + bypl * y;
423 uint8_t *dst;
424 uint8_t *src;
425 uint8_t col[4];
426
427 # ifdef DIRECT_VRAM
428 if (s->ds->dpy_fill)
429 s->ds->dpy_fill(s->ds, x, y, w, h, c);
430 else
431 # endif
432 {
433 col[0] = c;
434 col[1] = c >> 8;
435 col[2] = c >> 16;
436 col[3] = c >> 24;
437
438 if (line --) {
439 dst = fst;
440 src = col;
441 for (column = width; column > 0; column --) {
442 *(dst ++) = *(src ++);
443 if (src - col == bypp)
444 src = col;
445 }
446 dst = fst;
447 for (; line > 0; line --) {
448 dst += bypl;
449 memcpy(dst, fst, width);
450 }
451 }
452 }
453
454 vmsvga_update_rect_delayed(s, x, y, w, h);
455 }
456 #endif
457
458 struct vmsvga_cursor_definition_s {
459 int width;
460 int height;
461 int id;
462 int bpp;
463 int hot_x;
464 int hot_y;
465 uint32_t mask[1024];
466 uint32_t image[1024];
467 };
468
469 #define SVGA_BITMAP_SIZE(w, h) ((((w) + 31) >> 5) * (h))
470 #define SVGA_PIXMAP_SIZE(w, h, bpp) (((((w) * (bpp)) + 31) >> 5) * (h))
471
472 #ifdef HW_MOUSE_ACCEL
473 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
474 struct vmsvga_cursor_definition_s *c)
475 {
476 int i;
477 for (i = SVGA_BITMAP_SIZE(c->width, c->height) - 1; i >= 0; i --)
478 c->mask[i] = ~c->mask[i];
479
480 if (s->ds->cursor_define)
481 s->ds->cursor_define(c->width, c->height, c->bpp, c->hot_x, c->hot_y,
482 (uint8_t *) c->image, (uint8_t *) c->mask);
483 }
484 #endif
485
486 #define CMD(f) le32_to_cpu(s->cmd->f)
487
488 static inline int vmsvga_fifo_empty(struct vmsvga_state_s *s)
489 {
490 if (!s->config || !s->enable)
491 return 1;
492 return (s->cmd->next_cmd == s->cmd->stop);
493 }
494
495 static inline uint32_t vmsvga_fifo_read_raw(struct vmsvga_state_s *s)
496 {
497 uint32_t cmd = s->fifo[CMD(stop) >> 2];
498 s->cmd->stop = cpu_to_le32(CMD(stop) + 4);
499 if (CMD(stop) >= CMD(max))
500 s->cmd->stop = s->cmd->min;
501 return cmd;
502 }
503
504 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
505 {
506 return le32_to_cpu(vmsvga_fifo_read_raw(s));
507 }
508
509 static void vmsvga_fifo_run(struct vmsvga_state_s *s)
510 {
511 uint32_t cmd, colour;
512 int args = 0;
513 int x, y, dx, dy, width, height;
514 struct vmsvga_cursor_definition_s cursor;
515 while (!vmsvga_fifo_empty(s))
516 switch (cmd = vmsvga_fifo_read(s)) {
517 case SVGA_CMD_UPDATE:
518 case SVGA_CMD_UPDATE_VERBOSE:
519 x = vmsvga_fifo_read(s);
520 y = vmsvga_fifo_read(s);
521 width = vmsvga_fifo_read(s);
522 height = vmsvga_fifo_read(s);
523 vmsvga_update_rect_delayed(s, x, y, width, height);
524 break;
525
526 case SVGA_CMD_RECT_FILL:
527 colour = vmsvga_fifo_read(s);
528 x = vmsvga_fifo_read(s);
529 y = vmsvga_fifo_read(s);
530 width = vmsvga_fifo_read(s);
531 height = vmsvga_fifo_read(s);
532 #ifdef HW_FILL_ACCEL
533 vmsvga_fill_rect(s, colour, x, y, width, height);
534 break;
535 #else
536 goto badcmd;
537 #endif
538
539 case SVGA_CMD_RECT_COPY:
540 x = vmsvga_fifo_read(s);
541 y = vmsvga_fifo_read(s);
542 dx = vmsvga_fifo_read(s);
543 dy = vmsvga_fifo_read(s);
544 width = vmsvga_fifo_read(s);
545 height = vmsvga_fifo_read(s);
546 #ifdef HW_RECT_ACCEL
547 vmsvga_copy_rect(s, x, y, dx, dy, width, height);
548 break;
549 #else
550 goto badcmd;
551 #endif
552
553 case SVGA_CMD_DEFINE_CURSOR:
554 cursor.id = vmsvga_fifo_read(s);
555 cursor.hot_x = vmsvga_fifo_read(s);
556 cursor.hot_y = vmsvga_fifo_read(s);
557 cursor.width = x = vmsvga_fifo_read(s);
558 cursor.height = y = vmsvga_fifo_read(s);
559 vmsvga_fifo_read(s);
560 cursor.bpp = vmsvga_fifo_read(s);
561 for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++)
562 cursor.mask[args] = vmsvga_fifo_read_raw(s);
563 for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++)
564 cursor.image[args] = vmsvga_fifo_read_raw(s);
565 #ifdef HW_MOUSE_ACCEL
566 vmsvga_cursor_define(s, &cursor);
567 break;
568 #else
569 args = 0;
570 goto badcmd;
571 #endif
572
573 /*
574 * Other commands that we at least know the number of arguments
575 * for so we can avoid FIFO desync if driver uses them illegally.
576 */
577 case SVGA_CMD_DEFINE_ALPHA_CURSOR:
578 vmsvga_fifo_read(s);
579 vmsvga_fifo_read(s);
580 vmsvga_fifo_read(s);
581 x = vmsvga_fifo_read(s);
582 y = vmsvga_fifo_read(s);
583 args = x * y;
584 goto badcmd;
585 case SVGA_CMD_RECT_ROP_FILL:
586 args = 6;
587 goto badcmd;
588 case SVGA_CMD_RECT_ROP_COPY:
589 args = 7;
590 goto badcmd;
591 case SVGA_CMD_DRAW_GLYPH_CLIPPED:
592 vmsvga_fifo_read(s);
593 vmsvga_fifo_read(s);
594 args = 7 + (vmsvga_fifo_read(s) >> 2);
595 goto badcmd;
596 case SVGA_CMD_SURFACE_ALPHA_BLEND:
597 args = 12;
598 goto badcmd;
599
600 /*
601 * Other commands that are not listed as depending on any
602 * CAPABILITIES bits, but are not described in the README either.
603 */
604 case SVGA_CMD_SURFACE_FILL:
605 case SVGA_CMD_SURFACE_COPY:
606 case SVGA_CMD_FRONT_ROP_FILL:
607 case SVGA_CMD_FENCE:
608 case SVGA_CMD_INVALID_CMD:
609 break; /* Nop */
610
611 default:
612 badcmd:
613 while (args --)
614 vmsvga_fifo_read(s);
615 printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
616 __FUNCTION__, cmd);
617 break;
618 }
619
620 s->syncing = 0;
621 }
622
623 static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
624 {
625 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
626 return s->index;
627 }
628
629 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
630 {
631 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
632 s->index = index;
633 }
634
635 static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
636 {
637 uint32_t caps;
638 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
639 switch (s->index) {
640 case SVGA_REG_ID:
641 return s->svgaid;
642
643 case SVGA_REG_ENABLE:
644 return s->enable;
645
646 case SVGA_REG_WIDTH:
647 return s->width;
648
649 case SVGA_REG_HEIGHT:
650 return s->height;
651
652 case SVGA_REG_MAX_WIDTH:
653 return SVGA_MAX_WIDTH;
654
655 case SVGA_REG_MAX_HEIGHT:
656 return SVGA_MAX_HEIGHT;
657
658 case SVGA_REG_DEPTH:
659 return s->depth;
660
661 case SVGA_REG_BITS_PER_PIXEL:
662 return (s->depth + 7) & ~7;
663
664 case SVGA_REG_PSEUDOCOLOR:
665 return 0x0;
666
667 case SVGA_REG_RED_MASK:
668 return s->wred;
669 case SVGA_REG_GREEN_MASK:
670 return s->wgreen;
671 case SVGA_REG_BLUE_MASK:
672 return s->wblue;
673
674 case SVGA_REG_BYTES_PER_LINE:
675 return ((s->depth + 7) >> 3) * s->new_width;
676
677 case SVGA_REG_FB_START:
678 return s->vram_base;
679
680 case SVGA_REG_FB_OFFSET:
681 return 0x0;
682
683 case SVGA_REG_VRAM_SIZE:
684 return s->vram_size - SVGA_FIFO_SIZE;
685
686 case SVGA_REG_FB_SIZE:
687 return s->fb_size;
688
689 case SVGA_REG_CAPABILITIES:
690 caps = SVGA_CAP_NONE;
691 #ifdef HW_RECT_ACCEL
692 caps |= SVGA_CAP_RECT_COPY;
693 #endif
694 #ifdef HW_FILL_ACCEL
695 caps |= SVGA_CAP_RECT_FILL;
696 #endif
697 #ifdef HW_MOUSE_ACCEL
698 if (s->ds->mouse_set)
699 caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
700 SVGA_CAP_CURSOR_BYPASS;
701 #endif
702 return caps;
703
704 case SVGA_REG_MEM_START:
705 return s->vram_base + s->vram_size - SVGA_FIFO_SIZE;
706
707 case SVGA_REG_MEM_SIZE:
708 return SVGA_FIFO_SIZE;
709
710 case SVGA_REG_CONFIG_DONE:
711 return s->config;
712
713 case SVGA_REG_SYNC:
714 case SVGA_REG_BUSY:
715 return s->syncing;
716
717 case SVGA_REG_GUEST_ID:
718 return s->guest;
719
720 case SVGA_REG_CURSOR_ID:
721 return s->cursor.id;
722
723 case SVGA_REG_CURSOR_X:
724 return s->cursor.x;
725
726 case SVGA_REG_CURSOR_Y:
727 return s->cursor.x;
728
729 case SVGA_REG_CURSOR_ON:
730 return s->cursor.on;
731
732 case SVGA_REG_HOST_BITS_PER_PIXEL:
733 return (s->depth + 7) & ~7;
734
735 case SVGA_REG_SCRATCH_SIZE:
736 return s->scratch_size;
737
738 case SVGA_REG_MEM_REGS:
739 case SVGA_REG_NUM_DISPLAYS:
740 case SVGA_REG_PITCHLOCK:
741 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
742 return 0;
743
744 default:
745 if (s->index >= SVGA_SCRATCH_BASE &&
746 s->index < SVGA_SCRATCH_BASE + s->scratch_size)
747 return s->scratch[s->index - SVGA_SCRATCH_BASE];
748 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
749 }
750
751 return 0;
752 }
753
754 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
755 {
756 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
757 switch (s->index) {
758 case SVGA_REG_ID:
759 if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
760 s->svgaid = value;
761 break;
762
763 case SVGA_REG_ENABLE:
764 s->enable = value;
765 s->config &= !!value;
766 s->width = -1;
767 s->height = -1;
768 s->invalidated = 1;
769 #ifdef EMBED_STDVGA
770 s->invalidate(opaque);
771 #endif
772 if (s->enable)
773 s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height;
774 break;
775
776 case SVGA_REG_WIDTH:
777 s->new_width = value;
778 s->invalidated = 1;
779 break;
780
781 case SVGA_REG_HEIGHT:
782 s->new_height = value;
783 s->invalidated = 1;
784 break;
785
786 case SVGA_REG_DEPTH:
787 case SVGA_REG_BITS_PER_PIXEL:
788 if (value != s->depth) {
789 printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
790 s->config = 0;
791 }
792 break;
793
794 case SVGA_REG_CONFIG_DONE:
795 if (value) {
796 s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
797 /* Check range and alignment. */
798 if ((CMD(min) | CMD(max) |
799 CMD(next_cmd) | CMD(stop)) & 3)
800 break;
801 if (CMD(min) < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
802 break;
803 if (CMD(max) > SVGA_FIFO_SIZE)
804 break;
805 if (CMD(max) < CMD(min) + 10 * 1024)
806 break;
807 }
808 s->config = !!value;
809 break;
810
811 case SVGA_REG_SYNC:
812 s->syncing = 1;
813 vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
814 break;
815
816 case SVGA_REG_GUEST_ID:
817 s->guest = value;
818 #ifdef VERBOSE
819 if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
820 ARRAY_SIZE(vmsvga_guest_id))
821 printf("%s: guest runs %s.\n", __FUNCTION__,
822 vmsvga_guest_id[value - GUEST_OS_BASE]);
823 #endif
824 break;
825
826 case SVGA_REG_CURSOR_ID:
827 s->cursor.id = value;
828 break;
829
830 case SVGA_REG_CURSOR_X:
831 s->cursor.x = value;
832 break;
833
834 case SVGA_REG_CURSOR_Y:
835 s->cursor.y = value;
836 break;
837
838 case SVGA_REG_CURSOR_ON:
839 s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
840 s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
841 #ifdef HW_MOUSE_ACCEL
842 if (s->ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
843 s->ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on);
844 #endif
845 break;
846
847 case SVGA_REG_MEM_REGS:
848 case SVGA_REG_NUM_DISPLAYS:
849 case SVGA_REG_PITCHLOCK:
850 case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
851 break;
852
853 default:
854 if (s->index >= SVGA_SCRATCH_BASE &&
855 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
856 s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
857 break;
858 }
859 printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
860 }
861 }
862
863 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
864 {
865 printf("%s: what are we supposed to return?\n", __FUNCTION__);
866 return 0xcafe;
867 }
868
869 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
870 {
871 printf("%s: what are we supposed to do with (%08x)?\n",
872 __FUNCTION__, data);
873 }
874
875 static inline void vmsvga_size(struct vmsvga_state_s *s)
876 {
877 if (s->new_width != s->width || s->new_height != s->height) {
878 s->width = s->new_width;
879 s->height = s->new_height;
880 qemu_console_resize(s->console, s->width, s->height);
881 s->invalidated = 1;
882 }
883 }
884
885 static void vmsvga_update_display(void *opaque)
886 {
887 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
888 if (!s->enable) {
889 #ifdef EMBED_STDVGA
890 s->update(opaque);
891 #endif
892 return;
893 }
894
895 vmsvga_size(s);
896
897 vmsvga_fifo_run(s);
898 vmsvga_update_rect_flush(s);
899
900 /*
901 * Is it more efficient to look at vram VGA-dirty bits or wait
902 * for the driver to issue SVGA_CMD_UPDATE?
903 */
904 if (s->invalidated) {
905 s->invalidated = 0;
906 vmsvga_update_screen(s);
907 }
908 }
909
910 static void vmsvga_reset(struct vmsvga_state_s *s)
911 {
912 s->index = 0;
913 s->enable = 0;
914 s->config = 0;
915 s->width = -1;
916 s->height = -1;
917 s->svgaid = SVGA_ID;
918 s->depth = ds_get_bits_per_pixel(s->ds) ? ds_get_bits_per_pixel(s->ds) : 24;
919 s->bypp = (s->depth + 7) >> 3;
920 s->cursor.on = 0;
921 s->redraw_fifo_first = 0;
922 s->redraw_fifo_last = 0;
923 switch (s->depth) {
924 case 8:
925 s->wred = 0x00000007;
926 s->wgreen = 0x00000038;
927 s->wblue = 0x000000c0;
928 break;
929 case 15:
930 s->wred = 0x0000001f;
931 s->wgreen = 0x000003e0;
932 s->wblue = 0x00007c00;
933 break;
934 case 16:
935 s->wred = 0x0000001f;
936 s->wgreen = 0x000007e0;
937 s->wblue = 0x0000f800;
938 break;
939 case 24:
940 s->wred = 0x00ff0000;
941 s->wgreen = 0x0000ff00;
942 s->wblue = 0x000000ff;
943 break;
944 case 32:
945 s->wred = 0x00ff0000;
946 s->wgreen = 0x0000ff00;
947 s->wblue = 0x000000ff;
948 break;
949 }
950 s->syncing = 0;
951 }
952
953 static void vmsvga_invalidate_display(void *opaque)
954 {
955 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
956 if (!s->enable) {
957 #ifdef EMBED_STDVGA
958 s->invalidate(opaque);
959 #endif
960 return;
961 }
962
963 s->invalidated = 1;
964 }
965
966 /* save the vga display in a PPM image even if no display is
967 available */
968 static void vmsvga_screen_dump(void *opaque, const char *filename)
969 {
970 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
971 if (!s->enable) {
972 #ifdef EMBED_STDVGA
973 s->screen_dump(opaque, filename);
974 #endif
975 return;
976 }
977
978 if (s->depth == 32) {
979 ppm_save(filename, s->vram, s->width, s->height, ds_get_linesize(s->ds));
980 }
981 }
982
983 static void vmsvga_text_update(void *opaque, console_ch_t *chardata)
984 {
985 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
986
987 if (s->text_update)
988 s->text_update(opaque, chardata);
989 }
990
991 #ifdef DIRECT_VRAM
992 static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr)
993 {
994 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
995 if (addr < s->fb_size)
996 return *(uint8_t *) (ds_get_data(s->ds) + addr);
997 else
998 return *(uint8_t *) (s->vram + addr);
999 }
1000
1001 static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr)
1002 {
1003 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1004 if (addr < s->fb_size)
1005 return *(uint16_t *) (ds_get_data(s->ds) + addr);
1006 else
1007 return *(uint16_t *) (s->vram + addr);
1008 }
1009
1010 static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr)
1011 {
1012 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1013 if (addr < s->fb_size)
1014 return *(uint32_t *) (ds_get_data(s->ds) + addr);
1015 else
1016 return *(uint32_t *) (s->vram + addr);
1017 }
1018
1019 static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr,
1020 uint32_t value)
1021 {
1022 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1023 if (addr < s->fb_size)
1024 *(uint8_t *) (ds_get_data(s->ds) + addr) = value;
1025 else
1026 *(uint8_t *) (s->vram + addr) = value;
1027 }
1028
1029 static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr,
1030 uint32_t value)
1031 {
1032 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1033 if (addr < s->fb_size)
1034 *(uint16_t *) (ds_get_data(s->ds) + addr) = value;
1035 else
1036 *(uint16_t *) (s->vram + addr) = value;
1037 }
1038
1039 static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr,
1040 uint32_t value)
1041 {
1042 struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1043 if (addr < s->fb_size)
1044 *(uint32_t *) (ds_get_data(s->ds) + addr) = value;
1045 else
1046 *(uint32_t *) (s->vram + addr) = value;
1047 }
1048
1049 static CPUReadMemoryFunc *vmsvga_vram_read[] = {
1050 vmsvga_vram_readb,
1051 vmsvga_vram_readw,
1052 vmsvga_vram_readl,
1053 };
1054
1055 static CPUWriteMemoryFunc *vmsvga_vram_write[] = {
1056 vmsvga_vram_writeb,
1057 vmsvga_vram_writew,
1058 vmsvga_vram_writel,
1059 };
1060 #endif
1061
1062 static void vmsvga_save(struct vmsvga_state_s *s, QEMUFile *f)
1063 {
1064 qemu_put_be32(f, s->depth);
1065 qemu_put_be32(f, s->enable);
1066 qemu_put_be32(f, s->config);
1067 qemu_put_be32(f, s->cursor.id);
1068 qemu_put_be32(f, s->cursor.x);
1069 qemu_put_be32(f, s->cursor.y);
1070 qemu_put_be32(f, s->cursor.on);
1071 qemu_put_be32(f, s->index);
1072 qemu_put_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
1073 qemu_put_be32(f, s->new_width);
1074 qemu_put_be32(f, s->new_height);
1075 qemu_put_be32s(f, &s->guest);
1076 qemu_put_be32s(f, &s->svgaid);
1077 qemu_put_be32(f, s->syncing);
1078 qemu_put_be32(f, s->fb_size);
1079 }
1080
1081 static int vmsvga_load(struct vmsvga_state_s *s, QEMUFile *f)
1082 {
1083 int depth;
1084 depth=qemu_get_be32(f);
1085 s->enable=qemu_get_be32(f);
1086 s->config=qemu_get_be32(f);
1087 s->cursor.id=qemu_get_be32(f);
1088 s->cursor.x=qemu_get_be32(f);
1089 s->cursor.y=qemu_get_be32(f);
1090 s->cursor.on=qemu_get_be32(f);
1091 s->index=qemu_get_be32(f);
1092 qemu_get_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
1093 s->new_width=qemu_get_be32(f);
1094 s->new_height=qemu_get_be32(f);
1095 qemu_get_be32s(f, &s->guest);
1096 qemu_get_be32s(f, &s->svgaid);
1097 s->syncing=qemu_get_be32(f);
1098 s->fb_size=qemu_get_be32(f);
1099
1100 if (s->enable && depth != s->depth) {
1101 printf("%s: need colour depth of %i bits to resume operation.\n",
1102 __FUNCTION__, depth);
1103 return -EINVAL;
1104 }
1105
1106 s->invalidated = 1;
1107 if (s->config)
1108 s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
1109
1110 return 0;
1111 }
1112
1113 static void vmsvga_init(struct vmsvga_state_s *s, DisplayState *ds,
1114 uint8_t *vga_ram_base, unsigned long vga_ram_offset,
1115 int vga_ram_size)
1116 {
1117 s->ds = ds;
1118 s->vram = vga_ram_base;
1119 s->vram_size = vga_ram_size;
1120 s->vram_offset = vga_ram_offset;
1121
1122 s->scratch_size = SVGA_SCRATCH_SIZE;
1123 s->scratch = (uint32_t *) qemu_malloc(s->scratch_size * 4);
1124
1125 vmsvga_reset(s);
1126
1127 #ifdef EMBED_STDVGA
1128 vga_common_init((VGAState *) s, ds,
1129 vga_ram_base, vga_ram_offset, vga_ram_size);
1130 vga_init((VGAState *) s);
1131 #endif
1132
1133 s->console = graphic_console_init(ds, vmsvga_update_display,
1134 vmsvga_invalidate_display,
1135 vmsvga_screen_dump,
1136 vmsvga_text_update, s);
1137
1138 #ifdef CONFIG_BOCHS_VBE
1139 /* XXX: use optimized standard vga accesses */
1140 cpu_register_physical_memory(VBE_DISPI_LFB_PHYSICAL_ADDRESS,
1141 vga_ram_size, vga_ram_offset);
1142 #endif
1143 }
1144
1145 static void pci_vmsvga_save(QEMUFile *f, void *opaque)
1146 {
1147 struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
1148 pci_device_save(&s->card, f);
1149 vmsvga_save(&s->chip, f);
1150 }
1151
1152 static int pci_vmsvga_load(QEMUFile *f, void *opaque, int version_id)
1153 {
1154 struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
1155 int ret;
1156
1157 ret = pci_device_load(&s->card, f);
1158 if (ret < 0)
1159 return ret;
1160
1161 ret = vmsvga_load(&s->chip, f);
1162 if (ret < 0)
1163 return ret;
1164
1165 return 0;
1166 }
1167
1168 static void pci_vmsvga_map_ioport(PCIDevice *pci_dev, int region_num,
1169 uint32_t addr, uint32_t size, int type)
1170 {
1171 struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1172 struct vmsvga_state_s *s = &d->chip;
1173
1174 register_ioport_read(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1175 1, 4, vmsvga_index_read, s);
1176 register_ioport_write(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1177 1, 4, vmsvga_index_write, s);
1178 register_ioport_read(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1179 1, 4, vmsvga_value_read, s);
1180 register_ioport_write(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1181 1, 4, vmsvga_value_write, s);
1182 register_ioport_read(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1183 1, 4, vmsvga_bios_read, s);
1184 register_ioport_write(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1185 1, 4, vmsvga_bios_write, s);
1186 }
1187
1188 static void pci_vmsvga_map_mem(PCIDevice *pci_dev, int region_num,
1189 uint32_t addr, uint32_t size, int type)
1190 {
1191 struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1192 struct vmsvga_state_s *s = &d->chip;
1193 ram_addr_t iomemtype;
1194
1195 s->vram_base = addr;
1196 #ifdef DIRECT_VRAM
1197 iomemtype = cpu_register_io_memory(0, vmsvga_vram_read,
1198 vmsvga_vram_write, s);
1199 #else
1200 iomemtype = s->vram_offset | IO_MEM_RAM;
1201 #endif
1202 cpu_register_physical_memory(s->vram_base, s->vram_size,
1203 iomemtype);
1204 }
1205
1206 #define PCI_VENDOR_ID_VMWARE 0x15ad
1207 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
1208 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
1209 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
1210 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
1211 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
1212 #define PCI_CLASS_BASE_DISPLAY 0x03
1213 #define PCI_CLASS_SUB_VGA 0x00
1214 #define PCI_CLASS_HEADERTYPE_00h 0x00
1215
1216 void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
1217 unsigned long vga_ram_offset, int vga_ram_size)
1218 {
1219 struct pci_vmsvga_state_s *s;
1220
1221 /* Setup PCI configuration */
1222 s = (struct pci_vmsvga_state_s *)
1223 pci_register_device(bus, "QEMUware SVGA",
1224 sizeof(struct pci_vmsvga_state_s), -1, 0, 0);
1225 s->card.config[PCI_VENDOR_ID] = PCI_VENDOR_ID_VMWARE & 0xff;
1226 s->card.config[PCI_VENDOR_ID + 1] = PCI_VENDOR_ID_VMWARE >> 8;
1227 s->card.config[PCI_DEVICE_ID] = SVGA_PCI_DEVICE_ID & 0xff;
1228 s->card.config[PCI_DEVICE_ID + 1] = SVGA_PCI_DEVICE_ID >> 8;
1229 s->card.config[PCI_COMMAND] = 0x07; /* I/O + Memory */
1230 s->card.config[PCI_CLASS_DEVICE] = PCI_CLASS_SUB_VGA;
1231 s->card.config[0x0b] = PCI_CLASS_BASE_DISPLAY;
1232 s->card.config[0x0c] = 0x08; /* Cache line size */
1233 s->card.config[0x0d] = 0x40; /* Latency timer */
1234 s->card.config[0x0e] = PCI_CLASS_HEADERTYPE_00h;
1235 s->card.config[0x2c] = PCI_VENDOR_ID_VMWARE & 0xff;
1236 s->card.config[0x2d] = PCI_VENDOR_ID_VMWARE >> 8;
1237 s->card.config[0x2e] = SVGA_PCI_DEVICE_ID & 0xff;
1238 s->card.config[0x2f] = SVGA_PCI_DEVICE_ID >> 8;
1239 s->card.config[0x3c] = 0xff; /* End */
1240
1241 pci_register_io_region(&s->card, 0, 0x10,
1242 PCI_ADDRESS_SPACE_IO, pci_vmsvga_map_ioport);
1243 pci_register_io_region(&s->card, 1, vga_ram_size,
1244 PCI_ADDRESS_SPACE_MEM_PREFETCH, pci_vmsvga_map_mem);
1245
1246 vmsvga_init(&s->chip, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
1247
1248 register_savevm("vmware_vga", 0, 0, pci_vmsvga_save, pci_vmsvga_load, s);
1249 }
Qemu copy for testing