hw/watchdog/cmsdk-apb-watchdog.c

   1 /*
   2  * ARM CMSDK APB watchdog emulation
   3  *
   4  * Copyright (c) 2018 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License version 2 or
   9  *  (at your option) any later version.
  10  */
  11
  12 /*
  13  * This is a model of the "APB watchdog" which is part of the Cortex-M
  14  * System Design Kit (CMSDK) and documented in the Cortex-M System
  15  * Design Kit Technical Reference Manual (ARM DDI0479C):
  16  * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
  17  *
  18  * We also support the variant of this device found in the TI
  19  * Stellaris/Luminary boards and documented in:
  20  * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
  21  */
  22
  23 #include "qemu/osdep.h"
  24 #include "qemu/log.h"
  25 #include "trace.h"
  26 #include "qapi/error.h"
  27 #include "qemu/main-loop.h"
  28 #include "qemu/module.h"
  29 #include "sysemu/watchdog.h"
  30 #include "hw/sysbus.h"
  31 #include "hw/irq.h"
  32 #include "hw/qdev-properties.h"
  33 #include "hw/registerfields.h"
  34 #include "hw/watchdog/cmsdk-apb-watchdog.h"
  35 #include "migration/vmstate.h"
  36
  37 REG32(WDOGLOAD, 0x0)
  38 REG32(WDOGVALUE, 0x4)
  39 REG32(WDOGCONTROL, 0x8)
  40     FIELD(WDOGCONTROL, INTEN, 0, 1)
  41     FIELD(WDOGCONTROL, RESEN, 1, 1)
  42 #define R_WDOGCONTROL_VALID_MASK (R_WDOGCONTROL_INTEN_MASK | \
  43                                   R_WDOGCONTROL_RESEN_MASK)
  44 REG32(WDOGINTCLR, 0xc)
  45 REG32(WDOGRIS, 0x10)
  46     FIELD(WDOGRIS, INT, 0, 1)
  47 REG32(WDOGMIS, 0x14)
  48 REG32(WDOGTEST, 0x418) /* only in Stellaris/Luminary version of the device */
  49 REG32(WDOGLOCK, 0xc00)
  50 #define WDOG_UNLOCK_VALUE 0x1ACCE551
  51 REG32(WDOGITCR, 0xf00)
  52     FIELD(WDOGITCR, ENABLE, 0, 1)
  53 #define R_WDOGITCR_VALID_MASK R_WDOGITCR_ENABLE_MASK
  54 REG32(WDOGITOP, 0xf04)
  55     FIELD(WDOGITOP, WDOGRES, 0, 1)
  56     FIELD(WDOGITOP, WDOGINT, 1, 1)
  57 #define R_WDOGITOP_VALID_MASK (R_WDOGITOP_WDOGRES_MASK | \
  58                                R_WDOGITOP_WDOGINT_MASK)
  59 REG32(PID4, 0xfd0)
  60 REG32(PID5, 0xfd4)
  61 REG32(PID6, 0xfd8)
  62 REG32(PID7, 0xfdc)
  63 REG32(PID0, 0xfe0)
  64 REG32(PID1, 0xfe4)
  65 REG32(PID2, 0xfe8)
  66 REG32(PID3, 0xfec)
  67 REG32(CID0, 0xff0)
  68 REG32(CID1, 0xff4)
  69 REG32(CID2, 0xff8)
  70 REG32(CID3, 0xffc)
  71
  72 /* PID/CID values */
  73 static const uint32_t cmsdk_apb_watchdog_id[] = {
  74     0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
  75     0x24, 0xb8, 0x1b, 0x00, /* PID0..PID3 */
  76     0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
  77 };
  78
  79 static const uint32_t luminary_watchdog_id[] = {
  80     0x00, 0x00, 0x00, 0x00, /* PID4..PID7 */
  81     0x05, 0x18, 0x18, 0x01, /* PID0..PID3 */
  82     0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
  83 };
  84
  85 static bool cmsdk_apb_watchdog_intstatus(CMSDKAPBWatchdog *s)
  86 {
  87     /* Return masked interrupt status */
  88     return s->intstatus && (s->control & R_WDOGCONTROL_INTEN_MASK);
  89 }
  90
  91 static bool cmsdk_apb_watchdog_resetstatus(CMSDKAPBWatchdog *s)
  92 {
  93     /* Return masked reset status */
  94     return s->resetstatus && (s->control & R_WDOGCONTROL_RESEN_MASK);
  95 }
  96
  97 static void cmsdk_apb_watchdog_update(CMSDKAPBWatchdog *s)
  98 {
  99     bool wdogint;
 100     bool wdogres;
 101
 102     if (s->itcr) {
 103         /*
 104          * Not checking that !s->is_luminary since s->itcr can't be written
 105          * when s->is_luminary in the first place.
 106          */
 107         wdogint = s->itop & R_WDOGITOP_WDOGINT_MASK;
 108         wdogres = s->itop & R_WDOGITOP_WDOGRES_MASK;
 109     } else {
 110         wdogint = cmsdk_apb_watchdog_intstatus(s);
 111         wdogres = cmsdk_apb_watchdog_resetstatus(s);
 112     }
 113
 114     qemu_set_irq(s->wdogint, wdogint);
 115     if (wdogres) {
 116         watchdog_perform_action();
 117     }
 118 }
 119
 120 static uint64_t cmsdk_apb_watchdog_read(void *opaque, hwaddr offset,
 121                                         unsigned size)
 122 {
 123     CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);
 124     uint64_t r;
 125
 126     switch (offset) {
 127     case A_WDOGLOAD:
 128         r = ptimer_get_limit(s->timer);
 129         break;
 130     case A_WDOGVALUE:
 131         r = ptimer_get_count(s->timer);
 132         break;
 133     case A_WDOGCONTROL:
 134         r = s->control;
 135         break;
 136     case A_WDOGRIS:
 137         r = s->intstatus;
 138         break;
 139     case A_WDOGMIS:
 140         r = cmsdk_apb_watchdog_intstatus(s);
 141         break;
 142     case A_WDOGLOCK:
 143         r = s->lock;
 144         break;
 145     case A_WDOGITCR:
 146         if (s->is_luminary) {
 147             goto bad_offset;
 148         }
 149         r = s->itcr;
 150         break;
 151     case A_PID4 ... A_CID3:
 152         r = s->id[(offset - A_PID4) / 4];
 153         break;
 154     case A_WDOGINTCLR:
 155     case A_WDOGITOP:
 156         if (s->is_luminary) {
 157             goto bad_offset;
 158         }
 159         qemu_log_mask(LOG_GUEST_ERROR,
 160                       "CMSDK APB watchdog read: read of WO offset %x\n",
 161                       (int)offset);
 162         r = 0;
 163         break;
 164     case A_WDOGTEST:
 165         if (!s->is_luminary) {
 166             goto bad_offset;
 167         }
 168         qemu_log_mask(LOG_UNIMP,
 169                       "Luminary watchdog read: stall not implemented\n");
 170         r = 0;
 171         break;
 172     default:
 173 bad_offset:
 174         qemu_log_mask(LOG_GUEST_ERROR,
 175                       "CMSDK APB watchdog read: bad offset %x\n", (int)offset);
 176         r = 0;
 177         break;
 178     }
 179     trace_cmsdk_apb_watchdog_read(offset, r, size);
 180     return r;
 181 }
 182
 183 static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset,
 184                                      uint64_t value, unsigned size)
 185 {
 186     CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);
 187
 188     trace_cmsdk_apb_watchdog_write(offset, value, size);
 189
 190     if (s->lock && offset != A_WDOGLOCK) {
 191         /* Write access is disabled via WDOGLOCK */
 192         qemu_log_mask(LOG_GUEST_ERROR,
 193                       "CMSDK APB watchdog write: write to locked watchdog\n");
 194         return;
 195     }
 196
 197     switch (offset) {
 198     case A_WDOGLOAD:
 199         /*
 200          * Reset the load value and the current count, and make sure
 201          * we're counting.
 202          */
 203         ptimer_set_limit(s->timer, value, 1);
 204         ptimer_run(s->timer, 0);
 205         break;
 206     case A_WDOGCONTROL:
 207         if (s->is_luminary && 0 != (R_WDOGCONTROL_INTEN_MASK & s->control)) {
 208             /*
 209              * The Luminary version of this device ignores writes to
 210              * this register after the guest has enabled interrupts
 211              * (so they can only be disabled again via reset).
 212              */
 213             break;
 214         }
 215         s->control = value & R_WDOGCONTROL_VALID_MASK;
 216         cmsdk_apb_watchdog_update(s);
 217         break;
 218     case A_WDOGINTCLR:
 219         s->intstatus = 0;
 220         ptimer_set_count(s->timer, ptimer_get_limit(s->timer));
 221         cmsdk_apb_watchdog_update(s);
 222         break;
 223     case A_WDOGLOCK:
 224         s->lock = (value != WDOG_UNLOCK_VALUE);
 225         break;
 226     case A_WDOGITCR:
 227         if (s->is_luminary) {
 228             goto bad_offset;
 229         }
 230         s->itcr = value & R_WDOGITCR_VALID_MASK;
 231         cmsdk_apb_watchdog_update(s);
 232         break;
 233     case A_WDOGITOP:
 234         if (s->is_luminary) {
 235             goto bad_offset;
 236         }
 237         s->itop = value & R_WDOGITOP_VALID_MASK;
 238         cmsdk_apb_watchdog_update(s);
 239         break;
 240     case A_WDOGVALUE:
 241     case A_WDOGRIS:
 242     case A_WDOGMIS:
 243     case A_PID4 ... A_CID3:
 244         qemu_log_mask(LOG_GUEST_ERROR,
 245                       "CMSDK APB watchdog write: write to RO offset 0x%x\n",
 246                       (int)offset);
 247         break;
 248     case A_WDOGTEST:
 249         if (!s->is_luminary) {
 250             goto bad_offset;
 251         }
 252         qemu_log_mask(LOG_UNIMP,
 253                       "Luminary watchdog write: stall not implemented\n");
 254         break;
 255     default:
 256 bad_offset:
 257         qemu_log_mask(LOG_GUEST_ERROR,
 258                       "CMSDK APB watchdog write: bad offset 0x%x\n",
 259                       (int)offset);
 260         break;
 261     }
 262 }
 263
 264 static const MemoryRegionOps cmsdk_apb_watchdog_ops = {
 265     .read = cmsdk_apb_watchdog_read,
 266     .write = cmsdk_apb_watchdog_write,
 267     .endianness = DEVICE_LITTLE_ENDIAN,
 268     /* byte/halfword accesses are just zero-padded on reads and writes */
 269     .impl.min_access_size = 4,
 270     .impl.max_access_size = 4,
 271     .valid.min_access_size = 1,
 272     .valid.max_access_size = 4,
 273 };
 274
 275 static void cmsdk_apb_watchdog_tick(void *opaque)
 276 {
 277     CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);
 278
 279     if (!s->intstatus) {
 280         /* Count expired for the first time: raise interrupt */
 281         s->intstatus = R_WDOGRIS_INT_MASK;
 282     } else {
 283         /* Count expired for the second time: raise reset and stop clock */
 284         s->resetstatus = 1;
 285         ptimer_stop(s->timer);
 286     }
 287     cmsdk_apb_watchdog_update(s);
 288 }
 289
 290 static void cmsdk_apb_watchdog_reset(DeviceState *dev)
 291 {
 292     CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev);
 293
 294     trace_cmsdk_apb_watchdog_reset();
 295     s->control = 0;
 296     s->intstatus = 0;
 297     s->lock = 0;
 298     s->itcr = 0;
 299     s->itop = 0;
 300     s->resetstatus = 0;
 301     /* Set the limit and the count */
 302     ptimer_set_limit(s->timer, 0xffffffff, 1);
 303     ptimer_run(s->timer, 0);
 304 }
 305
 306 static void cmsdk_apb_watchdog_init(Object *obj)
 307 {
 308     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 309     CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(obj);
 310
 311     memory_region_init_io(&s->iomem, obj, &cmsdk_apb_watchdog_ops,
 312                           s, "cmsdk-apb-watchdog", 0x1000);
 313     sysbus_init_mmio(sbd, &s->iomem);
 314     sysbus_init_irq(sbd, &s->wdogint);
 315
 316     s->is_luminary = false;
 317     s->id = cmsdk_apb_watchdog_id;
 318 }
 319
 320 static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp)
 321 {
 322     CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev);
 323     QEMUBH *bh;
 324
 325     if (s->wdogclk_frq == 0) {
 326         error_setg(errp,
 327                    "CMSDK APB watchdog: wdogclk-frq property must be set");
 328         return;
 329     }
 330
 331     bh = qemu_bh_new(cmsdk_apb_watchdog_tick, s);
 332     s->timer = ptimer_init(bh,
 333                            PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD |
 334                            PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT |
 335                            PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
 336                            PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
 337
 338     ptimer_set_freq(s->timer, s->wdogclk_frq);
 339 }
 340
 341 static const VMStateDescription cmsdk_apb_watchdog_vmstate = {
 342     .name = "cmsdk-apb-watchdog",
 343     .version_id = 1,
 344     .minimum_version_id = 1,
 345     .fields = (VMStateField[]) {
 346         VMSTATE_PTIMER(timer, CMSDKAPBWatchdog),
 347         VMSTATE_UINT32(control, CMSDKAPBWatchdog),
 348         VMSTATE_UINT32(intstatus, CMSDKAPBWatchdog),
 349         VMSTATE_UINT32(lock, CMSDKAPBWatchdog),
 350         VMSTATE_UINT32(itcr, CMSDKAPBWatchdog),
 351         VMSTATE_UINT32(itop, CMSDKAPBWatchdog),
 352         VMSTATE_UINT32(resetstatus, CMSDKAPBWatchdog),
 353         VMSTATE_END_OF_LIST()
 354     }
 355 };
 356
 357 static Property cmsdk_apb_watchdog_properties[] = {
 358     DEFINE_PROP_UINT32("wdogclk-frq", CMSDKAPBWatchdog, wdogclk_frq, 0),
 359     DEFINE_PROP_END_OF_LIST(),
 360 };
 361
 362 static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data)
 363 {
 364     DeviceClass *dc = DEVICE_CLASS(klass);
 365
 366     dc->realize = cmsdk_apb_watchdog_realize;
 367     dc->vmsd = &cmsdk_apb_watchdog_vmstate;
 368     dc->reset = cmsdk_apb_watchdog_reset;
 369     dc->props = cmsdk_apb_watchdog_properties;
 370 }
 371
 372 static const TypeInfo cmsdk_apb_watchdog_info = {
 373     .name = TYPE_CMSDK_APB_WATCHDOG,
 374     .parent = TYPE_SYS_BUS_DEVICE,
 375     .instance_size = sizeof(CMSDKAPBWatchdog),
 376     .instance_init = cmsdk_apb_watchdog_init,
 377     .class_init = cmsdk_apb_watchdog_class_init,
 378 };
 379
 380 static void luminary_watchdog_init(Object *obj)
 381 {
 382     CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(obj);
 383
 384     s->is_luminary = true;
 385     s->id = luminary_watchdog_id;
 386 }
 387
 388 static const TypeInfo luminary_watchdog_info = {
 389     .name = TYPE_LUMINARY_WATCHDOG,
 390     .parent = TYPE_CMSDK_APB_WATCHDOG,
 391     .instance_init = luminary_watchdog_init
 392 };
 393
 394 static void cmsdk_apb_watchdog_register_types(void)
 395 {
 396     type_register_static(&cmsdk_apb_watchdog_info);
 397     type_register_static(&luminary_watchdog_info);
 398 }
 399
 400 type_init(cmsdk_apb_watchdog_register_types);