hw/watchdog/cmsdk-apb-watchdog.c

   1 /*
   2  * ARM CMSDK APB watchdog emulation
   3  *
   4  * Copyright (c) 2018 Linaro Limited
   5  * Written by Peter Maydell
   6  *
   7  *  This program is free software; you can redistribute it and/or modify
   8  *  it under the terms of the GNU General Public License version 2 or
   9  *  (at your option) any later version.
  10  */
  11
  12 /*
  13  * This is a model of the "APB watchdog" which is part of the Cortex-M
  14  * System Design Kit (CMSDK) and documented in the Cortex-M System
  15  * Design Kit Technical Reference Manual (ARM DDI0479C):
  16  * https://developer.arm.com/products/system-design/system-design-kits/cortex-m-system-design-kit
  17  *
  18  * We also support the variant of this device found in the TI
  19  * Stellaris/Luminary boards and documented in:
  20  * http://www.ti.com/lit/ds/symlink/lm3s6965.pdf
  21  */
  22
  23 #include "qemu/osdep.h"
  24 #include "qemu/log.h"
  25 #include "trace.h"
  26 #include "qapi/error.h"
  27 #include "qemu/main-loop.h"
  28 #include "qemu/module.h"
  29 #include "sysemu/watchdog.h"
  30 #include "hw/sysbus.h"
  31 #include "hw/irq.h"
  32 #include "hw/registerfields.h"
  33 #include "hw/watchdog/cmsdk-apb-watchdog.h"
  34
  35 REG32(WDOGLOAD, 0x0)
  36 REG32(WDOGVALUE, 0x4)
  37 REG32(WDOGCONTROL, 0x8)
  38     FIELD(WDOGCONTROL, INTEN, 0, 1)
  39     FIELD(WDOGCONTROL, RESEN, 1, 1)
  40 #define R_WDOGCONTROL_VALID_MASK (R_WDOGCONTROL_INTEN_MASK | \
  41                                   R_WDOGCONTROL_RESEN_MASK)
  42 REG32(WDOGINTCLR, 0xc)
  43 REG32(WDOGRIS, 0x10)
  44     FIELD(WDOGRIS, INT, 0, 1)
  45 REG32(WDOGMIS, 0x14)
  46 REG32(WDOGTEST, 0x418) /* only in Stellaris/Luminary version of the device */
  47 REG32(WDOGLOCK, 0xc00)
  48 #define WDOG_UNLOCK_VALUE 0x1ACCE551
  49 REG32(WDOGITCR, 0xf00)
  50     FIELD(WDOGITCR, ENABLE, 0, 1)
  51 #define R_WDOGITCR_VALID_MASK R_WDOGITCR_ENABLE_MASK
  52 REG32(WDOGITOP, 0xf04)
  53     FIELD(WDOGITOP, WDOGRES, 0, 1)
  54     FIELD(WDOGITOP, WDOGINT, 1, 1)
  55 #define R_WDOGITOP_VALID_MASK (R_WDOGITOP_WDOGRES_MASK | \
  56                                R_WDOGITOP_WDOGINT_MASK)
  57 REG32(PID4, 0xfd0)
  58 REG32(PID5, 0xfd4)
  59 REG32(PID6, 0xfd8)
  60 REG32(PID7, 0xfdc)
  61 REG32(PID0, 0xfe0)
  62 REG32(PID1, 0xfe4)
  63 REG32(PID2, 0xfe8)
  64 REG32(PID3, 0xfec)
  65 REG32(CID0, 0xff0)
  66 REG32(CID1, 0xff4)
  67 REG32(CID2, 0xff8)
  68 REG32(CID3, 0xffc)
  69
  70 /* PID/CID values */
  71 static const uint32_t cmsdk_apb_watchdog_id[] = {
  72     0x04, 0x00, 0x00, 0x00, /* PID4..PID7 */
  73     0x24, 0xb8, 0x1b, 0x00, /* PID0..PID3 */
  74     0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
  75 };
  76
  77 static const uint32_t luminary_watchdog_id[] = {
  78     0x00, 0x00, 0x00, 0x00, /* PID4..PID7 */
  79     0x05, 0x18, 0x18, 0x01, /* PID0..PID3 */
  80     0x0d, 0xf0, 0x05, 0xb1, /* CID0..CID3 */
  81 };
  82
  83 static bool cmsdk_apb_watchdog_intstatus(CMSDKAPBWatchdog *s)
  84 {
  85     /* Return masked interrupt status */
  86     return s->intstatus && (s->control & R_WDOGCONTROL_INTEN_MASK);
  87 }
  88
  89 static bool cmsdk_apb_watchdog_resetstatus(CMSDKAPBWatchdog *s)
  90 {
  91     /* Return masked reset status */
  92     return s->resetstatus && (s->control & R_WDOGCONTROL_RESEN_MASK);
  93 }
  94
  95 static void cmsdk_apb_watchdog_update(CMSDKAPBWatchdog *s)
  96 {
  97     bool wdogint;
  98     bool wdogres;
  99
 100     if (s->itcr) {
 101         /*
 102          * Not checking that !s->is_luminary since s->itcr can't be written
 103          * when s->is_luminary in the first place.
 104          */
 105         wdogint = s->itop & R_WDOGITOP_WDOGINT_MASK;
 106         wdogres = s->itop & R_WDOGITOP_WDOGRES_MASK;
 107     } else {
 108         wdogint = cmsdk_apb_watchdog_intstatus(s);
 109         wdogres = cmsdk_apb_watchdog_resetstatus(s);
 110     }
 111
 112     qemu_set_irq(s->wdogint, wdogint);
 113     if (wdogres) {
 114         watchdog_perform_action();
 115     }
 116 }
 117
 118 static uint64_t cmsdk_apb_watchdog_read(void *opaque, hwaddr offset,
 119                                         unsigned size)
 120 {
 121     CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);
 122     uint64_t r;
 123
 124     switch (offset) {
 125     case A_WDOGLOAD:
 126         r = ptimer_get_limit(s->timer);
 127         break;
 128     case A_WDOGVALUE:
 129         r = ptimer_get_count(s->timer);
 130         break;
 131     case A_WDOGCONTROL:
 132         r = s->control;
 133         break;
 134     case A_WDOGRIS:
 135         r = s->intstatus;
 136         break;
 137     case A_WDOGMIS:
 138         r = cmsdk_apb_watchdog_intstatus(s);
 139         break;
 140     case A_WDOGLOCK:
 141         r = s->lock;
 142         break;
 143     case A_WDOGITCR:
 144         if (s->is_luminary) {
 145             goto bad_offset;
 146         }
 147         r = s->itcr;
 148         break;
 149     case A_PID4 ... A_CID3:
 150         r = s->id[(offset - A_PID4) / 4];
 151         break;
 152     case A_WDOGINTCLR:
 153     case A_WDOGITOP:
 154         if (s->is_luminary) {
 155             goto bad_offset;
 156         }
 157         qemu_log_mask(LOG_GUEST_ERROR,
 158                       "CMSDK APB watchdog read: read of WO offset %x\n",
 159                       (int)offset);
 160         r = 0;
 161         break;
 162     case A_WDOGTEST:
 163         if (!s->is_luminary) {
 164             goto bad_offset;
 165         }
 166         qemu_log_mask(LOG_UNIMP,
 167                       "Luminary watchdog read: stall not implemented\n");
 168         r = 0;
 169         break;
 170     default:
 171 bad_offset:
 172         qemu_log_mask(LOG_GUEST_ERROR,
 173                       "CMSDK APB watchdog read: bad offset %x\n", (int)offset);
 174         r = 0;
 175         break;
 176     }
 177     trace_cmsdk_apb_watchdog_read(offset, r, size);
 178     return r;
 179 }
 180
 181 static void cmsdk_apb_watchdog_write(void *opaque, hwaddr offset,
 182                                      uint64_t value, unsigned size)
 183 {
 184     CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);
 185
 186     trace_cmsdk_apb_watchdog_write(offset, value, size);
 187
 188     if (s->lock && offset != A_WDOGLOCK) {
 189         /* Write access is disabled via WDOGLOCK */
 190         qemu_log_mask(LOG_GUEST_ERROR,
 191                       "CMSDK APB watchdog write: write to locked watchdog\n");
 192         return;
 193     }
 194
 195     switch (offset) {
 196     case A_WDOGLOAD:
 197         /*
 198          * Reset the load value and the current count, and make sure
 199          * we're counting.
 200          */
 201         ptimer_set_limit(s->timer, value, 1);
 202         ptimer_run(s->timer, 0);
 203         break;
 204     case A_WDOGCONTROL:
 205         if (s->is_luminary && 0 != (R_WDOGCONTROL_INTEN_MASK & s->control)) {
 206             /*
 207              * The Luminary version of this device ignores writes to
 208              * this register after the guest has enabled interrupts
 209              * (so they can only be disabled again via reset).
 210              */
 211             break;
 212         }
 213         s->control = value & R_WDOGCONTROL_VALID_MASK;
 214         cmsdk_apb_watchdog_update(s);
 215         break;
 216     case A_WDOGINTCLR:
 217         s->intstatus = 0;
 218         ptimer_set_count(s->timer, ptimer_get_limit(s->timer));
 219         cmsdk_apb_watchdog_update(s);
 220         break;
 221     case A_WDOGLOCK:
 222         s->lock = (value != WDOG_UNLOCK_VALUE);
 223         break;
 224     case A_WDOGITCR:
 225         if (s->is_luminary) {
 226             goto bad_offset;
 227         }
 228         s->itcr = value & R_WDOGITCR_VALID_MASK;
 229         cmsdk_apb_watchdog_update(s);
 230         break;
 231     case A_WDOGITOP:
 232         if (s->is_luminary) {
 233             goto bad_offset;
 234         }
 235         s->itop = value & R_WDOGITOP_VALID_MASK;
 236         cmsdk_apb_watchdog_update(s);
 237         break;
 238     case A_WDOGVALUE:
 239     case A_WDOGRIS:
 240     case A_WDOGMIS:
 241     case A_PID4 ... A_CID3:
 242         qemu_log_mask(LOG_GUEST_ERROR,
 243                       "CMSDK APB watchdog write: write to RO offset 0x%x\n",
 244                       (int)offset);
 245         break;
 246     case A_WDOGTEST:
 247         if (!s->is_luminary) {
 248             goto bad_offset;
 249         }
 250         qemu_log_mask(LOG_UNIMP,
 251                       "Luminary watchdog write: stall not implemented\n");
 252         break;
 253     default:
 254 bad_offset:
 255         qemu_log_mask(LOG_GUEST_ERROR,
 256                       "CMSDK APB watchdog write: bad offset 0x%x\n",
 257                       (int)offset);
 258         break;
 259     }
 260 }
 261
 262 static const MemoryRegionOps cmsdk_apb_watchdog_ops = {
 263     .read = cmsdk_apb_watchdog_read,
 264     .write = cmsdk_apb_watchdog_write,
 265     .endianness = DEVICE_LITTLE_ENDIAN,
 266     /* byte/halfword accesses are just zero-padded on reads and writes */
 267     .impl.min_access_size = 4,
 268     .impl.max_access_size = 4,
 269     .valid.min_access_size = 1,
 270     .valid.max_access_size = 4,
 271 };
 272
 273 static void cmsdk_apb_watchdog_tick(void *opaque)
 274 {
 275     CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(opaque);
 276
 277     if (!s->intstatus) {
 278         /* Count expired for the first time: raise interrupt */
 279         s->intstatus = R_WDOGRIS_INT_MASK;
 280     } else {
 281         /* Count expired for the second time: raise reset and stop clock */
 282         s->resetstatus = 1;
 283         ptimer_stop(s->timer);
 284     }
 285     cmsdk_apb_watchdog_update(s);
 286 }
 287
 288 static void cmsdk_apb_watchdog_reset(DeviceState *dev)
 289 {
 290     CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev);
 291
 292     trace_cmsdk_apb_watchdog_reset();
 293     s->control = 0;
 294     s->intstatus = 0;
 295     s->lock = 0;
 296     s->itcr = 0;
 297     s->itop = 0;
 298     s->resetstatus = 0;
 299     /* Set the limit and the count */
 300     ptimer_set_limit(s->timer, 0xffffffff, 1);
 301     ptimer_run(s->timer, 0);
 302 }
 303
 304 static void cmsdk_apb_watchdog_init(Object *obj)
 305 {
 306     SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
 307     CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(obj);
 308
 309     memory_region_init_io(&s->iomem, obj, &cmsdk_apb_watchdog_ops,
 310                           s, "cmsdk-apb-watchdog", 0x1000);
 311     sysbus_init_mmio(sbd, &s->iomem);
 312     sysbus_init_irq(sbd, &s->wdogint);
 313
 314     s->is_luminary = false;
 315     s->id = cmsdk_apb_watchdog_id;
 316 }
 317
 318 static void cmsdk_apb_watchdog_realize(DeviceState *dev, Error **errp)
 319 {
 320     CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(dev);
 321     QEMUBH *bh;
 322
 323     if (s->wdogclk_frq == 0) {
 324         error_setg(errp,
 325                    "CMSDK APB watchdog: wdogclk-frq property must be set");
 326         return;
 327     }
 328
 329     bh = qemu_bh_new(cmsdk_apb_watchdog_tick, s);
 330     s->timer = ptimer_init(bh,
 331                            PTIMER_POLICY_WRAP_AFTER_ONE_PERIOD |
 332                            PTIMER_POLICY_TRIGGER_ONLY_ON_DECREMENT |
 333                            PTIMER_POLICY_NO_IMMEDIATE_RELOAD |
 334                            PTIMER_POLICY_NO_COUNTER_ROUND_DOWN);
 335
 336     ptimer_set_freq(s->timer, s->wdogclk_frq);
 337 }
 338
 339 static const VMStateDescription cmsdk_apb_watchdog_vmstate = {
 340     .name = "cmsdk-apb-watchdog",
 341     .version_id = 1,
 342     .minimum_version_id = 1,
 343     .fields = (VMStateField[]) {
 344         VMSTATE_PTIMER(timer, CMSDKAPBWatchdog),
 345         VMSTATE_UINT32(control, CMSDKAPBWatchdog),
 346         VMSTATE_UINT32(intstatus, CMSDKAPBWatchdog),
 347         VMSTATE_UINT32(lock, CMSDKAPBWatchdog),
 348         VMSTATE_UINT32(itcr, CMSDKAPBWatchdog),
 349         VMSTATE_UINT32(itop, CMSDKAPBWatchdog),
 350         VMSTATE_UINT32(resetstatus, CMSDKAPBWatchdog),
 351         VMSTATE_END_OF_LIST()
 352     }
 353 };
 354
 355 static Property cmsdk_apb_watchdog_properties[] = {
 356     DEFINE_PROP_UINT32("wdogclk-frq", CMSDKAPBWatchdog, wdogclk_frq, 0),
 357     DEFINE_PROP_END_OF_LIST(),
 358 };
 359
 360 static void cmsdk_apb_watchdog_class_init(ObjectClass *klass, void *data)
 361 {
 362     DeviceClass *dc = DEVICE_CLASS(klass);
 363
 364     dc->realize = cmsdk_apb_watchdog_realize;
 365     dc->vmsd = &cmsdk_apb_watchdog_vmstate;
 366     dc->reset = cmsdk_apb_watchdog_reset;
 367     dc->props = cmsdk_apb_watchdog_properties;
 368 }
 369
 370 static const TypeInfo cmsdk_apb_watchdog_info = {
 371     .name = TYPE_CMSDK_APB_WATCHDOG,
 372     .parent = TYPE_SYS_BUS_DEVICE,
 373     .instance_size = sizeof(CMSDKAPBWatchdog),
 374     .instance_init = cmsdk_apb_watchdog_init,
 375     .class_init = cmsdk_apb_watchdog_class_init,
 376 };
 377
 378 static void luminary_watchdog_init(Object *obj)
 379 {
 380     CMSDKAPBWatchdog *s = CMSDK_APB_WATCHDOG(obj);
 381
 382     s->is_luminary = true;
 383     s->id = luminary_watchdog_id;
 384 }
 385
 386 static const TypeInfo luminary_watchdog_info = {
 387     .name = TYPE_LUMINARY_WATCHDOG,
 388     .parent = TYPE_CMSDK_APB_WATCHDOG,
 389     .instance_init = luminary_watchdog_init
 390 };
 391
 392 static void cmsdk_apb_watchdog_register_types(void)
 393 {
 394     type_register_static(&cmsdk_apb_watchdog_info);
 395     type_register_static(&luminary_watchdog_info);
 396 }
 397
 398 type_init(cmsdk_apb_watchdog_register_types);