hw/watchdog/wdt_aspeed.c

   1 /*
   2  * ASPEED Watchdog Controller
   3  *
   4  * Copyright (C) 2016-2017 IBM Corp.
   5  *
   6  * This code is licensed under the GPL version 2 or later. See the
   7  * COPYING file in the top-level directory.
   8  */
   9
  10 #include "qemu/osdep.h"
  11
  12 #include "qapi/error.h"
  13 #include "qemu/log.h"
  14 #include "qemu/module.h"
  15 #include "qemu/timer.h"
  16 #include "sysemu/watchdog.h"
  17 #include "hw/misc/aspeed_scu.h"
  18 #include "hw/qdev-properties.h"
  19 #include "hw/sysbus.h"
  20 #include "hw/watchdog/wdt_aspeed.h"
  21 #include "migration/vmstate.h"
  22 #include "trace.h"
  23
  24 #define WDT_STATUS                      (0x00 / 4)
  25 #define WDT_RELOAD_VALUE                (0x04 / 4)
  26 #define WDT_RESTART                     (0x08 / 4)
  27 #define WDT_CTRL                        (0x0C / 4)
  28 #define   WDT_CTRL_RESET_MODE_SOC       (0x00 << 5)
  29 #define   WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
  30 #define   WDT_CTRL_1MHZ_CLK             BIT(4)
  31 #define   WDT_CTRL_WDT_EXT              BIT(3)
  32 #define   WDT_CTRL_WDT_INTR             BIT(2)
  33 #define   WDT_CTRL_RESET_SYSTEM         BIT(1)
  34 #define   WDT_CTRL_ENABLE               BIT(0)
  35 #define WDT_RESET_WIDTH                 (0x18 / 4)
  36 #define   WDT_RESET_WIDTH_ACTIVE_HIGH   BIT(31)
  37 #define     WDT_POLARITY_MASK           (0xFF << 24)
  38 #define     WDT_ACTIVE_HIGH_MAGIC       (0xA5 << 24)
  39 #define     WDT_ACTIVE_LOW_MAGIC        (0x5A << 24)
  40 #define   WDT_RESET_WIDTH_PUSH_PULL     BIT(30)
  41 #define     WDT_DRIVE_TYPE_MASK         (0xFF << 24)
  42 #define     WDT_PUSH_PULL_MAGIC         (0xA8 << 24)
  43 #define     WDT_OPEN_DRAIN_MAGIC        (0x8A << 24)
  44 #define WDT_RESET_MASK1                 (0x1c / 4)
  45
  46 #define WDT_TIMEOUT_STATUS              (0x10 / 4)
  47 #define WDT_TIMEOUT_CLEAR               (0x14 / 4)
  48
  49 #define WDT_RESTART_MAGIC               0x4755
  50
  51 #define AST2600_SCU_RESET_CONTROL1      (0x40 / 4)
  52 #define SCU_RESET_CONTROL1              (0x04 / 4)
  53 #define    SCU_RESET_SDRAM              BIT(0)
  54
  55 static bool aspeed_wdt_is_enabled(const AspeedWDTState *s)
  56 {
  57     return s->regs[WDT_CTRL] & WDT_CTRL_ENABLE;
  58 }
  59
  60 static uint64_t aspeed_wdt_read(void *opaque, hwaddr offset, unsigned size)
  61 {
  62     AspeedWDTState *s = ASPEED_WDT(opaque);
  63
  64     trace_aspeed_wdt_read(offset, size);
  65
  66     offset >>= 2;
  67
  68     switch (offset) {
  69     case WDT_STATUS:
  70         return s->regs[WDT_STATUS];
  71     case WDT_RELOAD_VALUE:
  72         return s->regs[WDT_RELOAD_VALUE];
  73     case WDT_RESTART:
  74         qemu_log_mask(LOG_GUEST_ERROR,
  75                       "%s: read from write-only reg at offset 0x%"
  76                       HWADDR_PRIx "\n", __func__, offset);
  77         return 0;
  78     case WDT_CTRL:
  79         return s->regs[WDT_CTRL];
  80     case WDT_RESET_WIDTH:
  81         return s->regs[WDT_RESET_WIDTH];
  82     case WDT_RESET_MASK1:
  83         return s->regs[WDT_RESET_MASK1];
  84     case WDT_TIMEOUT_STATUS:
  85     case WDT_TIMEOUT_CLEAR:
  86         qemu_log_mask(LOG_UNIMP,
  87                       "%s: uninmplemented read at offset 0x%" HWADDR_PRIx "\n",
  88                       __func__, offset);
  89         return 0;
  90     default:
  91         qemu_log_mask(LOG_GUEST_ERROR,
  92                       "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n",
  93                       __func__, offset);
  94         return 0;
  95     }
  96
  97 }
  98
  99 static void aspeed_wdt_reload(AspeedWDTState *s)
 100 {
 101     uint64_t reload;
 102
 103     if (!(s->regs[WDT_CTRL] & WDT_CTRL_1MHZ_CLK)) {
 104         reload = muldiv64(s->regs[WDT_RELOAD_VALUE], NANOSECONDS_PER_SECOND,
 105                           s->pclk_freq);
 106     } else {
 107         reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL;
 108     }
 109
 110     if (aspeed_wdt_is_enabled(s)) {
 111         timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload);
 112     }
 113 }
 114
 115 static void aspeed_wdt_reload_1mhz(AspeedWDTState *s)
 116 {
 117     uint64_t reload = s->regs[WDT_RELOAD_VALUE] * 1000ULL;
 118
 119     if (aspeed_wdt_is_enabled(s)) {
 120         timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + reload);
 121     }
 122 }
 123
 124 static uint64_t aspeed_2400_sanitize_ctrl(uint64_t data)
 125 {
 126     return data & 0xffff;
 127 }
 128
 129 static uint64_t aspeed_2500_sanitize_ctrl(uint64_t data)
 130 {
 131     return (data & ~(0xfUL << 8)) | WDT_CTRL_1MHZ_CLK;
 132 }
 133
 134 static uint64_t aspeed_2600_sanitize_ctrl(uint64_t data)
 135 {
 136     return data & ~(0x7UL << 7);
 137 }
 138
 139 static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
 140                              unsigned size)
 141 {
 142     AspeedWDTState *s = ASPEED_WDT(opaque);
 143     AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(s);
 144     bool enable;
 145
 146     trace_aspeed_wdt_write(offset, size, data);
 147
 148     offset >>= 2;
 149
 150     switch (offset) {
 151     case WDT_STATUS:
 152         qemu_log_mask(LOG_GUEST_ERROR,
 153                       "%s: write to read-only reg at offset 0x%"
 154                       HWADDR_PRIx "\n", __func__, offset);
 155         break;
 156     case WDT_RELOAD_VALUE:
 157         s->regs[WDT_RELOAD_VALUE] = data;
 158         break;
 159     case WDT_RESTART:
 160         if ((data & 0xFFFF) == WDT_RESTART_MAGIC) {
 161             s->regs[WDT_STATUS] = s->regs[WDT_RELOAD_VALUE];
 162             awc->wdt_reload(s);
 163         }
 164         break;
 165     case WDT_CTRL:
 166         data = awc->sanitize_ctrl(data);
 167         enable = data & WDT_CTRL_ENABLE;
 168         if (enable && !aspeed_wdt_is_enabled(s)) {
 169             s->regs[WDT_CTRL] = data;
 170             awc->wdt_reload(s);
 171         } else if (!enable && aspeed_wdt_is_enabled(s)) {
 172             s->regs[WDT_CTRL] = data;
 173             timer_del(s->timer);
 174         } else {
 175             s->regs[WDT_CTRL] = data;
 176         }
 177         break;
 178     case WDT_RESET_WIDTH:
 179         if (awc->reset_pulse) {
 180             awc->reset_pulse(s, data & WDT_POLARITY_MASK);
 181         }
 182         s->regs[WDT_RESET_WIDTH] &= ~awc->ext_pulse_width_mask;
 183         s->regs[WDT_RESET_WIDTH] |= data & awc->ext_pulse_width_mask;
 184         break;
 185
 186     case WDT_RESET_MASK1:
 187         /* TODO: implement */
 188         s->regs[WDT_RESET_MASK1] = data;
 189         break;
 190
 191     case WDT_TIMEOUT_STATUS:
 192     case WDT_TIMEOUT_CLEAR:
 193         qemu_log_mask(LOG_UNIMP,
 194                       "%s: uninmplemented write at offset 0x%" HWADDR_PRIx "\n",
 195                       __func__, offset);
 196         break;
 197     default:
 198         qemu_log_mask(LOG_GUEST_ERROR,
 199                       "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n",
 200                       __func__, offset);
 201     }
 202     return;
 203 }
 204
 205 static const VMStateDescription vmstate_aspeed_wdt = {
 206     .name = "vmstate_aspeed_wdt",
 207     .version_id = 0,
 208     .minimum_version_id = 0,
 209     .fields = (VMStateField[]) {
 210         VMSTATE_TIMER_PTR(timer, AspeedWDTState),
 211         VMSTATE_UINT32_ARRAY(regs, AspeedWDTState, ASPEED_WDT_REGS_MAX),
 212         VMSTATE_END_OF_LIST()
 213     }
 214 };
 215
 216 static const MemoryRegionOps aspeed_wdt_ops = {
 217     .read = aspeed_wdt_read,
 218     .write = aspeed_wdt_write,
 219     .endianness = DEVICE_LITTLE_ENDIAN,
 220     .valid.min_access_size = 4,
 221     .valid.max_access_size = 4,
 222     .valid.unaligned = false,
 223 };
 224
 225 static void aspeed_wdt_reset(DeviceState *dev)
 226 {
 227     AspeedWDTState *s = ASPEED_WDT(dev);
 228     AspeedWDTClass *awc = ASPEED_WDT_GET_CLASS(s);
 229
 230     s->regs[WDT_STATUS] = awc->default_status;
 231     s->regs[WDT_RELOAD_VALUE] = awc->default_reload_value;
 232     s->regs[WDT_RESTART] = 0;
 233     s->regs[WDT_CTRL] = awc->sanitize_ctrl(0);
 234     s->regs[WDT_RESET_WIDTH] = 0xFF;
 235
 236     timer_del(s->timer);
 237 }
 238
 239 static void aspeed_wdt_timer_expired(void *dev)
 240 {
 241     AspeedWDTState *s = ASPEED_WDT(dev);
 242     uint32_t reset_ctrl_reg = ASPEED_WDT_GET_CLASS(s)->reset_ctrl_reg;
 243
 244     /* Do not reset on SDRAM controller reset */
 245     if (s->scu->regs[reset_ctrl_reg] & SCU_RESET_SDRAM) {
 246         timer_del(s->timer);
 247         s->regs[WDT_CTRL] = 0;
 248         return;
 249     }
 250
 251     qemu_log_mask(CPU_LOG_RESET, "Watchdog timer %" HWADDR_PRIx " expired.\n",
 252                   s->iomem.addr);
 253     watchdog_perform_action();
 254     timer_del(s->timer);
 255 }
 256
 257 #define PCLK_HZ 24000000
 258
 259 static void aspeed_wdt_realize(DeviceState *dev, Error **errp)
 260 {
 261     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
 262     AspeedWDTState *s = ASPEED_WDT(dev);
 263
 264     assert(s->scu);
 265
 266     s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, aspeed_wdt_timer_expired, dev);
 267
 268     /* FIXME: This setting should be derived from the SCU hw strapping
 269      * register SCU70
 270      */
 271     s->pclk_freq = PCLK_HZ;
 272
 273     memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_wdt_ops, s,
 274                           TYPE_ASPEED_WDT, ASPEED_WDT_REGS_MAX * 4);
 275     sysbus_init_mmio(sbd, &s->iomem);
 276 }
 277
 278 static Property aspeed_wdt_properties[] = {
 279     DEFINE_PROP_LINK("scu", AspeedWDTState, scu, TYPE_ASPEED_SCU,
 280                      AspeedSCUState *),
 281     DEFINE_PROP_END_OF_LIST(),
 282 };
 283
 284 static void aspeed_wdt_class_init(ObjectClass *klass, void *data)
 285 {
 286     DeviceClass *dc = DEVICE_CLASS(klass);
 287
 288     dc->desc = "ASPEED Watchdog Controller";
 289     dc->realize = aspeed_wdt_realize;
 290     dc->reset = aspeed_wdt_reset;
 291     set_bit(DEVICE_CATEGORY_WATCHDOG, dc->categories);
 292     dc->vmsd = &vmstate_aspeed_wdt;
 293     device_class_set_props(dc, aspeed_wdt_properties);
 294     dc->desc = "Aspeed watchdog device";
 295 }
 296
 297 static const TypeInfo aspeed_wdt_info = {
 298     .parent = TYPE_SYS_BUS_DEVICE,
 299     .name  = TYPE_ASPEED_WDT,
 300     .instance_size  = sizeof(AspeedWDTState),
 301     .class_init = aspeed_wdt_class_init,
 302     .class_size    = sizeof(AspeedWDTClass),
 303     .abstract      = true,
 304 };
 305
 306 static void aspeed_2400_wdt_class_init(ObjectClass *klass, void *data)
 307 {
 308     DeviceClass *dc = DEVICE_CLASS(klass);
 309     AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
 310
 311     dc->desc = "ASPEED 2400 Watchdog Controller";
 312     awc->offset = 0x20;
 313     awc->ext_pulse_width_mask = 0xff;
 314     awc->reset_ctrl_reg = SCU_RESET_CONTROL1;
 315     awc->wdt_reload = aspeed_wdt_reload;
 316     awc->sanitize_ctrl = aspeed_2400_sanitize_ctrl;
 317     awc->default_status = 0x03EF1480;
 318     awc->default_reload_value = 0x03EF1480;
 319 }
 320
 321 static const TypeInfo aspeed_2400_wdt_info = {
 322     .name = TYPE_ASPEED_2400_WDT,
 323     .parent = TYPE_ASPEED_WDT,
 324     .instance_size = sizeof(AspeedWDTState),
 325     .class_init = aspeed_2400_wdt_class_init,
 326 };
 327
 328 static void aspeed_2500_wdt_reset_pulse(AspeedWDTState *s, uint32_t property)
 329 {
 330     if (property) {
 331         if (property == WDT_ACTIVE_HIGH_MAGIC) {
 332             s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_ACTIVE_HIGH;
 333         } else if (property == WDT_ACTIVE_LOW_MAGIC) {
 334             s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_ACTIVE_HIGH;
 335         } else if (property == WDT_PUSH_PULL_MAGIC) {
 336             s->regs[WDT_RESET_WIDTH] |= WDT_RESET_WIDTH_PUSH_PULL;
 337         } else if (property == WDT_OPEN_DRAIN_MAGIC) {
 338             s->regs[WDT_RESET_WIDTH] &= ~WDT_RESET_WIDTH_PUSH_PULL;
 339         }
 340     }
 341 }
 342
 343 static void aspeed_2500_wdt_class_init(ObjectClass *klass, void *data)
 344 {
 345     DeviceClass *dc = DEVICE_CLASS(klass);
 346     AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
 347
 348     dc->desc = "ASPEED 2500 Watchdog Controller";
 349     awc->offset = 0x20;
 350     awc->ext_pulse_width_mask = 0xfffff;
 351     awc->reset_ctrl_reg = SCU_RESET_CONTROL1;
 352     awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
 353     awc->wdt_reload = aspeed_wdt_reload_1mhz;
 354     awc->sanitize_ctrl = aspeed_2500_sanitize_ctrl;
 355     awc->default_status = 0x014FB180;
 356     awc->default_reload_value = 0x014FB180;
 357 }
 358
 359 static const TypeInfo aspeed_2500_wdt_info = {
 360     .name = TYPE_ASPEED_2500_WDT,
 361     .parent = TYPE_ASPEED_WDT,
 362     .instance_size = sizeof(AspeedWDTState),
 363     .class_init = aspeed_2500_wdt_class_init,
 364 };
 365
 366 static void aspeed_2600_wdt_class_init(ObjectClass *klass, void *data)
 367 {
 368     DeviceClass *dc = DEVICE_CLASS(klass);
 369     AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
 370
 371     dc->desc = "ASPEED 2600 Watchdog Controller";
 372     awc->offset = 0x40;
 373     awc->ext_pulse_width_mask = 0xfffff; /* TODO */
 374     awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
 375     awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
 376     awc->wdt_reload = aspeed_wdt_reload_1mhz;
 377     awc->sanitize_ctrl = aspeed_2600_sanitize_ctrl;
 378     awc->default_status = 0x014FB180;
 379     awc->default_reload_value = 0x014FB180;
 380 }
 381
 382 static const TypeInfo aspeed_2600_wdt_info = {
 383     .name = TYPE_ASPEED_2600_WDT,
 384     .parent = TYPE_ASPEED_WDT,
 385     .instance_size = sizeof(AspeedWDTState),
 386     .class_init = aspeed_2600_wdt_class_init,
 387 };
 388
 389 static void aspeed_1030_wdt_class_init(ObjectClass *klass, void *data)
 390 {
 391     DeviceClass *dc = DEVICE_CLASS(klass);
 392     AspeedWDTClass *awc = ASPEED_WDT_CLASS(klass);
 393
 394     dc->desc = "ASPEED 1030 Watchdog Controller";
 395     awc->offset = 0x80;
 396     awc->ext_pulse_width_mask = 0xfffff; /* TODO */
 397     awc->reset_ctrl_reg = AST2600_SCU_RESET_CONTROL1;
 398     awc->reset_pulse = aspeed_2500_wdt_reset_pulse;
 399     awc->wdt_reload = aspeed_wdt_reload_1mhz;
 400     awc->sanitize_ctrl = aspeed_2600_sanitize_ctrl;
 401     awc->default_status = 0x014FB180;
 402     awc->default_reload_value = 0x014FB180;
 403 }
 404
 405 static const TypeInfo aspeed_1030_wdt_info = {
 406     .name = TYPE_ASPEED_1030_WDT,
 407     .parent = TYPE_ASPEED_WDT,
 408     .instance_size = sizeof(AspeedWDTState),
 409     .class_init = aspeed_1030_wdt_class_init,
 410 };
 411
 412 static void wdt_aspeed_register_types(void)
 413 {
 414     type_register_static(&aspeed_wdt_info);
 415     type_register_static(&aspeed_2400_wdt_info);
 416     type_register_static(&aspeed_2500_wdt_info);
 417     type_register_static(&aspeed_2600_wdt_info);
 418     type_register_static(&aspeed_1030_wdt_info);
 419 }
 420
 421 type_init(wdt_aspeed_register_types)