2 * Copyright (c) 2007, Neocleus Corporation.
3 * Copyright (c) 2007, Intel Corporation.
5 * This work is licensed under the terms of the GNU GPL, version 2. See
6 * the COPYING file in the top-level directory.
8 * Alex Novik <alex@neocleus.com>
9 * Allen Kay <allen.m.kay@intel.com>
10 * Guy Zana <guy@neocleus.com>
12 * This file implements direct PCI assignment to a HVM guest
15 #include "qemu/timer.h"
16 #include "hw/xen/xen_backend.h"
19 #define XEN_PT_MERGE_VALUE(value, data, val_mask) \
20 (((value) & (val_mask)) | ((data) & ~(val_mask)))
22 #define XEN_PT_INVALID_REG 0xFFFFFFFF /* invalid register value */
26 static int xen_pt_ptr_reg_init(XenPCIPassthroughState
*s
, XenPTRegInfo
*reg
,
27 uint32_t real_offset
, uint32_t *data
);
32 /* A return value of 1 means the capability should NOT be exposed to guest. */
33 static int xen_pt_hide_dev_cap(const XenHostPCIDevice
*d
, uint8_t grp_id
)
37 /* The PCI Express Capability Structure of the VF of Intel 82599 10GbE
38 * Controller looks trivial, e.g., the PCI Express Capabilities
39 * Register is 0. We should not try to expose it to guest.
41 * The datasheet is available at
42 * http://download.intel.com/design/network/datashts/82599_datasheet.pdf
44 * See 'Table 9.7. VF PCIe Configuration Space' of the datasheet, the
45 * PCI Express Capability Structure of the VF of Intel 82599 10GbE
46 * Controller looks trivial, e.g., the PCI Express Capabilities
47 * Register is 0, so the Capability Version is 0 and
48 * xen_pt_pcie_size_init() would fail.
50 if (d
->vendor_id
== PCI_VENDOR_ID_INTEL
&&
51 d
->device_id
== PCI_DEVICE_ID_INTEL_82599_SFP_VF
) {
59 /* find emulate register group entry */
60 XenPTRegGroup
*xen_pt_find_reg_grp(XenPCIPassthroughState
*s
, uint32_t address
)
62 XenPTRegGroup
*entry
= NULL
;
64 /* find register group entry */
65 QLIST_FOREACH(entry
, &s
->reg_grps
, entries
) {
67 if ((entry
->base_offset
<= address
)
68 && ((entry
->base_offset
+ entry
->size
) > address
)) {
73 /* group entry not found */
77 /* find emulate register entry */
78 XenPTReg
*xen_pt_find_reg(XenPTRegGroup
*reg_grp
, uint32_t address
)
80 XenPTReg
*reg_entry
= NULL
;
81 XenPTRegInfo
*reg
= NULL
;
82 uint32_t real_offset
= 0;
84 /* find register entry */
85 QLIST_FOREACH(reg_entry
, ®_grp
->reg_tbl_list
, entries
) {
87 real_offset
= reg_grp
->base_offset
+ reg
->offset
;
89 if ((real_offset
<= address
)
90 && ((real_offset
+ reg
->size
) > address
)) {
98 static uint32_t get_throughable_mask(const XenPCIPassthroughState
*s
,
99 const XenPTRegInfo
*reg
,
102 uint32_t throughable_mask
= ~(reg
->emu_mask
| reg
->ro_mask
);
104 return throughable_mask
& valid_mask
;
108 * general register functions
111 /* register initialization function */
113 static int xen_pt_common_reg_init(XenPCIPassthroughState
*s
,
114 XenPTRegInfo
*reg
, uint32_t real_offset
,
117 *data
= reg
->init_val
;
121 /* Read register functions */
123 static int xen_pt_byte_reg_read(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
124 uint8_t *value
, uint8_t valid_mask
)
126 XenPTRegInfo
*reg
= cfg_entry
->reg
;
127 uint8_t valid_emu_mask
= 0;
129 /* emulate byte register */
130 valid_emu_mask
= reg
->emu_mask
& valid_mask
;
131 *value
= XEN_PT_MERGE_VALUE(*value
, cfg_entry
->data
, ~valid_emu_mask
);
135 static int xen_pt_word_reg_read(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
136 uint16_t *value
, uint16_t valid_mask
)
138 XenPTRegInfo
*reg
= cfg_entry
->reg
;
139 uint16_t valid_emu_mask
= 0;
141 /* emulate word register */
142 valid_emu_mask
= reg
->emu_mask
& valid_mask
;
143 *value
= XEN_PT_MERGE_VALUE(*value
, cfg_entry
->data
, ~valid_emu_mask
);
147 static int xen_pt_long_reg_read(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
148 uint32_t *value
, uint32_t valid_mask
)
150 XenPTRegInfo
*reg
= cfg_entry
->reg
;
151 uint32_t valid_emu_mask
= 0;
153 /* emulate long register */
154 valid_emu_mask
= reg
->emu_mask
& valid_mask
;
155 *value
= XEN_PT_MERGE_VALUE(*value
, cfg_entry
->data
, ~valid_emu_mask
);
160 /* Write register functions */
162 static int xen_pt_byte_reg_write(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
163 uint8_t *val
, uint8_t dev_value
,
166 XenPTRegInfo
*reg
= cfg_entry
->reg
;
167 uint8_t writable_mask
= 0;
168 uint8_t throughable_mask
= get_throughable_mask(s
, reg
, valid_mask
);
170 /* modify emulate register */
171 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
172 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
174 /* create value for writing to I/O device register */
175 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
179 static int xen_pt_word_reg_write(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
180 uint16_t *val
, uint16_t dev_value
,
183 XenPTRegInfo
*reg
= cfg_entry
->reg
;
184 uint16_t writable_mask
= 0;
185 uint16_t throughable_mask
= get_throughable_mask(s
, reg
, valid_mask
);
187 /* modify emulate register */
188 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
189 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
191 /* create value for writing to I/O device register */
192 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
196 static int xen_pt_long_reg_write(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
197 uint32_t *val
, uint32_t dev_value
,
200 XenPTRegInfo
*reg
= cfg_entry
->reg
;
201 uint32_t writable_mask
= 0;
202 uint32_t throughable_mask
= get_throughable_mask(s
, reg
, valid_mask
);
204 /* modify emulate register */
205 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
206 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
208 /* create value for writing to I/O device register */
209 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
215 /* XenPTRegInfo declaration
216 * - only for emulated register (either a part or whole bit).
217 * - for passthrough register that need special behavior (like interacting with
218 * other component), set emu_mask to all 0 and specify r/w func properly.
219 * - do NOT use ALL F for init_val, otherwise the tbl will not be registered.
222 /********************
226 static int xen_pt_vendor_reg_init(XenPCIPassthroughState
*s
,
227 XenPTRegInfo
*reg
, uint32_t real_offset
,
230 *data
= s
->real_device
.vendor_id
;
233 static int xen_pt_device_reg_init(XenPCIPassthroughState
*s
,
234 XenPTRegInfo
*reg
, uint32_t real_offset
,
237 *data
= s
->real_device
.device_id
;
240 static int xen_pt_status_reg_init(XenPCIPassthroughState
*s
,
241 XenPTRegInfo
*reg
, uint32_t real_offset
,
244 XenPTRegGroup
*reg_grp_entry
= NULL
;
245 XenPTReg
*reg_entry
= NULL
;
246 uint32_t reg_field
= 0;
248 /* find Header register group */
249 reg_grp_entry
= xen_pt_find_reg_grp(s
, PCI_CAPABILITY_LIST
);
251 /* find Capabilities Pointer register */
252 reg_entry
= xen_pt_find_reg(reg_grp_entry
, PCI_CAPABILITY_LIST
);
254 /* check Capabilities Pointer register */
255 if (reg_entry
->data
) {
256 reg_field
|= PCI_STATUS_CAP_LIST
;
258 reg_field
&= ~PCI_STATUS_CAP_LIST
;
261 xen_shutdown_fatal_error("Internal error: Couldn't find XenPTReg*"
262 " for Capabilities Pointer register."
263 " (%s)\n", __func__
);
267 xen_shutdown_fatal_error("Internal error: Couldn't find XenPTRegGroup"
268 " for Header. (%s)\n", __func__
);
275 static int xen_pt_header_type_reg_init(XenPCIPassthroughState
*s
,
276 XenPTRegInfo
*reg
, uint32_t real_offset
,
279 /* read PCI_HEADER_TYPE */
280 *data
= reg
->init_val
| 0x80;
284 /* initialize Interrupt Pin register */
285 static int xen_pt_irqpin_reg_init(XenPCIPassthroughState
*s
,
286 XenPTRegInfo
*reg
, uint32_t real_offset
,
289 *data
= xen_pt_pci_read_intx(s
);
293 /* Command register */
294 static int xen_pt_cmd_reg_write(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
295 uint16_t *val
, uint16_t dev_value
,
298 XenPTRegInfo
*reg
= cfg_entry
->reg
;
299 uint16_t writable_mask
= 0;
300 uint16_t throughable_mask
= get_throughable_mask(s
, reg
, valid_mask
);
302 /* modify emulate register */
303 writable_mask
= ~reg
->ro_mask
& valid_mask
;
304 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
306 /* create value for writing to I/O device register */
307 if (*val
& PCI_COMMAND_INTX_DISABLE
) {
308 throughable_mask
|= PCI_COMMAND_INTX_DISABLE
;
310 if (s
->machine_irq
) {
311 throughable_mask
|= PCI_COMMAND_INTX_DISABLE
;
315 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
321 #define XEN_PT_BAR_MEM_RO_MASK 0x0000000F /* BAR ReadOnly mask(Memory) */
322 #define XEN_PT_BAR_MEM_EMU_MASK 0xFFFFFFF0 /* BAR emul mask(Memory) */
323 #define XEN_PT_BAR_IO_RO_MASK 0x00000003 /* BAR ReadOnly mask(I/O) */
324 #define XEN_PT_BAR_IO_EMU_MASK 0xFFFFFFFC /* BAR emul mask(I/O) */
326 static bool is_64bit_bar(PCIIORegion
*r
)
328 return !!(r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
);
331 static uint64_t xen_pt_get_bar_size(PCIIORegion
*r
)
333 if (is_64bit_bar(r
)) {
335 size64
= (r
+ 1)->size
;
343 static XenPTBarFlag
xen_pt_bar_reg_parse(XenPCIPassthroughState
*s
,
346 PCIDevice
*d
= &s
->dev
;
347 XenPTRegion
*region
= NULL
;
350 /* check 64bit BAR */
351 if ((0 < index
) && (index
< PCI_ROM_SLOT
)) {
352 int type
= s
->real_device
.io_regions
[index
- 1].type
;
354 if ((type
& XEN_HOST_PCI_REGION_TYPE_MEM
)
355 && (type
& XEN_HOST_PCI_REGION_TYPE_MEM_64
)) {
356 region
= &s
->bases
[index
- 1];
357 if (region
->bar_flag
!= XEN_PT_BAR_FLAG_UPPER
) {
358 return XEN_PT_BAR_FLAG_UPPER
;
363 /* check unused BAR */
364 r
= &d
->io_regions
[index
];
365 if (!xen_pt_get_bar_size(r
)) {
366 return XEN_PT_BAR_FLAG_UNUSED
;
370 if (index
== PCI_ROM_SLOT
) {
371 return XEN_PT_BAR_FLAG_MEM
;
374 /* check BAR I/O indicator */
375 if (s
->real_device
.io_regions
[index
].type
& XEN_HOST_PCI_REGION_TYPE_IO
) {
376 return XEN_PT_BAR_FLAG_IO
;
378 return XEN_PT_BAR_FLAG_MEM
;
382 static inline uint32_t base_address_with_flags(XenHostPCIIORegion
*hr
)
384 if (hr
->type
& XEN_HOST_PCI_REGION_TYPE_IO
) {
385 return hr
->base_addr
| (hr
->bus_flags
& ~PCI_BASE_ADDRESS_IO_MASK
);
387 return hr
->base_addr
| (hr
->bus_flags
& ~PCI_BASE_ADDRESS_MEM_MASK
);
391 static int xen_pt_bar_reg_init(XenPCIPassthroughState
*s
, XenPTRegInfo
*reg
,
392 uint32_t real_offset
, uint32_t *data
)
394 uint32_t reg_field
= 0;
397 index
= xen_pt_bar_offset_to_index(reg
->offset
);
398 if (index
< 0 || index
>= PCI_NUM_REGIONS
) {
399 XEN_PT_ERR(&s
->dev
, "Internal error: Invalid BAR index [%d].\n", index
);
404 s
->bases
[index
].bar_flag
= xen_pt_bar_reg_parse(s
, index
);
405 if (s
->bases
[index
].bar_flag
== XEN_PT_BAR_FLAG_UNUSED
) {
406 reg_field
= XEN_PT_INVALID_REG
;
412 static int xen_pt_bar_reg_read(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
413 uint32_t *value
, uint32_t valid_mask
)
415 XenPTRegInfo
*reg
= cfg_entry
->reg
;
416 uint32_t valid_emu_mask
= 0;
417 uint32_t bar_emu_mask
= 0;
421 index
= xen_pt_bar_offset_to_index(reg
->offset
);
422 if (index
< 0 || index
>= PCI_NUM_REGIONS
- 1) {
423 XEN_PT_ERR(&s
->dev
, "Internal error: Invalid BAR index [%d].\n", index
);
427 /* use fixed-up value from kernel sysfs */
428 *value
= base_address_with_flags(&s
->real_device
.io_regions
[index
]);
430 /* set emulate mask depend on BAR flag */
431 switch (s
->bases
[index
].bar_flag
) {
432 case XEN_PT_BAR_FLAG_MEM
:
433 bar_emu_mask
= XEN_PT_BAR_MEM_EMU_MASK
;
435 case XEN_PT_BAR_FLAG_IO
:
436 bar_emu_mask
= XEN_PT_BAR_IO_EMU_MASK
;
438 case XEN_PT_BAR_FLAG_UPPER
:
439 bar_emu_mask
= XEN_PT_BAR_ALLF
;
446 valid_emu_mask
= bar_emu_mask
& valid_mask
;
447 *value
= XEN_PT_MERGE_VALUE(*value
, cfg_entry
->data
, ~valid_emu_mask
);
451 static int xen_pt_bar_reg_write(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
452 uint32_t *val
, uint32_t dev_value
,
455 XenPTRegInfo
*reg
= cfg_entry
->reg
;
456 XenPTRegion
*base
= NULL
;
457 PCIDevice
*d
= &s
->dev
;
458 const PCIIORegion
*r
;
459 uint32_t writable_mask
= 0;
460 uint32_t bar_emu_mask
= 0;
461 uint32_t bar_ro_mask
= 0;
465 index
= xen_pt_bar_offset_to_index(reg
->offset
);
466 if (index
< 0 || index
>= PCI_NUM_REGIONS
) {
467 XEN_PT_ERR(d
, "Internal error: Invalid BAR index [%d].\n", index
);
471 r
= &d
->io_regions
[index
];
472 base
= &s
->bases
[index
];
473 r_size
= xen_pt_get_emul_size(base
->bar_flag
, r
->size
);
475 /* set emulate mask and read-only mask values depend on the BAR flag */
476 switch (s
->bases
[index
].bar_flag
) {
477 case XEN_PT_BAR_FLAG_MEM
:
478 bar_emu_mask
= XEN_PT_BAR_MEM_EMU_MASK
;
480 /* low 32 bits mask for 64 bit bars */
481 bar_ro_mask
= XEN_PT_BAR_ALLF
;
483 bar_ro_mask
= XEN_PT_BAR_MEM_RO_MASK
| (r_size
- 1);
486 case XEN_PT_BAR_FLAG_IO
:
487 bar_emu_mask
= XEN_PT_BAR_IO_EMU_MASK
;
488 bar_ro_mask
= XEN_PT_BAR_IO_RO_MASK
| (r_size
- 1);
490 case XEN_PT_BAR_FLAG_UPPER
:
491 bar_emu_mask
= XEN_PT_BAR_ALLF
;
492 bar_ro_mask
= r_size
? r_size
- 1 : 0;
498 /* modify emulate register */
499 writable_mask
= bar_emu_mask
& ~bar_ro_mask
& valid_mask
;
500 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
502 /* check whether we need to update the virtual region address or not */
503 switch (s
->bases
[index
].bar_flag
) {
504 case XEN_PT_BAR_FLAG_UPPER
:
505 case XEN_PT_BAR_FLAG_MEM
:
508 case XEN_PT_BAR_FLAG_IO
:
515 /* create value for writing to I/O device register */
516 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, 0);
521 /* write Exp ROM BAR */
522 static int xen_pt_exp_rom_bar_reg_write(XenPCIPassthroughState
*s
,
523 XenPTReg
*cfg_entry
, uint32_t *val
,
524 uint32_t dev_value
, uint32_t valid_mask
)
526 XenPTRegInfo
*reg
= cfg_entry
->reg
;
527 XenPTRegion
*base
= NULL
;
528 PCIDevice
*d
= (PCIDevice
*)&s
->dev
;
529 uint32_t writable_mask
= 0;
530 uint32_t throughable_mask
= get_throughable_mask(s
, reg
, valid_mask
);
532 uint32_t bar_ro_mask
= 0;
534 r_size
= d
->io_regions
[PCI_ROM_SLOT
].size
;
535 base
= &s
->bases
[PCI_ROM_SLOT
];
536 /* align memory type resource size */
537 r_size
= xen_pt_get_emul_size(base
->bar_flag
, r_size
);
539 /* set emulate mask and read-only mask */
540 bar_ro_mask
= (reg
->ro_mask
| (r_size
- 1)) & ~PCI_ROM_ADDRESS_ENABLE
;
542 /* modify emulate register */
543 writable_mask
= ~bar_ro_mask
& valid_mask
;
544 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
546 /* create value for writing to I/O device register */
547 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
552 /* Header Type0 reg static information table */
553 static XenPTRegInfo xen_pt_emu_reg_header0
[] = {
556 .offset
= PCI_VENDOR_ID
,
561 .init
= xen_pt_vendor_reg_init
,
562 .u
.w
.read
= xen_pt_word_reg_read
,
563 .u
.w
.write
= xen_pt_word_reg_write
,
567 .offset
= PCI_DEVICE_ID
,
572 .init
= xen_pt_device_reg_init
,
573 .u
.w
.read
= xen_pt_word_reg_read
,
574 .u
.w
.write
= xen_pt_word_reg_write
,
578 .offset
= PCI_COMMAND
,
583 .init
= xen_pt_common_reg_init
,
584 .u
.w
.read
= xen_pt_word_reg_read
,
585 .u
.w
.write
= xen_pt_cmd_reg_write
,
587 /* Capabilities Pointer reg */
589 .offset
= PCI_CAPABILITY_LIST
,
594 .init
= xen_pt_ptr_reg_init
,
595 .u
.b
.read
= xen_pt_byte_reg_read
,
596 .u
.b
.write
= xen_pt_byte_reg_write
,
599 /* use emulated Cap Ptr value to initialize,
600 * so need to be declared after Cap Ptr reg
603 .offset
= PCI_STATUS
,
609 .init
= xen_pt_status_reg_init
,
610 .u
.w
.read
= xen_pt_word_reg_read
,
611 .u
.w
.write
= xen_pt_word_reg_write
,
613 /* Cache Line Size reg */
615 .offset
= PCI_CACHE_LINE_SIZE
,
620 .init
= xen_pt_common_reg_init
,
621 .u
.b
.read
= xen_pt_byte_reg_read
,
622 .u
.b
.write
= xen_pt_byte_reg_write
,
624 /* Latency Timer reg */
626 .offset
= PCI_LATENCY_TIMER
,
631 .init
= xen_pt_common_reg_init
,
632 .u
.b
.read
= xen_pt_byte_reg_read
,
633 .u
.b
.write
= xen_pt_byte_reg_write
,
635 /* Header Type reg */
637 .offset
= PCI_HEADER_TYPE
,
642 .init
= xen_pt_header_type_reg_init
,
643 .u
.b
.read
= xen_pt_byte_reg_read
,
644 .u
.b
.write
= xen_pt_byte_reg_write
,
646 /* Interrupt Line reg */
648 .offset
= PCI_INTERRUPT_LINE
,
653 .init
= xen_pt_common_reg_init
,
654 .u
.b
.read
= xen_pt_byte_reg_read
,
655 .u
.b
.write
= xen_pt_byte_reg_write
,
657 /* Interrupt Pin reg */
659 .offset
= PCI_INTERRUPT_PIN
,
664 .init
= xen_pt_irqpin_reg_init
,
665 .u
.b
.read
= xen_pt_byte_reg_read
,
666 .u
.b
.write
= xen_pt_byte_reg_write
,
669 /* mask of BAR need to be decided later, depends on IO/MEM type */
671 .offset
= PCI_BASE_ADDRESS_0
,
673 .init_val
= 0x00000000,
674 .init
= xen_pt_bar_reg_init
,
675 .u
.dw
.read
= xen_pt_bar_reg_read
,
676 .u
.dw
.write
= xen_pt_bar_reg_write
,
680 .offset
= PCI_BASE_ADDRESS_1
,
682 .init_val
= 0x00000000,
683 .init
= xen_pt_bar_reg_init
,
684 .u
.dw
.read
= xen_pt_bar_reg_read
,
685 .u
.dw
.write
= xen_pt_bar_reg_write
,
689 .offset
= PCI_BASE_ADDRESS_2
,
691 .init_val
= 0x00000000,
692 .init
= xen_pt_bar_reg_init
,
693 .u
.dw
.read
= xen_pt_bar_reg_read
,
694 .u
.dw
.write
= xen_pt_bar_reg_write
,
698 .offset
= PCI_BASE_ADDRESS_3
,
700 .init_val
= 0x00000000,
701 .init
= xen_pt_bar_reg_init
,
702 .u
.dw
.read
= xen_pt_bar_reg_read
,
703 .u
.dw
.write
= xen_pt_bar_reg_write
,
707 .offset
= PCI_BASE_ADDRESS_4
,
709 .init_val
= 0x00000000,
710 .init
= xen_pt_bar_reg_init
,
711 .u
.dw
.read
= xen_pt_bar_reg_read
,
712 .u
.dw
.write
= xen_pt_bar_reg_write
,
716 .offset
= PCI_BASE_ADDRESS_5
,
718 .init_val
= 0x00000000,
719 .init
= xen_pt_bar_reg_init
,
720 .u
.dw
.read
= xen_pt_bar_reg_read
,
721 .u
.dw
.write
= xen_pt_bar_reg_write
,
723 /* Expansion ROM BAR reg */
725 .offset
= PCI_ROM_ADDRESS
,
727 .init_val
= 0x00000000,
728 .ro_mask
= 0x000007FE,
729 .emu_mask
= 0xFFFFF800,
730 .init
= xen_pt_bar_reg_init
,
731 .u
.dw
.read
= xen_pt_long_reg_read
,
732 .u
.dw
.write
= xen_pt_exp_rom_bar_reg_write
,
740 /*********************************
741 * Vital Product Data Capability
744 /* Vital Product Data Capability Structure reg static information table */
745 static XenPTRegInfo xen_pt_emu_reg_vpd
[] = {
747 .offset
= PCI_CAP_LIST_NEXT
,
752 .init
= xen_pt_ptr_reg_init
,
753 .u
.b
.read
= xen_pt_byte_reg_read
,
754 .u
.b
.write
= xen_pt_byte_reg_write
,
762 /**************************************
763 * Vendor Specific Capability
766 /* Vendor Specific Capability Structure reg static information table */
767 static XenPTRegInfo xen_pt_emu_reg_vendor
[] = {
769 .offset
= PCI_CAP_LIST_NEXT
,
774 .init
= xen_pt_ptr_reg_init
,
775 .u
.b
.read
= xen_pt_byte_reg_read
,
776 .u
.b
.write
= xen_pt_byte_reg_write
,
784 /*****************************
785 * PCI Express Capability
788 static inline uint8_t get_capability_version(XenPCIPassthroughState
*s
,
791 uint8_t flags
= pci_get_byte(s
->dev
.config
+ offset
+ PCI_EXP_FLAGS
);
792 return flags
& PCI_EXP_FLAGS_VERS
;
795 static inline uint8_t get_device_type(XenPCIPassthroughState
*s
,
798 uint8_t flags
= pci_get_byte(s
->dev
.config
+ offset
+ PCI_EXP_FLAGS
);
799 return (flags
& PCI_EXP_FLAGS_TYPE
) >> 4;
802 /* initialize Link Control register */
803 static int xen_pt_linkctrl_reg_init(XenPCIPassthroughState
*s
,
804 XenPTRegInfo
*reg
, uint32_t real_offset
,
807 uint8_t cap_ver
= get_capability_version(s
, real_offset
- reg
->offset
);
808 uint8_t dev_type
= get_device_type(s
, real_offset
- reg
->offset
);
810 /* no need to initialize in case of Root Complex Integrated Endpoint
813 if ((dev_type
== PCI_EXP_TYPE_RC_END
) && (cap_ver
== 1)) {
814 *data
= XEN_PT_INVALID_REG
;
817 *data
= reg
->init_val
;
820 /* initialize Device Control 2 register */
821 static int xen_pt_devctrl2_reg_init(XenPCIPassthroughState
*s
,
822 XenPTRegInfo
*reg
, uint32_t real_offset
,
825 uint8_t cap_ver
= get_capability_version(s
, real_offset
- reg
->offset
);
827 /* no need to initialize in case of cap_ver 1.x */
829 *data
= XEN_PT_INVALID_REG
;
832 *data
= reg
->init_val
;
835 /* initialize Link Control 2 register */
836 static int xen_pt_linkctrl2_reg_init(XenPCIPassthroughState
*s
,
837 XenPTRegInfo
*reg
, uint32_t real_offset
,
840 uint8_t cap_ver
= get_capability_version(s
, real_offset
- reg
->offset
);
841 uint32_t reg_field
= 0;
843 /* no need to initialize in case of cap_ver 1.x */
845 reg_field
= XEN_PT_INVALID_REG
;
847 /* set Supported Link Speed */
848 uint8_t lnkcap
= pci_get_byte(s
->dev
.config
+ real_offset
- reg
->offset
850 reg_field
|= PCI_EXP_LNKCAP_SLS
& lnkcap
;
857 /* PCI Express Capability Structure reg static information table */
858 static XenPTRegInfo xen_pt_emu_reg_pcie
[] = {
859 /* Next Pointer reg */
861 .offset
= PCI_CAP_LIST_NEXT
,
866 .init
= xen_pt_ptr_reg_init
,
867 .u
.b
.read
= xen_pt_byte_reg_read
,
868 .u
.b
.write
= xen_pt_byte_reg_write
,
870 /* Device Capabilities reg */
872 .offset
= PCI_EXP_DEVCAP
,
874 .init_val
= 0x00000000,
875 .ro_mask
= 0xFFFFFFFF,
876 .emu_mask
= 0x10000000,
877 .init
= xen_pt_common_reg_init
,
878 .u
.dw
.read
= xen_pt_long_reg_read
,
879 .u
.dw
.write
= xen_pt_long_reg_write
,
881 /* Device Control reg */
883 .offset
= PCI_EXP_DEVCTL
,
888 .init
= xen_pt_common_reg_init
,
889 .u
.w
.read
= xen_pt_word_reg_read
,
890 .u
.w
.write
= xen_pt_word_reg_write
,
892 /* Link Control reg */
894 .offset
= PCI_EXP_LNKCTL
,
899 .init
= xen_pt_linkctrl_reg_init
,
900 .u
.w
.read
= xen_pt_word_reg_read
,
901 .u
.w
.write
= xen_pt_word_reg_write
,
903 /* Device Control 2 reg */
910 .init
= xen_pt_devctrl2_reg_init
,
911 .u
.w
.read
= xen_pt_word_reg_read
,
912 .u
.w
.write
= xen_pt_word_reg_write
,
914 /* Link Control 2 reg */
921 .init
= xen_pt_linkctrl2_reg_init
,
922 .u
.w
.read
= xen_pt_word_reg_read
,
923 .u
.w
.write
= xen_pt_word_reg_write
,
931 /*********************************
932 * Power Management Capability
935 /* write Power Management Control/Status register */
936 static int xen_pt_pmcsr_reg_write(XenPCIPassthroughState
*s
,
937 XenPTReg
*cfg_entry
, uint16_t *val
,
938 uint16_t dev_value
, uint16_t valid_mask
)
940 XenPTRegInfo
*reg
= cfg_entry
->reg
;
941 uint16_t writable_mask
= 0;
942 uint16_t throughable_mask
= get_throughable_mask(s
, reg
, valid_mask
);
944 /* modify emulate register */
945 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
946 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
948 /* create value for writing to I/O device register */
949 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
& ~PCI_PM_CTRL_PME_STATUS
,
955 /* Power Management Capability reg static information table */
956 static XenPTRegInfo xen_pt_emu_reg_pm
[] = {
957 /* Next Pointer reg */
959 .offset
= PCI_CAP_LIST_NEXT
,
964 .init
= xen_pt_ptr_reg_init
,
965 .u
.b
.read
= xen_pt_byte_reg_read
,
966 .u
.b
.write
= xen_pt_byte_reg_write
,
968 /* Power Management Capabilities reg */
970 .offset
= PCI_CAP_FLAGS
,
975 .init
= xen_pt_common_reg_init
,
976 .u
.w
.read
= xen_pt_word_reg_read
,
977 .u
.w
.write
= xen_pt_word_reg_write
,
979 /* PCI Power Management Control/Status reg */
981 .offset
= PCI_PM_CTRL
,
987 .init
= xen_pt_common_reg_init
,
988 .u
.w
.read
= xen_pt_word_reg_read
,
989 .u
.w
.write
= xen_pt_pmcsr_reg_write
,
997 /********************************
1002 #define xen_pt_msi_check_type(offset, flags, what) \
1003 ((offset) == ((flags) & PCI_MSI_FLAGS_64BIT ? \
1004 PCI_MSI_##what##_64 : PCI_MSI_##what##_32))
1006 /* Message Control register */
1007 static int xen_pt_msgctrl_reg_init(XenPCIPassthroughState
*s
,
1008 XenPTRegInfo
*reg
, uint32_t real_offset
,
1011 PCIDevice
*d
= &s
->dev
;
1012 XenPTMSI
*msi
= s
->msi
;
1013 uint16_t reg_field
= 0;
1015 /* use I/O device register's value as initial value */
1016 reg_field
= pci_get_word(d
->config
+ real_offset
);
1018 if (reg_field
& PCI_MSI_FLAGS_ENABLE
) {
1019 XEN_PT_LOG(&s
->dev
, "MSI already enabled, disabling it first\n");
1020 xen_host_pci_set_word(&s
->real_device
, real_offset
,
1021 reg_field
& ~PCI_MSI_FLAGS_ENABLE
);
1023 msi
->flags
|= reg_field
;
1024 msi
->ctrl_offset
= real_offset
;
1025 msi
->initialized
= false;
1026 msi
->mapped
= false;
1028 *data
= reg
->init_val
;
1031 static int xen_pt_msgctrl_reg_write(XenPCIPassthroughState
*s
,
1032 XenPTReg
*cfg_entry
, uint16_t *val
,
1033 uint16_t dev_value
, uint16_t valid_mask
)
1035 XenPTRegInfo
*reg
= cfg_entry
->reg
;
1036 XenPTMSI
*msi
= s
->msi
;
1037 uint16_t writable_mask
= 0;
1038 uint16_t throughable_mask
= get_throughable_mask(s
, reg
, valid_mask
);
1040 /* Currently no support for multi-vector */
1041 if (*val
& PCI_MSI_FLAGS_QSIZE
) {
1042 XEN_PT_WARN(&s
->dev
, "Tries to set more than 1 vector ctrl %x\n", *val
);
1045 /* modify emulate register */
1046 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
1047 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
1048 msi
->flags
|= cfg_entry
->data
& ~PCI_MSI_FLAGS_ENABLE
;
1050 /* create value for writing to I/O device register */
1051 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
1054 if (*val
& PCI_MSI_FLAGS_ENABLE
) {
1055 /* setup MSI pirq for the first time */
1056 if (!msi
->initialized
) {
1057 /* Init physical one */
1058 XEN_PT_LOG(&s
->dev
, "setup MSI\n");
1059 if (xen_pt_msi_setup(s
)) {
1060 /* We do not broadcast the error to the framework code, so
1061 * that MSI errors are contained in MSI emulation code and
1062 * QEMU can go on running.
1063 * Guest MSI would be actually not working.
1065 *val
&= ~PCI_MSI_FLAGS_ENABLE
;
1066 XEN_PT_WARN(&s
->dev
, "Can not map MSI.\n");
1069 if (xen_pt_msi_update(s
)) {
1070 *val
&= ~PCI_MSI_FLAGS_ENABLE
;
1071 XEN_PT_WARN(&s
->dev
, "Can not bind MSI\n");
1074 msi
->initialized
= true;
1077 msi
->flags
|= PCI_MSI_FLAGS_ENABLE
;
1078 } else if (msi
->mapped
) {
1079 xen_pt_msi_disable(s
);
1085 /* initialize Message Upper Address register */
1086 static int xen_pt_msgaddr64_reg_init(XenPCIPassthroughState
*s
,
1087 XenPTRegInfo
*reg
, uint32_t real_offset
,
1090 /* no need to initialize in case of 32 bit type */
1091 if (!(s
->msi
->flags
& PCI_MSI_FLAGS_64BIT
)) {
1092 *data
= XEN_PT_INVALID_REG
;
1094 *data
= reg
->init_val
;
1099 /* this function will be called twice (for 32 bit and 64 bit type) */
1100 /* initialize Message Data register */
1101 static int xen_pt_msgdata_reg_init(XenPCIPassthroughState
*s
,
1102 XenPTRegInfo
*reg
, uint32_t real_offset
,
1105 uint32_t flags
= s
->msi
->flags
;
1106 uint32_t offset
= reg
->offset
;
1108 /* check the offset whether matches the type or not */
1109 if (xen_pt_msi_check_type(offset
, flags
, DATA
)) {
1110 *data
= reg
->init_val
;
1112 *data
= XEN_PT_INVALID_REG
;
1117 /* this function will be called twice (for 32 bit and 64 bit type) */
1118 /* initialize Mask register */
1119 static int xen_pt_mask_reg_init(XenPCIPassthroughState
*s
,
1120 XenPTRegInfo
*reg
, uint32_t real_offset
,
1123 uint32_t flags
= s
->msi
->flags
;
1125 /* check the offset whether matches the type or not */
1126 if (!(flags
& PCI_MSI_FLAGS_MASKBIT
)) {
1127 *data
= XEN_PT_INVALID_REG
;
1128 } else if (xen_pt_msi_check_type(reg
->offset
, flags
, MASK
)) {
1129 *data
= reg
->init_val
;
1131 *data
= XEN_PT_INVALID_REG
;
1136 /* this function will be called twice (for 32 bit and 64 bit type) */
1137 /* initialize Pending register */
1138 static int xen_pt_pending_reg_init(XenPCIPassthroughState
*s
,
1139 XenPTRegInfo
*reg
, uint32_t real_offset
,
1142 uint32_t flags
= s
->msi
->flags
;
1144 /* check the offset whether matches the type or not */
1145 if (!(flags
& PCI_MSI_FLAGS_MASKBIT
)) {
1146 *data
= XEN_PT_INVALID_REG
;
1147 } else if (xen_pt_msi_check_type(reg
->offset
, flags
, PENDING
)) {
1148 *data
= reg
->init_val
;
1150 *data
= XEN_PT_INVALID_REG
;
1155 /* write Message Address register */
1156 static int xen_pt_msgaddr32_reg_write(XenPCIPassthroughState
*s
,
1157 XenPTReg
*cfg_entry
, uint32_t *val
,
1158 uint32_t dev_value
, uint32_t valid_mask
)
1160 XenPTRegInfo
*reg
= cfg_entry
->reg
;
1161 uint32_t writable_mask
= 0;
1162 uint32_t old_addr
= cfg_entry
->data
;
1164 /* modify emulate register */
1165 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
1166 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
1167 s
->msi
->addr_lo
= cfg_entry
->data
;
1169 /* create value for writing to I/O device register */
1170 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, 0);
1173 if (cfg_entry
->data
!= old_addr
) {
1174 if (s
->msi
->mapped
) {
1175 xen_pt_msi_update(s
);
1181 /* write Message Upper Address register */
1182 static int xen_pt_msgaddr64_reg_write(XenPCIPassthroughState
*s
,
1183 XenPTReg
*cfg_entry
, uint32_t *val
,
1184 uint32_t dev_value
, uint32_t valid_mask
)
1186 XenPTRegInfo
*reg
= cfg_entry
->reg
;
1187 uint32_t writable_mask
= 0;
1188 uint32_t old_addr
= cfg_entry
->data
;
1190 /* check whether the type is 64 bit or not */
1191 if (!(s
->msi
->flags
& PCI_MSI_FLAGS_64BIT
)) {
1193 "Can't write to the upper address without 64 bit support\n");
1197 /* modify emulate register */
1198 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
1199 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
1200 /* update the msi_info too */
1201 s
->msi
->addr_hi
= cfg_entry
->data
;
1203 /* create value for writing to I/O device register */
1204 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, 0);
1207 if (cfg_entry
->data
!= old_addr
) {
1208 if (s
->msi
->mapped
) {
1209 xen_pt_msi_update(s
);
1217 /* this function will be called twice (for 32 bit and 64 bit type) */
1218 /* write Message Data register */
1219 static int xen_pt_msgdata_reg_write(XenPCIPassthroughState
*s
,
1220 XenPTReg
*cfg_entry
, uint16_t *val
,
1221 uint16_t dev_value
, uint16_t valid_mask
)
1223 XenPTRegInfo
*reg
= cfg_entry
->reg
;
1224 XenPTMSI
*msi
= s
->msi
;
1225 uint16_t writable_mask
= 0;
1226 uint16_t old_data
= cfg_entry
->data
;
1227 uint32_t offset
= reg
->offset
;
1229 /* check the offset whether matches the type or not */
1230 if (!xen_pt_msi_check_type(offset
, msi
->flags
, DATA
)) {
1231 /* exit I/O emulator */
1232 XEN_PT_ERR(&s
->dev
, "the offset does not match the 32/64 bit type!\n");
1236 /* modify emulate register */
1237 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
1238 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
1239 /* update the msi_info too */
1240 msi
->data
= cfg_entry
->data
;
1242 /* create value for writing to I/O device register */
1243 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, 0);
1246 if (cfg_entry
->data
!= old_data
) {
1248 xen_pt_msi_update(s
);
1255 /* MSI Capability Structure reg static information table */
1256 static XenPTRegInfo xen_pt_emu_reg_msi
[] = {
1257 /* Next Pointer reg */
1259 .offset
= PCI_CAP_LIST_NEXT
,
1264 .init
= xen_pt_ptr_reg_init
,
1265 .u
.b
.read
= xen_pt_byte_reg_read
,
1266 .u
.b
.write
= xen_pt_byte_reg_write
,
1268 /* Message Control reg */
1270 .offset
= PCI_MSI_FLAGS
,
1276 .init
= xen_pt_msgctrl_reg_init
,
1277 .u
.w
.read
= xen_pt_word_reg_read
,
1278 .u
.w
.write
= xen_pt_msgctrl_reg_write
,
1280 /* Message Address reg */
1282 .offset
= PCI_MSI_ADDRESS_LO
,
1284 .init_val
= 0x00000000,
1285 .ro_mask
= 0x00000003,
1286 .emu_mask
= 0xFFFFFFFF,
1287 .init
= xen_pt_common_reg_init
,
1288 .u
.dw
.read
= xen_pt_long_reg_read
,
1289 .u
.dw
.write
= xen_pt_msgaddr32_reg_write
,
1291 /* Message Upper Address reg (if PCI_MSI_FLAGS_64BIT set) */
1293 .offset
= PCI_MSI_ADDRESS_HI
,
1295 .init_val
= 0x00000000,
1296 .ro_mask
= 0x00000000,
1297 .emu_mask
= 0xFFFFFFFF,
1298 .init
= xen_pt_msgaddr64_reg_init
,
1299 .u
.dw
.read
= xen_pt_long_reg_read
,
1300 .u
.dw
.write
= xen_pt_msgaddr64_reg_write
,
1302 /* Message Data reg (16 bits of data for 32-bit devices) */
1304 .offset
= PCI_MSI_DATA_32
,
1309 .init
= xen_pt_msgdata_reg_init
,
1310 .u
.w
.read
= xen_pt_word_reg_read
,
1311 .u
.w
.write
= xen_pt_msgdata_reg_write
,
1313 /* Message Data reg (16 bits of data for 64-bit devices) */
1315 .offset
= PCI_MSI_DATA_64
,
1320 .init
= xen_pt_msgdata_reg_init
,
1321 .u
.w
.read
= xen_pt_word_reg_read
,
1322 .u
.w
.write
= xen_pt_msgdata_reg_write
,
1324 /* Mask reg (if PCI_MSI_FLAGS_MASKBIT set, for 32-bit devices) */
1326 .offset
= PCI_MSI_MASK_32
,
1328 .init_val
= 0x00000000,
1329 .ro_mask
= 0xFFFFFFFF,
1330 .emu_mask
= 0xFFFFFFFF,
1331 .init
= xen_pt_mask_reg_init
,
1332 .u
.dw
.read
= xen_pt_long_reg_read
,
1333 .u
.dw
.write
= xen_pt_long_reg_write
,
1335 /* Mask reg (if PCI_MSI_FLAGS_MASKBIT set, for 64-bit devices) */
1337 .offset
= PCI_MSI_MASK_64
,
1339 .init_val
= 0x00000000,
1340 .ro_mask
= 0xFFFFFFFF,
1341 .emu_mask
= 0xFFFFFFFF,
1342 .init
= xen_pt_mask_reg_init
,
1343 .u
.dw
.read
= xen_pt_long_reg_read
,
1344 .u
.dw
.write
= xen_pt_long_reg_write
,
1346 /* Pending reg (if PCI_MSI_FLAGS_MASKBIT set, for 32-bit devices) */
1348 .offset
= PCI_MSI_MASK_32
+ 4,
1350 .init_val
= 0x00000000,
1351 .ro_mask
= 0xFFFFFFFF,
1352 .emu_mask
= 0x00000000,
1353 .init
= xen_pt_pending_reg_init
,
1354 .u
.dw
.read
= xen_pt_long_reg_read
,
1355 .u
.dw
.write
= xen_pt_long_reg_write
,
1357 /* Pending reg (if PCI_MSI_FLAGS_MASKBIT set, for 64-bit devices) */
1359 .offset
= PCI_MSI_MASK_64
+ 4,
1361 .init_val
= 0x00000000,
1362 .ro_mask
= 0xFFFFFFFF,
1363 .emu_mask
= 0x00000000,
1364 .init
= xen_pt_pending_reg_init
,
1365 .u
.dw
.read
= xen_pt_long_reg_read
,
1366 .u
.dw
.write
= xen_pt_long_reg_write
,
1374 /**************************************
1378 /* Message Control register for MSI-X */
1379 static int xen_pt_msixctrl_reg_init(XenPCIPassthroughState
*s
,
1380 XenPTRegInfo
*reg
, uint32_t real_offset
,
1383 PCIDevice
*d
= &s
->dev
;
1384 uint16_t reg_field
= 0;
1386 /* use I/O device register's value as initial value */
1387 reg_field
= pci_get_word(d
->config
+ real_offset
);
1389 if (reg_field
& PCI_MSIX_FLAGS_ENABLE
) {
1390 XEN_PT_LOG(d
, "MSIX already enabled, disabling it first\n");
1391 xen_host_pci_set_word(&s
->real_device
, real_offset
,
1392 reg_field
& ~PCI_MSIX_FLAGS_ENABLE
);
1395 s
->msix
->ctrl_offset
= real_offset
;
1397 *data
= reg
->init_val
;
1400 static int xen_pt_msixctrl_reg_write(XenPCIPassthroughState
*s
,
1401 XenPTReg
*cfg_entry
, uint16_t *val
,
1402 uint16_t dev_value
, uint16_t valid_mask
)
1404 XenPTRegInfo
*reg
= cfg_entry
->reg
;
1405 uint16_t writable_mask
= 0;
1406 uint16_t throughable_mask
= get_throughable_mask(s
, reg
, valid_mask
);
1407 int debug_msix_enabled_old
;
1409 /* modify emulate register */
1410 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
1411 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
1413 /* create value for writing to I/O device register */
1414 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
1417 if ((*val
& PCI_MSIX_FLAGS_ENABLE
)
1418 && !(*val
& PCI_MSIX_FLAGS_MASKALL
)) {
1419 xen_pt_msix_update(s
);
1420 } else if (!(*val
& PCI_MSIX_FLAGS_ENABLE
) && s
->msix
->enabled
) {
1421 xen_pt_msix_disable(s
);
1424 debug_msix_enabled_old
= s
->msix
->enabled
;
1425 s
->msix
->enabled
= !!(*val
& PCI_MSIX_FLAGS_ENABLE
);
1426 if (s
->msix
->enabled
!= debug_msix_enabled_old
) {
1427 XEN_PT_LOG(&s
->dev
, "%s MSI-X\n",
1428 s
->msix
->enabled
? "enable" : "disable");
1434 /* MSI-X Capability Structure reg static information table */
1435 static XenPTRegInfo xen_pt_emu_reg_msix
[] = {
1436 /* Next Pointer reg */
1438 .offset
= PCI_CAP_LIST_NEXT
,
1443 .init
= xen_pt_ptr_reg_init
,
1444 .u
.b
.read
= xen_pt_byte_reg_read
,
1445 .u
.b
.write
= xen_pt_byte_reg_write
,
1447 /* Message Control reg */
1449 .offset
= PCI_MSI_FLAGS
,
1455 .init
= xen_pt_msixctrl_reg_init
,
1456 .u
.w
.read
= xen_pt_word_reg_read
,
1457 .u
.w
.write
= xen_pt_msixctrl_reg_write
,
1465 /****************************
1469 /* capability structure register group size functions */
1471 static int xen_pt_reg_grp_size_init(XenPCIPassthroughState
*s
,
1472 const XenPTRegGroupInfo
*grp_reg
,
1473 uint32_t base_offset
, uint8_t *size
)
1475 *size
= grp_reg
->grp_size
;
1478 /* get Vendor Specific Capability Structure register group size */
1479 static int xen_pt_vendor_size_init(XenPCIPassthroughState
*s
,
1480 const XenPTRegGroupInfo
*grp_reg
,
1481 uint32_t base_offset
, uint8_t *size
)
1483 *size
= pci_get_byte(s
->dev
.config
+ base_offset
+ 0x02);
1486 /* get PCI Express Capability Structure register group size */
1487 static int xen_pt_pcie_size_init(XenPCIPassthroughState
*s
,
1488 const XenPTRegGroupInfo
*grp_reg
,
1489 uint32_t base_offset
, uint8_t *size
)
1491 PCIDevice
*d
= &s
->dev
;
1492 uint8_t version
= get_capability_version(s
, base_offset
);
1493 uint8_t type
= get_device_type(s
, base_offset
);
1494 uint8_t pcie_size
= 0;
1497 /* calculate size depend on capability version and device/port type */
1498 /* in case of PCI Express Base Specification Rev 1.x */
1500 /* The PCI Express Capabilities, Device Capabilities, and Device
1501 * Status/Control registers are required for all PCI Express devices.
1502 * The Link Capabilities and Link Status/Control are required for all
1503 * Endpoints that are not Root Complex Integrated Endpoints. Endpoints
1504 * are not required to implement registers other than those listed
1505 * above and terminate the capability structure.
1508 case PCI_EXP_TYPE_ENDPOINT
:
1509 case PCI_EXP_TYPE_LEG_END
:
1512 case PCI_EXP_TYPE_RC_END
:
1516 /* only EndPoint passthrough is supported */
1517 case PCI_EXP_TYPE_ROOT_PORT
:
1518 case PCI_EXP_TYPE_UPSTREAM
:
1519 case PCI_EXP_TYPE_DOWNSTREAM
:
1520 case PCI_EXP_TYPE_PCI_BRIDGE
:
1521 case PCI_EXP_TYPE_PCIE_BRIDGE
:
1522 case PCI_EXP_TYPE_RC_EC
:
1524 XEN_PT_ERR(d
, "Unsupported device/port type %#x.\n", type
);
1528 /* in case of PCI Express Base Specification Rev 2.0 */
1529 else if (version
== 2) {
1531 case PCI_EXP_TYPE_ENDPOINT
:
1532 case PCI_EXP_TYPE_LEG_END
:
1533 case PCI_EXP_TYPE_RC_END
:
1534 /* For Functions that do not implement the registers,
1535 * these spaces must be hardwired to 0b.
1539 /* only EndPoint passthrough is supported */
1540 case PCI_EXP_TYPE_ROOT_PORT
:
1541 case PCI_EXP_TYPE_UPSTREAM
:
1542 case PCI_EXP_TYPE_DOWNSTREAM
:
1543 case PCI_EXP_TYPE_PCI_BRIDGE
:
1544 case PCI_EXP_TYPE_PCIE_BRIDGE
:
1545 case PCI_EXP_TYPE_RC_EC
:
1547 XEN_PT_ERR(d
, "Unsupported device/port type %#x.\n", type
);
1551 XEN_PT_ERR(d
, "Unsupported capability version %#x.\n", version
);
1558 /* get MSI Capability Structure register group size */
1559 static int xen_pt_msi_size_init(XenPCIPassthroughState
*s
,
1560 const XenPTRegGroupInfo
*grp_reg
,
1561 uint32_t base_offset
, uint8_t *size
)
1563 PCIDevice
*d
= &s
->dev
;
1564 uint16_t msg_ctrl
= 0;
1565 uint8_t msi_size
= 0xa;
1567 msg_ctrl
= pci_get_word(d
->config
+ (base_offset
+ PCI_MSI_FLAGS
));
1569 /* check if 64-bit address is capable of per-vector masking */
1570 if (msg_ctrl
& PCI_MSI_FLAGS_64BIT
) {
1573 if (msg_ctrl
& PCI_MSI_FLAGS_MASKBIT
) {
1577 s
->msi
= g_new0(XenPTMSI
, 1);
1578 s
->msi
->pirq
= XEN_PT_UNASSIGNED_PIRQ
;
1583 /* get MSI-X Capability Structure register group size */
1584 static int xen_pt_msix_size_init(XenPCIPassthroughState
*s
,
1585 const XenPTRegGroupInfo
*grp_reg
,
1586 uint32_t base_offset
, uint8_t *size
)
1590 rc
= xen_pt_msix_init(s
, base_offset
);
1593 XEN_PT_ERR(&s
->dev
, "Internal error: Invalid xen_pt_msix_init.\n");
1597 *size
= grp_reg
->grp_size
;
1602 static const XenPTRegGroupInfo xen_pt_emu_reg_grps
[] = {
1603 /* Header Type0 reg group */
1606 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1608 .size_init
= xen_pt_reg_grp_size_init
,
1609 .emu_regs
= xen_pt_emu_reg_header0
,
1611 /* PCI PowerManagement Capability reg group */
1613 .grp_id
= PCI_CAP_ID_PM
,
1614 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1615 .grp_size
= PCI_PM_SIZEOF
,
1616 .size_init
= xen_pt_reg_grp_size_init
,
1617 .emu_regs
= xen_pt_emu_reg_pm
,
1619 /* AGP Capability Structure reg group */
1621 .grp_id
= PCI_CAP_ID_AGP
,
1622 .grp_type
= XEN_PT_GRP_TYPE_HARDWIRED
,
1624 .size_init
= xen_pt_reg_grp_size_init
,
1626 /* Vital Product Data Capability Structure reg group */
1628 .grp_id
= PCI_CAP_ID_VPD
,
1629 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1631 .size_init
= xen_pt_reg_grp_size_init
,
1632 .emu_regs
= xen_pt_emu_reg_vpd
,
1634 /* Slot Identification reg group */
1636 .grp_id
= PCI_CAP_ID_SLOTID
,
1637 .grp_type
= XEN_PT_GRP_TYPE_HARDWIRED
,
1639 .size_init
= xen_pt_reg_grp_size_init
,
1641 /* MSI Capability Structure reg group */
1643 .grp_id
= PCI_CAP_ID_MSI
,
1644 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1646 .size_init
= xen_pt_msi_size_init
,
1647 .emu_regs
= xen_pt_emu_reg_msi
,
1649 /* PCI-X Capabilities List Item reg group */
1651 .grp_id
= PCI_CAP_ID_PCIX
,
1652 .grp_type
= XEN_PT_GRP_TYPE_HARDWIRED
,
1654 .size_init
= xen_pt_reg_grp_size_init
,
1656 /* Vendor Specific Capability Structure reg group */
1658 .grp_id
= PCI_CAP_ID_VNDR
,
1659 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1661 .size_init
= xen_pt_vendor_size_init
,
1662 .emu_regs
= xen_pt_emu_reg_vendor
,
1664 /* SHPC Capability List Item reg group */
1666 .grp_id
= PCI_CAP_ID_SHPC
,
1667 .grp_type
= XEN_PT_GRP_TYPE_HARDWIRED
,
1669 .size_init
= xen_pt_reg_grp_size_init
,
1671 /* Subsystem ID and Subsystem Vendor ID Capability List Item reg group */
1673 .grp_id
= PCI_CAP_ID_SSVID
,
1674 .grp_type
= XEN_PT_GRP_TYPE_HARDWIRED
,
1676 .size_init
= xen_pt_reg_grp_size_init
,
1678 /* AGP 8x Capability Structure reg group */
1680 .grp_id
= PCI_CAP_ID_AGP3
,
1681 .grp_type
= XEN_PT_GRP_TYPE_HARDWIRED
,
1683 .size_init
= xen_pt_reg_grp_size_init
,
1685 /* PCI Express Capability Structure reg group */
1687 .grp_id
= PCI_CAP_ID_EXP
,
1688 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1690 .size_init
= xen_pt_pcie_size_init
,
1691 .emu_regs
= xen_pt_emu_reg_pcie
,
1693 /* MSI-X Capability Structure reg group */
1695 .grp_id
= PCI_CAP_ID_MSIX
,
1696 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1698 .size_init
= xen_pt_msix_size_init
,
1699 .emu_regs
= xen_pt_emu_reg_msix
,
1706 /* initialize Capabilities Pointer or Next Pointer register */
1707 static int xen_pt_ptr_reg_init(XenPCIPassthroughState
*s
,
1708 XenPTRegInfo
*reg
, uint32_t real_offset
,
1712 uint8_t *config
= s
->dev
.config
;
1713 uint32_t reg_field
= pci_get_byte(config
+ real_offset
);
1716 /* find capability offset */
1718 for (i
= 0; xen_pt_emu_reg_grps
[i
].grp_size
!= 0; i
++) {
1719 if (xen_pt_hide_dev_cap(&s
->real_device
,
1720 xen_pt_emu_reg_grps
[i
].grp_id
)) {
1724 cap_id
= pci_get_byte(config
+ reg_field
+ PCI_CAP_LIST_ID
);
1725 if (xen_pt_emu_reg_grps
[i
].grp_id
== cap_id
) {
1726 if (xen_pt_emu_reg_grps
[i
].grp_type
== XEN_PT_GRP_TYPE_EMU
) {
1729 /* ignore the 0 hardwired capability, find next one */
1734 /* next capability */
1735 reg_field
= pci_get_byte(config
+ reg_field
+ PCI_CAP_LIST_NEXT
);
1748 static uint8_t find_cap_offset(XenPCIPassthroughState
*s
, uint8_t cap
)
1751 unsigned max_cap
= PCI_CAP_MAX
;
1752 uint8_t pos
= PCI_CAPABILITY_LIST
;
1755 if (xen_host_pci_get_byte(&s
->real_device
, PCI_STATUS
, &status
)) {
1758 if ((status
& PCI_STATUS_CAP_LIST
) == 0) {
1763 if (xen_host_pci_get_byte(&s
->real_device
, pos
, &pos
)) {
1766 if (pos
< PCI_CONFIG_HEADER_SIZE
) {
1771 if (xen_host_pci_get_byte(&s
->real_device
,
1772 pos
+ PCI_CAP_LIST_ID
, &id
)) {
1783 pos
+= PCI_CAP_LIST_NEXT
;
1788 static int xen_pt_config_reg_init(XenPCIPassthroughState
*s
,
1789 XenPTRegGroup
*reg_grp
, XenPTRegInfo
*reg
)
1791 XenPTReg
*reg_entry
;
1795 reg_entry
= g_new0(XenPTReg
, 1);
1796 reg_entry
->reg
= reg
;
1799 /* initialize emulate register */
1800 rc
= reg
->init(s
, reg_entry
->reg
,
1801 reg_grp
->base_offset
+ reg
->offset
, &data
);
1806 if (data
== XEN_PT_INVALID_REG
) {
1807 /* free unused BAR register entry */
1811 /* set register value */
1812 reg_entry
->data
= data
;
1814 /* list add register entry */
1815 QLIST_INSERT_HEAD(®_grp
->reg_tbl_list
, reg_entry
, entries
);
1820 int xen_pt_config_init(XenPCIPassthroughState
*s
)
1824 QLIST_INIT(&s
->reg_grps
);
1826 for (i
= 0; xen_pt_emu_reg_grps
[i
].grp_size
!= 0; i
++) {
1827 uint32_t reg_grp_offset
= 0;
1828 XenPTRegGroup
*reg_grp_entry
= NULL
;
1830 if (xen_pt_emu_reg_grps
[i
].grp_id
!= 0xFF) {
1831 if (xen_pt_hide_dev_cap(&s
->real_device
,
1832 xen_pt_emu_reg_grps
[i
].grp_id
)) {
1836 reg_grp_offset
= find_cap_offset(s
, xen_pt_emu_reg_grps
[i
].grp_id
);
1838 if (!reg_grp_offset
) {
1843 reg_grp_entry
= g_new0(XenPTRegGroup
, 1);
1844 QLIST_INIT(®_grp_entry
->reg_tbl_list
);
1845 QLIST_INSERT_HEAD(&s
->reg_grps
, reg_grp_entry
, entries
);
1847 reg_grp_entry
->base_offset
= reg_grp_offset
;
1848 reg_grp_entry
->reg_grp
= xen_pt_emu_reg_grps
+ i
;
1849 if (xen_pt_emu_reg_grps
[i
].size_init
) {
1850 /* get register group size */
1851 rc
= xen_pt_emu_reg_grps
[i
].size_init(s
, reg_grp_entry
->reg_grp
,
1853 ®_grp_entry
->size
);
1855 xen_pt_config_delete(s
);
1860 if (xen_pt_emu_reg_grps
[i
].grp_type
== XEN_PT_GRP_TYPE_EMU
) {
1861 if (xen_pt_emu_reg_grps
[i
].emu_regs
) {
1863 XenPTRegInfo
*regs
= xen_pt_emu_reg_grps
[i
].emu_regs
;
1864 /* initialize capability register */
1865 for (j
= 0; regs
->size
!= 0; j
++, regs
++) {
1866 /* initialize capability register */
1867 rc
= xen_pt_config_reg_init(s
, reg_grp_entry
, regs
);
1869 xen_pt_config_delete(s
);
1880 /* delete all emulate register */
1881 void xen_pt_config_delete(XenPCIPassthroughState
*s
)
1883 struct XenPTRegGroup
*reg_group
, *next_grp
;
1884 struct XenPTReg
*reg
, *next_reg
;
1886 /* free MSI/MSI-X info table */
1888 xen_pt_msix_delete(s
);
1894 /* free all register group entry */
1895 QLIST_FOREACH_SAFE(reg_group
, &s
->reg_grps
, entries
, next_grp
) {
1896 /* free all register entry */
1897 QLIST_FOREACH_SAFE(reg
, ®_group
->reg_tbl_list
, entries
, next_reg
) {
1898 QLIST_REMOVE(reg
, entries
);
1902 QLIST_REMOVE(reg_group
, entries
);