2 * Copyright (c) 2007, Neocleus Corporation.
3 * Copyright (c) 2007, Intel Corporation.
5 * This work is licensed under the terms of the GNU GPL, version 2. See
6 * the COPYING file in the top-level directory.
8 * Alex Novik <alex@neocleus.com>
9 * Allen Kay <allen.m.kay@intel.com>
10 * Guy Zana <guy@neocleus.com>
12 * This file implements direct PCI assignment to a HVM guest
15 #include "qemu/timer.h"
16 #include "hw/xen/xen_backend.h"
19 #define XEN_PT_MERGE_VALUE(value, data, val_mask) \
20 (((value) & (val_mask)) | ((data) & ~(val_mask)))
22 #define XEN_PT_INVALID_REG 0xFFFFFFFF /* invalid register value */
26 static int xen_pt_ptr_reg_init(XenPCIPassthroughState
*s
, XenPTRegInfo
*reg
,
27 uint32_t real_offset
, uint32_t *data
);
32 /* A return value of 1 means the capability should NOT be exposed to guest. */
33 static int xen_pt_hide_dev_cap(const XenHostPCIDevice
*d
, uint8_t grp_id
)
37 /* The PCI Express Capability Structure of the VF of Intel 82599 10GbE
38 * Controller looks trivial, e.g., the PCI Express Capabilities
39 * Register is 0. We should not try to expose it to guest.
41 * The datasheet is available at
42 * http://download.intel.com/design/network/datashts/82599_datasheet.pdf
44 * See 'Table 9.7. VF PCIe Configuration Space' of the datasheet, the
45 * PCI Express Capability Structure of the VF of Intel 82599 10GbE
46 * Controller looks trivial, e.g., the PCI Express Capabilities
47 * Register is 0, so the Capability Version is 0 and
48 * xen_pt_pcie_size_init() would fail.
50 if (d
->vendor_id
== PCI_VENDOR_ID_INTEL
&&
51 d
->device_id
== PCI_DEVICE_ID_INTEL_82599_SFP_VF
) {
59 /* find emulate register group entry */
60 XenPTRegGroup
*xen_pt_find_reg_grp(XenPCIPassthroughState
*s
, uint32_t address
)
62 XenPTRegGroup
*entry
= NULL
;
64 /* find register group entry */
65 QLIST_FOREACH(entry
, &s
->reg_grps
, entries
) {
67 if ((entry
->base_offset
<= address
)
68 && ((entry
->base_offset
+ entry
->size
) > address
)) {
73 /* group entry not found */
77 /* find emulate register entry */
78 XenPTReg
*xen_pt_find_reg(XenPTRegGroup
*reg_grp
, uint32_t address
)
80 XenPTReg
*reg_entry
= NULL
;
81 XenPTRegInfo
*reg
= NULL
;
82 uint32_t real_offset
= 0;
84 /* find register entry */
85 QLIST_FOREACH(reg_entry
, ®_grp
->reg_tbl_list
, entries
) {
87 real_offset
= reg_grp
->base_offset
+ reg
->offset
;
89 if ((real_offset
<= address
)
90 && ((real_offset
+ reg
->size
) > address
)) {
98 static uint32_t get_throughable_mask(const XenPCIPassthroughState
*s
,
99 const XenPTRegInfo
*reg
,
102 uint32_t throughable_mask
= ~(reg
->emu_mask
| reg
->ro_mask
);
104 if (!s
->permissive
) {
105 throughable_mask
&= ~reg
->res_mask
;
108 return throughable_mask
& valid_mask
;
112 * general register functions
115 /* register initialization function */
117 static int xen_pt_common_reg_init(XenPCIPassthroughState
*s
,
118 XenPTRegInfo
*reg
, uint32_t real_offset
,
121 *data
= reg
->init_val
;
125 /* Read register functions */
127 static int xen_pt_byte_reg_read(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
128 uint8_t *value
, uint8_t valid_mask
)
130 XenPTRegInfo
*reg
= cfg_entry
->reg
;
131 uint8_t valid_emu_mask
= 0;
133 /* emulate byte register */
134 valid_emu_mask
= reg
->emu_mask
& valid_mask
;
135 *value
= XEN_PT_MERGE_VALUE(*value
, cfg_entry
->data
, ~valid_emu_mask
);
139 static int xen_pt_word_reg_read(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
140 uint16_t *value
, uint16_t valid_mask
)
142 XenPTRegInfo
*reg
= cfg_entry
->reg
;
143 uint16_t valid_emu_mask
= 0;
145 /* emulate word register */
146 valid_emu_mask
= reg
->emu_mask
& valid_mask
;
147 *value
= XEN_PT_MERGE_VALUE(*value
, cfg_entry
->data
, ~valid_emu_mask
);
151 static int xen_pt_long_reg_read(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
152 uint32_t *value
, uint32_t valid_mask
)
154 XenPTRegInfo
*reg
= cfg_entry
->reg
;
155 uint32_t valid_emu_mask
= 0;
157 /* emulate long register */
158 valid_emu_mask
= reg
->emu_mask
& valid_mask
;
159 *value
= XEN_PT_MERGE_VALUE(*value
, cfg_entry
->data
, ~valid_emu_mask
);
164 /* Write register functions */
166 static int xen_pt_byte_reg_write(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
167 uint8_t *val
, uint8_t dev_value
,
170 XenPTRegInfo
*reg
= cfg_entry
->reg
;
171 uint8_t writable_mask
= 0;
172 uint8_t throughable_mask
= get_throughable_mask(s
, reg
, valid_mask
);
174 /* modify emulate register */
175 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
176 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
178 /* create value for writing to I/O device register */
179 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
183 static int xen_pt_word_reg_write(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
184 uint16_t *val
, uint16_t dev_value
,
187 XenPTRegInfo
*reg
= cfg_entry
->reg
;
188 uint16_t writable_mask
= 0;
189 uint16_t throughable_mask
= get_throughable_mask(s
, reg
, valid_mask
);
191 /* modify emulate register */
192 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
193 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
195 /* create value for writing to I/O device register */
196 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
200 static int xen_pt_long_reg_write(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
201 uint32_t *val
, uint32_t dev_value
,
204 XenPTRegInfo
*reg
= cfg_entry
->reg
;
205 uint32_t writable_mask
= 0;
206 uint32_t throughable_mask
= get_throughable_mask(s
, reg
, valid_mask
);
208 /* modify emulate register */
209 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
210 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
212 /* create value for writing to I/O device register */
213 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
219 /* XenPTRegInfo declaration
220 * - only for emulated register (either a part or whole bit).
221 * - for passthrough register that need special behavior (like interacting with
222 * other component), set emu_mask to all 0 and specify r/w func properly.
223 * - do NOT use ALL F for init_val, otherwise the tbl will not be registered.
226 /********************
230 static int xen_pt_vendor_reg_init(XenPCIPassthroughState
*s
,
231 XenPTRegInfo
*reg
, uint32_t real_offset
,
234 *data
= s
->real_device
.vendor_id
;
237 static int xen_pt_device_reg_init(XenPCIPassthroughState
*s
,
238 XenPTRegInfo
*reg
, uint32_t real_offset
,
241 *data
= s
->real_device
.device_id
;
244 static int xen_pt_status_reg_init(XenPCIPassthroughState
*s
,
245 XenPTRegInfo
*reg
, uint32_t real_offset
,
248 XenPTRegGroup
*reg_grp_entry
= NULL
;
249 XenPTReg
*reg_entry
= NULL
;
250 uint32_t reg_field
= 0;
252 /* find Header register group */
253 reg_grp_entry
= xen_pt_find_reg_grp(s
, PCI_CAPABILITY_LIST
);
255 /* find Capabilities Pointer register */
256 reg_entry
= xen_pt_find_reg(reg_grp_entry
, PCI_CAPABILITY_LIST
);
258 /* check Capabilities Pointer register */
259 if (reg_entry
->data
) {
260 reg_field
|= PCI_STATUS_CAP_LIST
;
262 reg_field
&= ~PCI_STATUS_CAP_LIST
;
265 xen_shutdown_fatal_error("Internal error: Couldn't find XenPTReg*"
266 " for Capabilities Pointer register."
267 " (%s)\n", __func__
);
271 xen_shutdown_fatal_error("Internal error: Couldn't find XenPTRegGroup"
272 " for Header. (%s)\n", __func__
);
279 static int xen_pt_header_type_reg_init(XenPCIPassthroughState
*s
,
280 XenPTRegInfo
*reg
, uint32_t real_offset
,
283 /* read PCI_HEADER_TYPE */
284 *data
= reg
->init_val
| 0x80;
288 /* initialize Interrupt Pin register */
289 static int xen_pt_irqpin_reg_init(XenPCIPassthroughState
*s
,
290 XenPTRegInfo
*reg
, uint32_t real_offset
,
293 *data
= xen_pt_pci_read_intx(s
);
297 /* Command register */
298 static int xen_pt_cmd_reg_write(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
299 uint16_t *val
, uint16_t dev_value
,
302 XenPTRegInfo
*reg
= cfg_entry
->reg
;
303 uint16_t writable_mask
= 0;
304 uint16_t throughable_mask
= get_throughable_mask(s
, reg
, valid_mask
);
306 /* modify emulate register */
307 writable_mask
= ~reg
->ro_mask
& valid_mask
;
308 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
310 /* create value for writing to I/O device register */
311 if (*val
& PCI_COMMAND_INTX_DISABLE
) {
312 throughable_mask
|= PCI_COMMAND_INTX_DISABLE
;
314 if (s
->machine_irq
) {
315 throughable_mask
|= PCI_COMMAND_INTX_DISABLE
;
319 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
325 #define XEN_PT_BAR_MEM_RO_MASK 0x0000000F /* BAR ReadOnly mask(Memory) */
326 #define XEN_PT_BAR_MEM_EMU_MASK 0xFFFFFFF0 /* BAR emul mask(Memory) */
327 #define XEN_PT_BAR_IO_RO_MASK 0x00000003 /* BAR ReadOnly mask(I/O) */
328 #define XEN_PT_BAR_IO_EMU_MASK 0xFFFFFFFC /* BAR emul mask(I/O) */
330 static bool is_64bit_bar(PCIIORegion
*r
)
332 return !!(r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
);
335 static uint64_t xen_pt_get_bar_size(PCIIORegion
*r
)
337 if (is_64bit_bar(r
)) {
339 size64
= (r
+ 1)->size
;
347 static XenPTBarFlag
xen_pt_bar_reg_parse(XenPCIPassthroughState
*s
,
350 PCIDevice
*d
= &s
->dev
;
351 XenPTRegion
*region
= NULL
;
354 /* check 64bit BAR */
355 if ((0 < index
) && (index
< PCI_ROM_SLOT
)) {
356 int type
= s
->real_device
.io_regions
[index
- 1].type
;
358 if ((type
& XEN_HOST_PCI_REGION_TYPE_MEM
)
359 && (type
& XEN_HOST_PCI_REGION_TYPE_MEM_64
)) {
360 region
= &s
->bases
[index
- 1];
361 if (region
->bar_flag
!= XEN_PT_BAR_FLAG_UPPER
) {
362 return XEN_PT_BAR_FLAG_UPPER
;
367 /* check unused BAR */
368 r
= &d
->io_regions
[index
];
369 if (!xen_pt_get_bar_size(r
)) {
370 return XEN_PT_BAR_FLAG_UNUSED
;
374 if (index
== PCI_ROM_SLOT
) {
375 return XEN_PT_BAR_FLAG_MEM
;
378 /* check BAR I/O indicator */
379 if (s
->real_device
.io_regions
[index
].type
& XEN_HOST_PCI_REGION_TYPE_IO
) {
380 return XEN_PT_BAR_FLAG_IO
;
382 return XEN_PT_BAR_FLAG_MEM
;
386 static inline uint32_t base_address_with_flags(XenHostPCIIORegion
*hr
)
388 if (hr
->type
& XEN_HOST_PCI_REGION_TYPE_IO
) {
389 return hr
->base_addr
| (hr
->bus_flags
& ~PCI_BASE_ADDRESS_IO_MASK
);
391 return hr
->base_addr
| (hr
->bus_flags
& ~PCI_BASE_ADDRESS_MEM_MASK
);
395 static int xen_pt_bar_reg_init(XenPCIPassthroughState
*s
, XenPTRegInfo
*reg
,
396 uint32_t real_offset
, uint32_t *data
)
398 uint32_t reg_field
= 0;
401 index
= xen_pt_bar_offset_to_index(reg
->offset
);
402 if (index
< 0 || index
>= PCI_NUM_REGIONS
) {
403 XEN_PT_ERR(&s
->dev
, "Internal error: Invalid BAR index [%d].\n", index
);
408 s
->bases
[index
].bar_flag
= xen_pt_bar_reg_parse(s
, index
);
409 if (s
->bases
[index
].bar_flag
== XEN_PT_BAR_FLAG_UNUSED
) {
410 reg_field
= XEN_PT_INVALID_REG
;
416 static int xen_pt_bar_reg_read(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
417 uint32_t *value
, uint32_t valid_mask
)
419 XenPTRegInfo
*reg
= cfg_entry
->reg
;
420 uint32_t valid_emu_mask
= 0;
421 uint32_t bar_emu_mask
= 0;
425 index
= xen_pt_bar_offset_to_index(reg
->offset
);
426 if (index
< 0 || index
>= PCI_NUM_REGIONS
- 1) {
427 XEN_PT_ERR(&s
->dev
, "Internal error: Invalid BAR index [%d].\n", index
);
431 /* use fixed-up value from kernel sysfs */
432 *value
= base_address_with_flags(&s
->real_device
.io_regions
[index
]);
434 /* set emulate mask depend on BAR flag */
435 switch (s
->bases
[index
].bar_flag
) {
436 case XEN_PT_BAR_FLAG_MEM
:
437 bar_emu_mask
= XEN_PT_BAR_MEM_EMU_MASK
;
439 case XEN_PT_BAR_FLAG_IO
:
440 bar_emu_mask
= XEN_PT_BAR_IO_EMU_MASK
;
442 case XEN_PT_BAR_FLAG_UPPER
:
443 bar_emu_mask
= XEN_PT_BAR_ALLF
;
450 valid_emu_mask
= bar_emu_mask
& valid_mask
;
451 *value
= XEN_PT_MERGE_VALUE(*value
, cfg_entry
->data
, ~valid_emu_mask
);
455 static int xen_pt_bar_reg_write(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
456 uint32_t *val
, uint32_t dev_value
,
459 XenPTRegInfo
*reg
= cfg_entry
->reg
;
460 XenPTRegion
*base
= NULL
;
461 PCIDevice
*d
= &s
->dev
;
462 const PCIIORegion
*r
;
463 uint32_t writable_mask
= 0;
464 uint32_t bar_emu_mask
= 0;
465 uint32_t bar_ro_mask
= 0;
469 index
= xen_pt_bar_offset_to_index(reg
->offset
);
470 if (index
< 0 || index
>= PCI_NUM_REGIONS
) {
471 XEN_PT_ERR(d
, "Internal error: Invalid BAR index [%d].\n", index
);
475 r
= &d
->io_regions
[index
];
476 base
= &s
->bases
[index
];
477 r_size
= xen_pt_get_emul_size(base
->bar_flag
, r
->size
);
479 /* set emulate mask and read-only mask values depend on the BAR flag */
480 switch (s
->bases
[index
].bar_flag
) {
481 case XEN_PT_BAR_FLAG_MEM
:
482 bar_emu_mask
= XEN_PT_BAR_MEM_EMU_MASK
;
484 /* low 32 bits mask for 64 bit bars */
485 bar_ro_mask
= XEN_PT_BAR_ALLF
;
487 bar_ro_mask
= XEN_PT_BAR_MEM_RO_MASK
| (r_size
- 1);
490 case XEN_PT_BAR_FLAG_IO
:
491 bar_emu_mask
= XEN_PT_BAR_IO_EMU_MASK
;
492 bar_ro_mask
= XEN_PT_BAR_IO_RO_MASK
| (r_size
- 1);
494 case XEN_PT_BAR_FLAG_UPPER
:
495 bar_emu_mask
= XEN_PT_BAR_ALLF
;
496 bar_ro_mask
= r_size
? r_size
- 1 : 0;
502 /* modify emulate register */
503 writable_mask
= bar_emu_mask
& ~bar_ro_mask
& valid_mask
;
504 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
506 /* check whether we need to update the virtual region address or not */
507 switch (s
->bases
[index
].bar_flag
) {
508 case XEN_PT_BAR_FLAG_UPPER
:
509 case XEN_PT_BAR_FLAG_MEM
:
512 case XEN_PT_BAR_FLAG_IO
:
519 /* create value for writing to I/O device register */
520 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, 0);
525 /* write Exp ROM BAR */
526 static int xen_pt_exp_rom_bar_reg_write(XenPCIPassthroughState
*s
,
527 XenPTReg
*cfg_entry
, uint32_t *val
,
528 uint32_t dev_value
, uint32_t valid_mask
)
530 XenPTRegInfo
*reg
= cfg_entry
->reg
;
531 XenPTRegion
*base
= NULL
;
532 PCIDevice
*d
= (PCIDevice
*)&s
->dev
;
533 uint32_t writable_mask
= 0;
534 uint32_t throughable_mask
= get_throughable_mask(s
, reg
, valid_mask
);
536 uint32_t bar_ro_mask
= 0;
538 r_size
= d
->io_regions
[PCI_ROM_SLOT
].size
;
539 base
= &s
->bases
[PCI_ROM_SLOT
];
540 /* align memory type resource size */
541 r_size
= xen_pt_get_emul_size(base
->bar_flag
, r_size
);
543 /* set emulate mask and read-only mask */
544 bar_ro_mask
= (reg
->ro_mask
| (r_size
- 1)) & ~PCI_ROM_ADDRESS_ENABLE
;
546 /* modify emulate register */
547 writable_mask
= ~bar_ro_mask
& valid_mask
;
548 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
550 /* create value for writing to I/O device register */
551 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
556 /* Header Type0 reg static information table */
557 static XenPTRegInfo xen_pt_emu_reg_header0
[] = {
560 .offset
= PCI_VENDOR_ID
,
565 .init
= xen_pt_vendor_reg_init
,
566 .u
.w
.read
= xen_pt_word_reg_read
,
567 .u
.w
.write
= xen_pt_word_reg_write
,
571 .offset
= PCI_DEVICE_ID
,
576 .init
= xen_pt_device_reg_init
,
577 .u
.w
.read
= xen_pt_word_reg_read
,
578 .u
.w
.write
= xen_pt_word_reg_write
,
582 .offset
= PCI_COMMAND
,
587 .init
= xen_pt_common_reg_init
,
588 .u
.w
.read
= xen_pt_word_reg_read
,
589 .u
.w
.write
= xen_pt_cmd_reg_write
,
591 /* Capabilities Pointer reg */
593 .offset
= PCI_CAPABILITY_LIST
,
598 .init
= xen_pt_ptr_reg_init
,
599 .u
.b
.read
= xen_pt_byte_reg_read
,
600 .u
.b
.write
= xen_pt_byte_reg_write
,
603 /* use emulated Cap Ptr value to initialize,
604 * so need to be declared after Cap Ptr reg
607 .offset
= PCI_STATUS
,
613 .init
= xen_pt_status_reg_init
,
614 .u
.w
.read
= xen_pt_word_reg_read
,
615 .u
.w
.write
= xen_pt_word_reg_write
,
617 /* Cache Line Size reg */
619 .offset
= PCI_CACHE_LINE_SIZE
,
624 .init
= xen_pt_common_reg_init
,
625 .u
.b
.read
= xen_pt_byte_reg_read
,
626 .u
.b
.write
= xen_pt_byte_reg_write
,
628 /* Latency Timer reg */
630 .offset
= PCI_LATENCY_TIMER
,
635 .init
= xen_pt_common_reg_init
,
636 .u
.b
.read
= xen_pt_byte_reg_read
,
637 .u
.b
.write
= xen_pt_byte_reg_write
,
639 /* Header Type reg */
641 .offset
= PCI_HEADER_TYPE
,
646 .init
= xen_pt_header_type_reg_init
,
647 .u
.b
.read
= xen_pt_byte_reg_read
,
648 .u
.b
.write
= xen_pt_byte_reg_write
,
650 /* Interrupt Line reg */
652 .offset
= PCI_INTERRUPT_LINE
,
657 .init
= xen_pt_common_reg_init
,
658 .u
.b
.read
= xen_pt_byte_reg_read
,
659 .u
.b
.write
= xen_pt_byte_reg_write
,
661 /* Interrupt Pin reg */
663 .offset
= PCI_INTERRUPT_PIN
,
668 .init
= xen_pt_irqpin_reg_init
,
669 .u
.b
.read
= xen_pt_byte_reg_read
,
670 .u
.b
.write
= xen_pt_byte_reg_write
,
673 /* mask of BAR need to be decided later, depends on IO/MEM type */
675 .offset
= PCI_BASE_ADDRESS_0
,
677 .init_val
= 0x00000000,
678 .init
= xen_pt_bar_reg_init
,
679 .u
.dw
.read
= xen_pt_bar_reg_read
,
680 .u
.dw
.write
= xen_pt_bar_reg_write
,
684 .offset
= PCI_BASE_ADDRESS_1
,
686 .init_val
= 0x00000000,
687 .init
= xen_pt_bar_reg_init
,
688 .u
.dw
.read
= xen_pt_bar_reg_read
,
689 .u
.dw
.write
= xen_pt_bar_reg_write
,
693 .offset
= PCI_BASE_ADDRESS_2
,
695 .init_val
= 0x00000000,
696 .init
= xen_pt_bar_reg_init
,
697 .u
.dw
.read
= xen_pt_bar_reg_read
,
698 .u
.dw
.write
= xen_pt_bar_reg_write
,
702 .offset
= PCI_BASE_ADDRESS_3
,
704 .init_val
= 0x00000000,
705 .init
= xen_pt_bar_reg_init
,
706 .u
.dw
.read
= xen_pt_bar_reg_read
,
707 .u
.dw
.write
= xen_pt_bar_reg_write
,
711 .offset
= PCI_BASE_ADDRESS_4
,
713 .init_val
= 0x00000000,
714 .init
= xen_pt_bar_reg_init
,
715 .u
.dw
.read
= xen_pt_bar_reg_read
,
716 .u
.dw
.write
= xen_pt_bar_reg_write
,
720 .offset
= PCI_BASE_ADDRESS_5
,
722 .init_val
= 0x00000000,
723 .init
= xen_pt_bar_reg_init
,
724 .u
.dw
.read
= xen_pt_bar_reg_read
,
725 .u
.dw
.write
= xen_pt_bar_reg_write
,
727 /* Expansion ROM BAR reg */
729 .offset
= PCI_ROM_ADDRESS
,
731 .init_val
= 0x00000000,
732 .ro_mask
= 0x000007FE,
733 .emu_mask
= 0xFFFFF800,
734 .init
= xen_pt_bar_reg_init
,
735 .u
.dw
.read
= xen_pt_long_reg_read
,
736 .u
.dw
.write
= xen_pt_exp_rom_bar_reg_write
,
744 /*********************************
745 * Vital Product Data Capability
748 /* Vital Product Data Capability Structure reg static information table */
749 static XenPTRegInfo xen_pt_emu_reg_vpd
[] = {
751 .offset
= PCI_CAP_LIST_NEXT
,
756 .init
= xen_pt_ptr_reg_init
,
757 .u
.b
.read
= xen_pt_byte_reg_read
,
758 .u
.b
.write
= xen_pt_byte_reg_write
,
761 .offset
= PCI_VPD_ADDR
,
765 .init
= xen_pt_common_reg_init
,
766 .u
.w
.read
= xen_pt_word_reg_read
,
767 .u
.w
.write
= xen_pt_word_reg_write
,
775 /**************************************
776 * Vendor Specific Capability
779 /* Vendor Specific Capability Structure reg static information table */
780 static XenPTRegInfo xen_pt_emu_reg_vendor
[] = {
782 .offset
= PCI_CAP_LIST_NEXT
,
787 .init
= xen_pt_ptr_reg_init
,
788 .u
.b
.read
= xen_pt_byte_reg_read
,
789 .u
.b
.write
= xen_pt_byte_reg_write
,
797 /*****************************
798 * PCI Express Capability
801 static inline uint8_t get_capability_version(XenPCIPassthroughState
*s
,
804 uint8_t flags
= pci_get_byte(s
->dev
.config
+ offset
+ PCI_EXP_FLAGS
);
805 return flags
& PCI_EXP_FLAGS_VERS
;
808 static inline uint8_t get_device_type(XenPCIPassthroughState
*s
,
811 uint8_t flags
= pci_get_byte(s
->dev
.config
+ offset
+ PCI_EXP_FLAGS
);
812 return (flags
& PCI_EXP_FLAGS_TYPE
) >> 4;
815 /* initialize Link Control register */
816 static int xen_pt_linkctrl_reg_init(XenPCIPassthroughState
*s
,
817 XenPTRegInfo
*reg
, uint32_t real_offset
,
820 uint8_t cap_ver
= get_capability_version(s
, real_offset
- reg
->offset
);
821 uint8_t dev_type
= get_device_type(s
, real_offset
- reg
->offset
);
823 /* no need to initialize in case of Root Complex Integrated Endpoint
826 if ((dev_type
== PCI_EXP_TYPE_RC_END
) && (cap_ver
== 1)) {
827 *data
= XEN_PT_INVALID_REG
;
830 *data
= reg
->init_val
;
833 /* initialize Device Control 2 register */
834 static int xen_pt_devctrl2_reg_init(XenPCIPassthroughState
*s
,
835 XenPTRegInfo
*reg
, uint32_t real_offset
,
838 uint8_t cap_ver
= get_capability_version(s
, real_offset
- reg
->offset
);
840 /* no need to initialize in case of cap_ver 1.x */
842 *data
= XEN_PT_INVALID_REG
;
845 *data
= reg
->init_val
;
848 /* initialize Link Control 2 register */
849 static int xen_pt_linkctrl2_reg_init(XenPCIPassthroughState
*s
,
850 XenPTRegInfo
*reg
, uint32_t real_offset
,
853 uint8_t cap_ver
= get_capability_version(s
, real_offset
- reg
->offset
);
854 uint32_t reg_field
= 0;
856 /* no need to initialize in case of cap_ver 1.x */
858 reg_field
= XEN_PT_INVALID_REG
;
860 /* set Supported Link Speed */
861 uint8_t lnkcap
= pci_get_byte(s
->dev
.config
+ real_offset
- reg
->offset
863 reg_field
|= PCI_EXP_LNKCAP_SLS
& lnkcap
;
870 /* PCI Express Capability Structure reg static information table */
871 static XenPTRegInfo xen_pt_emu_reg_pcie
[] = {
872 /* Next Pointer reg */
874 .offset
= PCI_CAP_LIST_NEXT
,
879 .init
= xen_pt_ptr_reg_init
,
880 .u
.b
.read
= xen_pt_byte_reg_read
,
881 .u
.b
.write
= xen_pt_byte_reg_write
,
883 /* Device Capabilities reg */
885 .offset
= PCI_EXP_DEVCAP
,
887 .init_val
= 0x00000000,
888 .ro_mask
= 0xFFFFFFFF,
889 .emu_mask
= 0x10000000,
890 .init
= xen_pt_common_reg_init
,
891 .u
.dw
.read
= xen_pt_long_reg_read
,
892 .u
.dw
.write
= xen_pt_long_reg_write
,
894 /* Device Control reg */
896 .offset
= PCI_EXP_DEVCTL
,
901 .init
= xen_pt_common_reg_init
,
902 .u
.w
.read
= xen_pt_word_reg_read
,
903 .u
.w
.write
= xen_pt_word_reg_write
,
905 /* Device Status reg */
907 .offset
= PCI_EXP_DEVSTA
,
911 .init
= xen_pt_common_reg_init
,
912 .u
.w
.read
= xen_pt_word_reg_read
,
913 .u
.w
.write
= xen_pt_word_reg_write
,
915 /* Link Control reg */
917 .offset
= PCI_EXP_LNKCTL
,
922 .init
= xen_pt_linkctrl_reg_init
,
923 .u
.w
.read
= xen_pt_word_reg_read
,
924 .u
.w
.write
= xen_pt_word_reg_write
,
926 /* Link Status reg */
928 .offset
= PCI_EXP_LNKSTA
,
931 .init
= xen_pt_common_reg_init
,
932 .u
.w
.read
= xen_pt_word_reg_read
,
933 .u
.w
.write
= xen_pt_word_reg_write
,
935 /* Device Control 2 reg */
942 .init
= xen_pt_devctrl2_reg_init
,
943 .u
.w
.read
= xen_pt_word_reg_read
,
944 .u
.w
.write
= xen_pt_word_reg_write
,
946 /* Link Control 2 reg */
953 .init
= xen_pt_linkctrl2_reg_init
,
954 .u
.w
.read
= xen_pt_word_reg_read
,
955 .u
.w
.write
= xen_pt_word_reg_write
,
963 /*********************************
964 * Power Management Capability
967 /* write Power Management Control/Status register */
968 static int xen_pt_pmcsr_reg_write(XenPCIPassthroughState
*s
,
969 XenPTReg
*cfg_entry
, uint16_t *val
,
970 uint16_t dev_value
, uint16_t valid_mask
)
972 XenPTRegInfo
*reg
= cfg_entry
->reg
;
973 uint16_t writable_mask
= 0;
974 uint16_t throughable_mask
= get_throughable_mask(s
, reg
, valid_mask
);
976 /* modify emulate register */
977 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
978 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
980 /* create value for writing to I/O device register */
981 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
& ~PCI_PM_CTRL_PME_STATUS
,
987 /* Power Management Capability reg static information table */
988 static XenPTRegInfo xen_pt_emu_reg_pm
[] = {
989 /* Next Pointer reg */
991 .offset
= PCI_CAP_LIST_NEXT
,
996 .init
= xen_pt_ptr_reg_init
,
997 .u
.b
.read
= xen_pt_byte_reg_read
,
998 .u
.b
.write
= xen_pt_byte_reg_write
,
1000 /* Power Management Capabilities reg */
1002 .offset
= PCI_CAP_FLAGS
,
1007 .init
= xen_pt_common_reg_init
,
1008 .u
.w
.read
= xen_pt_word_reg_read
,
1009 .u
.w
.write
= xen_pt_word_reg_write
,
1011 /* PCI Power Management Control/Status reg */
1013 .offset
= PCI_PM_CTRL
,
1019 .init
= xen_pt_common_reg_init
,
1020 .u
.w
.read
= xen_pt_word_reg_read
,
1021 .u
.w
.write
= xen_pt_pmcsr_reg_write
,
1029 /********************************
1034 #define xen_pt_msi_check_type(offset, flags, what) \
1035 ((offset) == ((flags) & PCI_MSI_FLAGS_64BIT ? \
1036 PCI_MSI_##what##_64 : PCI_MSI_##what##_32))
1038 /* Message Control register */
1039 static int xen_pt_msgctrl_reg_init(XenPCIPassthroughState
*s
,
1040 XenPTRegInfo
*reg
, uint32_t real_offset
,
1043 PCIDevice
*d
= &s
->dev
;
1044 XenPTMSI
*msi
= s
->msi
;
1045 uint16_t reg_field
= 0;
1047 /* use I/O device register's value as initial value */
1048 reg_field
= pci_get_word(d
->config
+ real_offset
);
1050 if (reg_field
& PCI_MSI_FLAGS_ENABLE
) {
1051 XEN_PT_LOG(&s
->dev
, "MSI already enabled, disabling it first\n");
1052 xen_host_pci_set_word(&s
->real_device
, real_offset
,
1053 reg_field
& ~PCI_MSI_FLAGS_ENABLE
);
1055 msi
->flags
|= reg_field
;
1056 msi
->ctrl_offset
= real_offset
;
1057 msi
->initialized
= false;
1058 msi
->mapped
= false;
1060 *data
= reg
->init_val
;
1063 static int xen_pt_msgctrl_reg_write(XenPCIPassthroughState
*s
,
1064 XenPTReg
*cfg_entry
, uint16_t *val
,
1065 uint16_t dev_value
, uint16_t valid_mask
)
1067 XenPTRegInfo
*reg
= cfg_entry
->reg
;
1068 XenPTMSI
*msi
= s
->msi
;
1069 uint16_t writable_mask
= 0;
1070 uint16_t throughable_mask
= get_throughable_mask(s
, reg
, valid_mask
);
1072 /* Currently no support for multi-vector */
1073 if (*val
& PCI_MSI_FLAGS_QSIZE
) {
1074 XEN_PT_WARN(&s
->dev
, "Tries to set more than 1 vector ctrl %x\n", *val
);
1077 /* modify emulate register */
1078 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
1079 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
1080 msi
->flags
|= cfg_entry
->data
& ~PCI_MSI_FLAGS_ENABLE
;
1082 /* create value for writing to I/O device register */
1083 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
1086 if (*val
& PCI_MSI_FLAGS_ENABLE
) {
1087 /* setup MSI pirq for the first time */
1088 if (!msi
->initialized
) {
1089 /* Init physical one */
1090 XEN_PT_LOG(&s
->dev
, "setup MSI\n");
1091 if (xen_pt_msi_setup(s
)) {
1092 /* We do not broadcast the error to the framework code, so
1093 * that MSI errors are contained in MSI emulation code and
1094 * QEMU can go on running.
1095 * Guest MSI would be actually not working.
1097 *val
&= ~PCI_MSI_FLAGS_ENABLE
;
1098 XEN_PT_WARN(&s
->dev
, "Can not map MSI.\n");
1101 if (xen_pt_msi_update(s
)) {
1102 *val
&= ~PCI_MSI_FLAGS_ENABLE
;
1103 XEN_PT_WARN(&s
->dev
, "Can not bind MSI\n");
1106 msi
->initialized
= true;
1109 msi
->flags
|= PCI_MSI_FLAGS_ENABLE
;
1110 } else if (msi
->mapped
) {
1111 xen_pt_msi_disable(s
);
1117 /* initialize Message Upper Address register */
1118 static int xen_pt_msgaddr64_reg_init(XenPCIPassthroughState
*s
,
1119 XenPTRegInfo
*reg
, uint32_t real_offset
,
1122 /* no need to initialize in case of 32 bit type */
1123 if (!(s
->msi
->flags
& PCI_MSI_FLAGS_64BIT
)) {
1124 *data
= XEN_PT_INVALID_REG
;
1126 *data
= reg
->init_val
;
1131 /* this function will be called twice (for 32 bit and 64 bit type) */
1132 /* initialize Message Data register */
1133 static int xen_pt_msgdata_reg_init(XenPCIPassthroughState
*s
,
1134 XenPTRegInfo
*reg
, uint32_t real_offset
,
1137 uint32_t flags
= s
->msi
->flags
;
1138 uint32_t offset
= reg
->offset
;
1140 /* check the offset whether matches the type or not */
1141 if (xen_pt_msi_check_type(offset
, flags
, DATA
)) {
1142 *data
= reg
->init_val
;
1144 *data
= XEN_PT_INVALID_REG
;
1149 /* this function will be called twice (for 32 bit and 64 bit type) */
1150 /* initialize Mask register */
1151 static int xen_pt_mask_reg_init(XenPCIPassthroughState
*s
,
1152 XenPTRegInfo
*reg
, uint32_t real_offset
,
1155 uint32_t flags
= s
->msi
->flags
;
1157 /* check the offset whether matches the type or not */
1158 if (!(flags
& PCI_MSI_FLAGS_MASKBIT
)) {
1159 *data
= XEN_PT_INVALID_REG
;
1160 } else if (xen_pt_msi_check_type(reg
->offset
, flags
, MASK
)) {
1161 *data
= reg
->init_val
;
1163 *data
= XEN_PT_INVALID_REG
;
1168 /* this function will be called twice (for 32 bit and 64 bit type) */
1169 /* initialize Pending register */
1170 static int xen_pt_pending_reg_init(XenPCIPassthroughState
*s
,
1171 XenPTRegInfo
*reg
, uint32_t real_offset
,
1174 uint32_t flags
= s
->msi
->flags
;
1176 /* check the offset whether matches the type or not */
1177 if (!(flags
& PCI_MSI_FLAGS_MASKBIT
)) {
1178 *data
= XEN_PT_INVALID_REG
;
1179 } else if (xen_pt_msi_check_type(reg
->offset
, flags
, PENDING
)) {
1180 *data
= reg
->init_val
;
1182 *data
= XEN_PT_INVALID_REG
;
1187 /* write Message Address register */
1188 static int xen_pt_msgaddr32_reg_write(XenPCIPassthroughState
*s
,
1189 XenPTReg
*cfg_entry
, uint32_t *val
,
1190 uint32_t dev_value
, uint32_t valid_mask
)
1192 XenPTRegInfo
*reg
= cfg_entry
->reg
;
1193 uint32_t writable_mask
= 0;
1194 uint32_t old_addr
= cfg_entry
->data
;
1196 /* modify emulate register */
1197 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
1198 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
1199 s
->msi
->addr_lo
= cfg_entry
->data
;
1201 /* create value for writing to I/O device register */
1202 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, 0);
1205 if (cfg_entry
->data
!= old_addr
) {
1206 if (s
->msi
->mapped
) {
1207 xen_pt_msi_update(s
);
1213 /* write Message Upper Address register */
1214 static int xen_pt_msgaddr64_reg_write(XenPCIPassthroughState
*s
,
1215 XenPTReg
*cfg_entry
, uint32_t *val
,
1216 uint32_t dev_value
, uint32_t valid_mask
)
1218 XenPTRegInfo
*reg
= cfg_entry
->reg
;
1219 uint32_t writable_mask
= 0;
1220 uint32_t old_addr
= cfg_entry
->data
;
1222 /* check whether the type is 64 bit or not */
1223 if (!(s
->msi
->flags
& PCI_MSI_FLAGS_64BIT
)) {
1225 "Can't write to the upper address without 64 bit support\n");
1229 /* modify emulate register */
1230 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
1231 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
1232 /* update the msi_info too */
1233 s
->msi
->addr_hi
= cfg_entry
->data
;
1235 /* create value for writing to I/O device register */
1236 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, 0);
1239 if (cfg_entry
->data
!= old_addr
) {
1240 if (s
->msi
->mapped
) {
1241 xen_pt_msi_update(s
);
1249 /* this function will be called twice (for 32 bit and 64 bit type) */
1250 /* write Message Data register */
1251 static int xen_pt_msgdata_reg_write(XenPCIPassthroughState
*s
,
1252 XenPTReg
*cfg_entry
, uint16_t *val
,
1253 uint16_t dev_value
, uint16_t valid_mask
)
1255 XenPTRegInfo
*reg
= cfg_entry
->reg
;
1256 XenPTMSI
*msi
= s
->msi
;
1257 uint16_t writable_mask
= 0;
1258 uint16_t old_data
= cfg_entry
->data
;
1259 uint32_t offset
= reg
->offset
;
1261 /* check the offset whether matches the type or not */
1262 if (!xen_pt_msi_check_type(offset
, msi
->flags
, DATA
)) {
1263 /* exit I/O emulator */
1264 XEN_PT_ERR(&s
->dev
, "the offset does not match the 32/64 bit type!\n");
1268 /* modify emulate register */
1269 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
1270 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
1271 /* update the msi_info too */
1272 msi
->data
= cfg_entry
->data
;
1274 /* create value for writing to I/O device register */
1275 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, 0);
1278 if (cfg_entry
->data
!= old_data
) {
1280 xen_pt_msi_update(s
);
1287 /* MSI Capability Structure reg static information table */
1288 static XenPTRegInfo xen_pt_emu_reg_msi
[] = {
1289 /* Next Pointer reg */
1291 .offset
= PCI_CAP_LIST_NEXT
,
1296 .init
= xen_pt_ptr_reg_init
,
1297 .u
.b
.read
= xen_pt_byte_reg_read
,
1298 .u
.b
.write
= xen_pt_byte_reg_write
,
1300 /* Message Control reg */
1302 .offset
= PCI_MSI_FLAGS
,
1308 .init
= xen_pt_msgctrl_reg_init
,
1309 .u
.w
.read
= xen_pt_word_reg_read
,
1310 .u
.w
.write
= xen_pt_msgctrl_reg_write
,
1312 /* Message Address reg */
1314 .offset
= PCI_MSI_ADDRESS_LO
,
1316 .init_val
= 0x00000000,
1317 .ro_mask
= 0x00000003,
1318 .emu_mask
= 0xFFFFFFFF,
1319 .init
= xen_pt_common_reg_init
,
1320 .u
.dw
.read
= xen_pt_long_reg_read
,
1321 .u
.dw
.write
= xen_pt_msgaddr32_reg_write
,
1323 /* Message Upper Address reg (if PCI_MSI_FLAGS_64BIT set) */
1325 .offset
= PCI_MSI_ADDRESS_HI
,
1327 .init_val
= 0x00000000,
1328 .ro_mask
= 0x00000000,
1329 .emu_mask
= 0xFFFFFFFF,
1330 .init
= xen_pt_msgaddr64_reg_init
,
1331 .u
.dw
.read
= xen_pt_long_reg_read
,
1332 .u
.dw
.write
= xen_pt_msgaddr64_reg_write
,
1334 /* Message Data reg (16 bits of data for 32-bit devices) */
1336 .offset
= PCI_MSI_DATA_32
,
1341 .init
= xen_pt_msgdata_reg_init
,
1342 .u
.w
.read
= xen_pt_word_reg_read
,
1343 .u
.w
.write
= xen_pt_msgdata_reg_write
,
1345 /* Message Data reg (16 bits of data for 64-bit devices) */
1347 .offset
= PCI_MSI_DATA_64
,
1352 .init
= xen_pt_msgdata_reg_init
,
1353 .u
.w
.read
= xen_pt_word_reg_read
,
1354 .u
.w
.write
= xen_pt_msgdata_reg_write
,
1356 /* Mask reg (if PCI_MSI_FLAGS_MASKBIT set, for 32-bit devices) */
1358 .offset
= PCI_MSI_MASK_32
,
1360 .init_val
= 0x00000000,
1361 .ro_mask
= 0xFFFFFFFF,
1362 .emu_mask
= 0xFFFFFFFF,
1363 .init
= xen_pt_mask_reg_init
,
1364 .u
.dw
.read
= xen_pt_long_reg_read
,
1365 .u
.dw
.write
= xen_pt_long_reg_write
,
1367 /* Mask reg (if PCI_MSI_FLAGS_MASKBIT set, for 64-bit devices) */
1369 .offset
= PCI_MSI_MASK_64
,
1371 .init_val
= 0x00000000,
1372 .ro_mask
= 0xFFFFFFFF,
1373 .emu_mask
= 0xFFFFFFFF,
1374 .init
= xen_pt_mask_reg_init
,
1375 .u
.dw
.read
= xen_pt_long_reg_read
,
1376 .u
.dw
.write
= xen_pt_long_reg_write
,
1378 /* Pending reg (if PCI_MSI_FLAGS_MASKBIT set, for 32-bit devices) */
1380 .offset
= PCI_MSI_MASK_32
+ 4,
1382 .init_val
= 0x00000000,
1383 .ro_mask
= 0xFFFFFFFF,
1384 .emu_mask
= 0x00000000,
1385 .init
= xen_pt_pending_reg_init
,
1386 .u
.dw
.read
= xen_pt_long_reg_read
,
1387 .u
.dw
.write
= xen_pt_long_reg_write
,
1389 /* Pending reg (if PCI_MSI_FLAGS_MASKBIT set, for 64-bit devices) */
1391 .offset
= PCI_MSI_MASK_64
+ 4,
1393 .init_val
= 0x00000000,
1394 .ro_mask
= 0xFFFFFFFF,
1395 .emu_mask
= 0x00000000,
1396 .init
= xen_pt_pending_reg_init
,
1397 .u
.dw
.read
= xen_pt_long_reg_read
,
1398 .u
.dw
.write
= xen_pt_long_reg_write
,
1406 /**************************************
1410 /* Message Control register for MSI-X */
1411 static int xen_pt_msixctrl_reg_init(XenPCIPassthroughState
*s
,
1412 XenPTRegInfo
*reg
, uint32_t real_offset
,
1415 PCIDevice
*d
= &s
->dev
;
1416 uint16_t reg_field
= 0;
1418 /* use I/O device register's value as initial value */
1419 reg_field
= pci_get_word(d
->config
+ real_offset
);
1421 if (reg_field
& PCI_MSIX_FLAGS_ENABLE
) {
1422 XEN_PT_LOG(d
, "MSIX already enabled, disabling it first\n");
1423 xen_host_pci_set_word(&s
->real_device
, real_offset
,
1424 reg_field
& ~PCI_MSIX_FLAGS_ENABLE
);
1427 s
->msix
->ctrl_offset
= real_offset
;
1429 *data
= reg
->init_val
;
1432 static int xen_pt_msixctrl_reg_write(XenPCIPassthroughState
*s
,
1433 XenPTReg
*cfg_entry
, uint16_t *val
,
1434 uint16_t dev_value
, uint16_t valid_mask
)
1436 XenPTRegInfo
*reg
= cfg_entry
->reg
;
1437 uint16_t writable_mask
= 0;
1438 uint16_t throughable_mask
= get_throughable_mask(s
, reg
, valid_mask
);
1439 int debug_msix_enabled_old
;
1441 /* modify emulate register */
1442 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
1443 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
1445 /* create value for writing to I/O device register */
1446 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
1449 if ((*val
& PCI_MSIX_FLAGS_ENABLE
)
1450 && !(*val
& PCI_MSIX_FLAGS_MASKALL
)) {
1451 xen_pt_msix_update(s
);
1452 } else if (!(*val
& PCI_MSIX_FLAGS_ENABLE
) && s
->msix
->enabled
) {
1453 xen_pt_msix_disable(s
);
1456 debug_msix_enabled_old
= s
->msix
->enabled
;
1457 s
->msix
->enabled
= !!(*val
& PCI_MSIX_FLAGS_ENABLE
);
1458 if (s
->msix
->enabled
!= debug_msix_enabled_old
) {
1459 XEN_PT_LOG(&s
->dev
, "%s MSI-X\n",
1460 s
->msix
->enabled
? "enable" : "disable");
1466 /* MSI-X Capability Structure reg static information table */
1467 static XenPTRegInfo xen_pt_emu_reg_msix
[] = {
1468 /* Next Pointer reg */
1470 .offset
= PCI_CAP_LIST_NEXT
,
1475 .init
= xen_pt_ptr_reg_init
,
1476 .u
.b
.read
= xen_pt_byte_reg_read
,
1477 .u
.b
.write
= xen_pt_byte_reg_write
,
1479 /* Message Control reg */
1481 .offset
= PCI_MSI_FLAGS
,
1487 .init
= xen_pt_msixctrl_reg_init
,
1488 .u
.w
.read
= xen_pt_word_reg_read
,
1489 .u
.w
.write
= xen_pt_msixctrl_reg_write
,
1497 /****************************
1501 /* capability structure register group size functions */
1503 static int xen_pt_reg_grp_size_init(XenPCIPassthroughState
*s
,
1504 const XenPTRegGroupInfo
*grp_reg
,
1505 uint32_t base_offset
, uint8_t *size
)
1507 *size
= grp_reg
->grp_size
;
1510 /* get Vendor Specific Capability Structure register group size */
1511 static int xen_pt_vendor_size_init(XenPCIPassthroughState
*s
,
1512 const XenPTRegGroupInfo
*grp_reg
,
1513 uint32_t base_offset
, uint8_t *size
)
1515 *size
= pci_get_byte(s
->dev
.config
+ base_offset
+ 0x02);
1518 /* get PCI Express Capability Structure register group size */
1519 static int xen_pt_pcie_size_init(XenPCIPassthroughState
*s
,
1520 const XenPTRegGroupInfo
*grp_reg
,
1521 uint32_t base_offset
, uint8_t *size
)
1523 PCIDevice
*d
= &s
->dev
;
1524 uint8_t version
= get_capability_version(s
, base_offset
);
1525 uint8_t type
= get_device_type(s
, base_offset
);
1526 uint8_t pcie_size
= 0;
1529 /* calculate size depend on capability version and device/port type */
1530 /* in case of PCI Express Base Specification Rev 1.x */
1532 /* The PCI Express Capabilities, Device Capabilities, and Device
1533 * Status/Control registers are required for all PCI Express devices.
1534 * The Link Capabilities and Link Status/Control are required for all
1535 * Endpoints that are not Root Complex Integrated Endpoints. Endpoints
1536 * are not required to implement registers other than those listed
1537 * above and terminate the capability structure.
1540 case PCI_EXP_TYPE_ENDPOINT
:
1541 case PCI_EXP_TYPE_LEG_END
:
1544 case PCI_EXP_TYPE_RC_END
:
1548 /* only EndPoint passthrough is supported */
1549 case PCI_EXP_TYPE_ROOT_PORT
:
1550 case PCI_EXP_TYPE_UPSTREAM
:
1551 case PCI_EXP_TYPE_DOWNSTREAM
:
1552 case PCI_EXP_TYPE_PCI_BRIDGE
:
1553 case PCI_EXP_TYPE_PCIE_BRIDGE
:
1554 case PCI_EXP_TYPE_RC_EC
:
1556 XEN_PT_ERR(d
, "Unsupported device/port type %#x.\n", type
);
1560 /* in case of PCI Express Base Specification Rev 2.0 */
1561 else if (version
== 2) {
1563 case PCI_EXP_TYPE_ENDPOINT
:
1564 case PCI_EXP_TYPE_LEG_END
:
1565 case PCI_EXP_TYPE_RC_END
:
1566 /* For Functions that do not implement the registers,
1567 * these spaces must be hardwired to 0b.
1571 /* only EndPoint passthrough is supported */
1572 case PCI_EXP_TYPE_ROOT_PORT
:
1573 case PCI_EXP_TYPE_UPSTREAM
:
1574 case PCI_EXP_TYPE_DOWNSTREAM
:
1575 case PCI_EXP_TYPE_PCI_BRIDGE
:
1576 case PCI_EXP_TYPE_PCIE_BRIDGE
:
1577 case PCI_EXP_TYPE_RC_EC
:
1579 XEN_PT_ERR(d
, "Unsupported device/port type %#x.\n", type
);
1583 XEN_PT_ERR(d
, "Unsupported capability version %#x.\n", version
);
1590 /* get MSI Capability Structure register group size */
1591 static int xen_pt_msi_size_init(XenPCIPassthroughState
*s
,
1592 const XenPTRegGroupInfo
*grp_reg
,
1593 uint32_t base_offset
, uint8_t *size
)
1595 PCIDevice
*d
= &s
->dev
;
1596 uint16_t msg_ctrl
= 0;
1597 uint8_t msi_size
= 0xa;
1599 msg_ctrl
= pci_get_word(d
->config
+ (base_offset
+ PCI_MSI_FLAGS
));
1601 /* check if 64-bit address is capable of per-vector masking */
1602 if (msg_ctrl
& PCI_MSI_FLAGS_64BIT
) {
1605 if (msg_ctrl
& PCI_MSI_FLAGS_MASKBIT
) {
1609 s
->msi
= g_new0(XenPTMSI
, 1);
1610 s
->msi
->pirq
= XEN_PT_UNASSIGNED_PIRQ
;
1615 /* get MSI-X Capability Structure register group size */
1616 static int xen_pt_msix_size_init(XenPCIPassthroughState
*s
,
1617 const XenPTRegGroupInfo
*grp_reg
,
1618 uint32_t base_offset
, uint8_t *size
)
1622 rc
= xen_pt_msix_init(s
, base_offset
);
1625 XEN_PT_ERR(&s
->dev
, "Internal error: Invalid xen_pt_msix_init.\n");
1629 *size
= grp_reg
->grp_size
;
1634 static const XenPTRegGroupInfo xen_pt_emu_reg_grps
[] = {
1635 /* Header Type0 reg group */
1638 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1640 .size_init
= xen_pt_reg_grp_size_init
,
1641 .emu_regs
= xen_pt_emu_reg_header0
,
1643 /* PCI PowerManagement Capability reg group */
1645 .grp_id
= PCI_CAP_ID_PM
,
1646 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1647 .grp_size
= PCI_PM_SIZEOF
,
1648 .size_init
= xen_pt_reg_grp_size_init
,
1649 .emu_regs
= xen_pt_emu_reg_pm
,
1651 /* AGP Capability Structure reg group */
1653 .grp_id
= PCI_CAP_ID_AGP
,
1654 .grp_type
= XEN_PT_GRP_TYPE_HARDWIRED
,
1656 .size_init
= xen_pt_reg_grp_size_init
,
1658 /* Vital Product Data Capability Structure reg group */
1660 .grp_id
= PCI_CAP_ID_VPD
,
1661 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1663 .size_init
= xen_pt_reg_grp_size_init
,
1664 .emu_regs
= xen_pt_emu_reg_vpd
,
1666 /* Slot Identification reg group */
1668 .grp_id
= PCI_CAP_ID_SLOTID
,
1669 .grp_type
= XEN_PT_GRP_TYPE_HARDWIRED
,
1671 .size_init
= xen_pt_reg_grp_size_init
,
1673 /* MSI Capability Structure reg group */
1675 .grp_id
= PCI_CAP_ID_MSI
,
1676 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1678 .size_init
= xen_pt_msi_size_init
,
1679 .emu_regs
= xen_pt_emu_reg_msi
,
1681 /* PCI-X Capabilities List Item reg group */
1683 .grp_id
= PCI_CAP_ID_PCIX
,
1684 .grp_type
= XEN_PT_GRP_TYPE_HARDWIRED
,
1686 .size_init
= xen_pt_reg_grp_size_init
,
1688 /* Vendor Specific Capability Structure reg group */
1690 .grp_id
= PCI_CAP_ID_VNDR
,
1691 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1693 .size_init
= xen_pt_vendor_size_init
,
1694 .emu_regs
= xen_pt_emu_reg_vendor
,
1696 /* SHPC Capability List Item reg group */
1698 .grp_id
= PCI_CAP_ID_SHPC
,
1699 .grp_type
= XEN_PT_GRP_TYPE_HARDWIRED
,
1701 .size_init
= xen_pt_reg_grp_size_init
,
1703 /* Subsystem ID and Subsystem Vendor ID Capability List Item reg group */
1705 .grp_id
= PCI_CAP_ID_SSVID
,
1706 .grp_type
= XEN_PT_GRP_TYPE_HARDWIRED
,
1708 .size_init
= xen_pt_reg_grp_size_init
,
1710 /* AGP 8x Capability Structure reg group */
1712 .grp_id
= PCI_CAP_ID_AGP3
,
1713 .grp_type
= XEN_PT_GRP_TYPE_HARDWIRED
,
1715 .size_init
= xen_pt_reg_grp_size_init
,
1717 /* PCI Express Capability Structure reg group */
1719 .grp_id
= PCI_CAP_ID_EXP
,
1720 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1722 .size_init
= xen_pt_pcie_size_init
,
1723 .emu_regs
= xen_pt_emu_reg_pcie
,
1725 /* MSI-X Capability Structure reg group */
1727 .grp_id
= PCI_CAP_ID_MSIX
,
1728 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1730 .size_init
= xen_pt_msix_size_init
,
1731 .emu_regs
= xen_pt_emu_reg_msix
,
1738 /* initialize Capabilities Pointer or Next Pointer register */
1739 static int xen_pt_ptr_reg_init(XenPCIPassthroughState
*s
,
1740 XenPTRegInfo
*reg
, uint32_t real_offset
,
1744 uint8_t *config
= s
->dev
.config
;
1745 uint32_t reg_field
= pci_get_byte(config
+ real_offset
);
1748 /* find capability offset */
1750 for (i
= 0; xen_pt_emu_reg_grps
[i
].grp_size
!= 0; i
++) {
1751 if (xen_pt_hide_dev_cap(&s
->real_device
,
1752 xen_pt_emu_reg_grps
[i
].grp_id
)) {
1756 cap_id
= pci_get_byte(config
+ reg_field
+ PCI_CAP_LIST_ID
);
1757 if (xen_pt_emu_reg_grps
[i
].grp_id
== cap_id
) {
1758 if (xen_pt_emu_reg_grps
[i
].grp_type
== XEN_PT_GRP_TYPE_EMU
) {
1761 /* ignore the 0 hardwired capability, find next one */
1766 /* next capability */
1767 reg_field
= pci_get_byte(config
+ reg_field
+ PCI_CAP_LIST_NEXT
);
1780 static uint8_t find_cap_offset(XenPCIPassthroughState
*s
, uint8_t cap
)
1783 unsigned max_cap
= PCI_CAP_MAX
;
1784 uint8_t pos
= PCI_CAPABILITY_LIST
;
1787 if (xen_host_pci_get_byte(&s
->real_device
, PCI_STATUS
, &status
)) {
1790 if ((status
& PCI_STATUS_CAP_LIST
) == 0) {
1795 if (xen_host_pci_get_byte(&s
->real_device
, pos
, &pos
)) {
1798 if (pos
< PCI_CONFIG_HEADER_SIZE
) {
1803 if (xen_host_pci_get_byte(&s
->real_device
,
1804 pos
+ PCI_CAP_LIST_ID
, &id
)) {
1815 pos
+= PCI_CAP_LIST_NEXT
;
1820 static int xen_pt_config_reg_init(XenPCIPassthroughState
*s
,
1821 XenPTRegGroup
*reg_grp
, XenPTRegInfo
*reg
)
1823 XenPTReg
*reg_entry
;
1827 reg_entry
= g_new0(XenPTReg
, 1);
1828 reg_entry
->reg
= reg
;
1831 /* initialize emulate register */
1832 rc
= reg
->init(s
, reg_entry
->reg
,
1833 reg_grp
->base_offset
+ reg
->offset
, &data
);
1838 if (data
== XEN_PT_INVALID_REG
) {
1839 /* free unused BAR register entry */
1843 /* set register value */
1844 reg_entry
->data
= data
;
1846 /* list add register entry */
1847 QLIST_INSERT_HEAD(®_grp
->reg_tbl_list
, reg_entry
, entries
);
1852 int xen_pt_config_init(XenPCIPassthroughState
*s
)
1856 QLIST_INIT(&s
->reg_grps
);
1858 for (i
= 0; xen_pt_emu_reg_grps
[i
].grp_size
!= 0; i
++) {
1859 uint32_t reg_grp_offset
= 0;
1860 XenPTRegGroup
*reg_grp_entry
= NULL
;
1862 if (xen_pt_emu_reg_grps
[i
].grp_id
!= 0xFF) {
1863 if (xen_pt_hide_dev_cap(&s
->real_device
,
1864 xen_pt_emu_reg_grps
[i
].grp_id
)) {
1868 reg_grp_offset
= find_cap_offset(s
, xen_pt_emu_reg_grps
[i
].grp_id
);
1870 if (!reg_grp_offset
) {
1875 reg_grp_entry
= g_new0(XenPTRegGroup
, 1);
1876 QLIST_INIT(®_grp_entry
->reg_tbl_list
);
1877 QLIST_INSERT_HEAD(&s
->reg_grps
, reg_grp_entry
, entries
);
1879 reg_grp_entry
->base_offset
= reg_grp_offset
;
1880 reg_grp_entry
->reg_grp
= xen_pt_emu_reg_grps
+ i
;
1881 if (xen_pt_emu_reg_grps
[i
].size_init
) {
1882 /* get register group size */
1883 rc
= xen_pt_emu_reg_grps
[i
].size_init(s
, reg_grp_entry
->reg_grp
,
1885 ®_grp_entry
->size
);
1887 xen_pt_config_delete(s
);
1892 if (xen_pt_emu_reg_grps
[i
].grp_type
== XEN_PT_GRP_TYPE_EMU
) {
1893 if (xen_pt_emu_reg_grps
[i
].emu_regs
) {
1895 XenPTRegInfo
*regs
= xen_pt_emu_reg_grps
[i
].emu_regs
;
1896 /* initialize capability register */
1897 for (j
= 0; regs
->size
!= 0; j
++, regs
++) {
1898 /* initialize capability register */
1899 rc
= xen_pt_config_reg_init(s
, reg_grp_entry
, regs
);
1901 xen_pt_config_delete(s
);
1912 /* delete all emulate register */
1913 void xen_pt_config_delete(XenPCIPassthroughState
*s
)
1915 struct XenPTRegGroup
*reg_group
, *next_grp
;
1916 struct XenPTReg
*reg
, *next_reg
;
1918 /* free MSI/MSI-X info table */
1920 xen_pt_msix_delete(s
);
1926 /* free all register group entry */
1927 QLIST_FOREACH_SAFE(reg_group
, &s
->reg_grps
, entries
, next_grp
) {
1928 /* free all register entry */
1929 QLIST_FOREACH_SAFE(reg
, ®_group
->reg_tbl_list
, entries
, next_reg
) {
1930 QLIST_REMOVE(reg
, entries
);
1934 QLIST_REMOVE(reg_group
, entries
);