2 * Copyright (c) 2007, Neocleus Corporation.
3 * Copyright (c) 2007, Intel Corporation.
5 * This work is licensed under the terms of the GNU GPL, version 2. See
6 * the COPYING file in the top-level directory.
8 * Alex Novik <alex@neocleus.com>
9 * Allen Kay <allen.m.kay@intel.com>
10 * Guy Zana <guy@neocleus.com>
12 * This file implements direct PCI assignment to a HVM guest
15 #include "qemu/timer.h"
16 #include "hw/xen/xen_backend.h"
19 #define XEN_PT_MERGE_VALUE(value, data, val_mask) \
20 (((value) & (val_mask)) | ((data) & ~(val_mask)))
22 #define XEN_PT_INVALID_REG 0xFFFFFFFF /* invalid register value */
26 static int xen_pt_ptr_reg_init(XenPCIPassthroughState
*s
, XenPTRegInfo
*reg
,
27 uint32_t real_offset
, uint32_t *data
);
32 /* A return value of 1 means the capability should NOT be exposed to guest. */
33 static int xen_pt_hide_dev_cap(const XenHostPCIDevice
*d
, uint8_t grp_id
)
37 /* The PCI Express Capability Structure of the VF of Intel 82599 10GbE
38 * Controller looks trivial, e.g., the PCI Express Capabilities
39 * Register is 0. We should not try to expose it to guest.
41 * The datasheet is available at
42 * http://download.intel.com/design/network/datashts/82599_datasheet.pdf
44 * See 'Table 9.7. VF PCIe Configuration Space' of the datasheet, the
45 * PCI Express Capability Structure of the VF of Intel 82599 10GbE
46 * Controller looks trivial, e.g., the PCI Express Capabilities
47 * Register is 0, so the Capability Version is 0 and
48 * xen_pt_pcie_size_init() would fail.
50 if (d
->vendor_id
== PCI_VENDOR_ID_INTEL
&&
51 d
->device_id
== PCI_DEVICE_ID_INTEL_82599_SFP_VF
) {
59 /* find emulate register group entry */
60 XenPTRegGroup
*xen_pt_find_reg_grp(XenPCIPassthroughState
*s
, uint32_t address
)
62 XenPTRegGroup
*entry
= NULL
;
64 /* find register group entry */
65 QLIST_FOREACH(entry
, &s
->reg_grps
, entries
) {
67 if ((entry
->base_offset
<= address
)
68 && ((entry
->base_offset
+ entry
->size
) > address
)) {
73 /* group entry not found */
77 /* find emulate register entry */
78 XenPTReg
*xen_pt_find_reg(XenPTRegGroup
*reg_grp
, uint32_t address
)
80 XenPTReg
*reg_entry
= NULL
;
81 XenPTRegInfo
*reg
= NULL
;
82 uint32_t real_offset
= 0;
84 /* find register entry */
85 QLIST_FOREACH(reg_entry
, ®_grp
->reg_tbl_list
, entries
) {
87 real_offset
= reg_grp
->base_offset
+ reg
->offset
;
89 if ((real_offset
<= address
)
90 && ((real_offset
+ reg
->size
) > address
)) {
98 static uint32_t get_throughable_mask(const XenPCIPassthroughState
*s
,
99 XenPTRegInfo
*reg
, uint32_t valid_mask
)
101 uint32_t throughable_mask
= ~(reg
->emu_mask
| reg
->ro_mask
);
103 if (!s
->permissive
) {
104 throughable_mask
&= ~reg
->res_mask
;
107 return throughable_mask
& valid_mask
;
111 * general register functions
114 /* register initialization function */
116 static int xen_pt_common_reg_init(XenPCIPassthroughState
*s
,
117 XenPTRegInfo
*reg
, uint32_t real_offset
,
120 *data
= reg
->init_val
;
124 /* Read register functions */
126 static int xen_pt_byte_reg_read(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
127 uint8_t *value
, uint8_t valid_mask
)
129 XenPTRegInfo
*reg
= cfg_entry
->reg
;
130 uint8_t valid_emu_mask
= 0;
132 /* emulate byte register */
133 valid_emu_mask
= reg
->emu_mask
& valid_mask
;
134 *value
= XEN_PT_MERGE_VALUE(*value
, cfg_entry
->data
, ~valid_emu_mask
);
138 static int xen_pt_word_reg_read(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
139 uint16_t *value
, uint16_t valid_mask
)
141 XenPTRegInfo
*reg
= cfg_entry
->reg
;
142 uint16_t valid_emu_mask
= 0;
144 /* emulate word register */
145 valid_emu_mask
= reg
->emu_mask
& valid_mask
;
146 *value
= XEN_PT_MERGE_VALUE(*value
, cfg_entry
->data
, ~valid_emu_mask
);
150 static int xen_pt_long_reg_read(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
151 uint32_t *value
, uint32_t valid_mask
)
153 XenPTRegInfo
*reg
= cfg_entry
->reg
;
154 uint32_t valid_emu_mask
= 0;
156 /* emulate long register */
157 valid_emu_mask
= reg
->emu_mask
& valid_mask
;
158 *value
= XEN_PT_MERGE_VALUE(*value
, cfg_entry
->data
, ~valid_emu_mask
);
163 /* Write register functions */
165 static int xen_pt_byte_reg_write(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
166 uint8_t *val
, uint8_t dev_value
,
169 XenPTRegInfo
*reg
= cfg_entry
->reg
;
170 uint8_t writable_mask
= 0;
171 uint8_t throughable_mask
= get_throughable_mask(s
, reg
, valid_mask
);
173 /* modify emulate register */
174 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
175 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
177 /* create value for writing to I/O device register */
178 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
182 static int xen_pt_word_reg_write(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
183 uint16_t *val
, uint16_t dev_value
,
186 XenPTRegInfo
*reg
= cfg_entry
->reg
;
187 uint16_t writable_mask
= 0;
188 uint16_t throughable_mask
= get_throughable_mask(s
, reg
, valid_mask
);
190 /* modify emulate register */
191 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
192 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
194 /* create value for writing to I/O device register */
195 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
199 static int xen_pt_long_reg_write(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
200 uint32_t *val
, uint32_t dev_value
,
203 XenPTRegInfo
*reg
= cfg_entry
->reg
;
204 uint32_t writable_mask
= 0;
205 uint32_t throughable_mask
= get_throughable_mask(s
, reg
, valid_mask
);
207 /* modify emulate register */
208 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
209 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
211 /* create value for writing to I/O device register */
212 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
218 /* XenPTRegInfo declaration
219 * - only for emulated register (either a part or whole bit).
220 * - for passthrough register that need special behavior (like interacting with
221 * other component), set emu_mask to all 0 and specify r/w func properly.
222 * - do NOT use ALL F for init_val, otherwise the tbl will not be registered.
225 /********************
229 static int xen_pt_vendor_reg_init(XenPCIPassthroughState
*s
,
230 XenPTRegInfo
*reg
, uint32_t real_offset
,
233 *data
= s
->real_device
.vendor_id
;
236 static int xen_pt_device_reg_init(XenPCIPassthroughState
*s
,
237 XenPTRegInfo
*reg
, uint32_t real_offset
,
240 *data
= s
->real_device
.device_id
;
243 static int xen_pt_status_reg_init(XenPCIPassthroughState
*s
,
244 XenPTRegInfo
*reg
, uint32_t real_offset
,
247 XenPTRegGroup
*reg_grp_entry
= NULL
;
248 XenPTReg
*reg_entry
= NULL
;
249 uint32_t reg_field
= 0;
251 /* find Header register group */
252 reg_grp_entry
= xen_pt_find_reg_grp(s
, PCI_CAPABILITY_LIST
);
254 /* find Capabilities Pointer register */
255 reg_entry
= xen_pt_find_reg(reg_grp_entry
, PCI_CAPABILITY_LIST
);
257 /* check Capabilities Pointer register */
258 if (reg_entry
->data
) {
259 reg_field
|= PCI_STATUS_CAP_LIST
;
261 reg_field
&= ~PCI_STATUS_CAP_LIST
;
264 xen_shutdown_fatal_error("Internal error: Couldn't find XenPTReg*"
265 " for Capabilities Pointer register."
266 " (%s)\n", __func__
);
270 xen_shutdown_fatal_error("Internal error: Couldn't find XenPTRegGroup"
271 " for Header. (%s)\n", __func__
);
278 static int xen_pt_header_type_reg_init(XenPCIPassthroughState
*s
,
279 XenPTRegInfo
*reg
, uint32_t real_offset
,
282 /* read PCI_HEADER_TYPE */
283 *data
= reg
->init_val
| 0x80;
287 /* initialize Interrupt Pin register */
288 static int xen_pt_irqpin_reg_init(XenPCIPassthroughState
*s
,
289 XenPTRegInfo
*reg
, uint32_t real_offset
,
292 *data
= xen_pt_pci_read_intx(s
);
296 /* Command register */
297 static int xen_pt_cmd_reg_write(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
298 uint16_t *val
, uint16_t dev_value
,
301 XenPTRegInfo
*reg
= cfg_entry
->reg
;
302 uint16_t writable_mask
= 0;
303 uint16_t throughable_mask
= get_throughable_mask(s
, reg
, valid_mask
);
305 /* modify emulate register */
306 writable_mask
= ~reg
->ro_mask
& valid_mask
;
307 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
309 /* create value for writing to I/O device register */
310 if (*val
& PCI_COMMAND_INTX_DISABLE
) {
311 throughable_mask
|= PCI_COMMAND_INTX_DISABLE
;
313 if (s
->machine_irq
) {
314 throughable_mask
|= PCI_COMMAND_INTX_DISABLE
;
318 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
324 #define XEN_PT_BAR_MEM_RO_MASK 0x0000000F /* BAR ReadOnly mask(Memory) */
325 #define XEN_PT_BAR_MEM_EMU_MASK 0xFFFFFFF0 /* BAR emul mask(Memory) */
326 #define XEN_PT_BAR_IO_RO_MASK 0x00000003 /* BAR ReadOnly mask(I/O) */
327 #define XEN_PT_BAR_IO_EMU_MASK 0xFFFFFFFC /* BAR emul mask(I/O) */
329 static bool is_64bit_bar(PCIIORegion
*r
)
331 return !!(r
->type
& PCI_BASE_ADDRESS_MEM_TYPE_64
);
334 static uint64_t xen_pt_get_bar_size(PCIIORegion
*r
)
336 if (is_64bit_bar(r
)) {
338 size64
= (r
+ 1)->size
;
346 static XenPTBarFlag
xen_pt_bar_reg_parse(XenPCIPassthroughState
*s
,
349 PCIDevice
*d
= &s
->dev
;
350 XenPTRegion
*region
= NULL
;
353 /* check 64bit BAR */
354 if ((0 < index
) && (index
< PCI_ROM_SLOT
)) {
355 int type
= s
->real_device
.io_regions
[index
- 1].type
;
357 if ((type
& XEN_HOST_PCI_REGION_TYPE_MEM
)
358 && (type
& XEN_HOST_PCI_REGION_TYPE_MEM_64
)) {
359 region
= &s
->bases
[index
- 1];
360 if (region
->bar_flag
!= XEN_PT_BAR_FLAG_UPPER
) {
361 return XEN_PT_BAR_FLAG_UPPER
;
366 /* check unused BAR */
367 r
= &d
->io_regions
[index
];
368 if (!xen_pt_get_bar_size(r
)) {
369 return XEN_PT_BAR_FLAG_UNUSED
;
373 if (index
== PCI_ROM_SLOT
) {
374 return XEN_PT_BAR_FLAG_MEM
;
377 /* check BAR I/O indicator */
378 if (s
->real_device
.io_regions
[index
].type
& XEN_HOST_PCI_REGION_TYPE_IO
) {
379 return XEN_PT_BAR_FLAG_IO
;
381 return XEN_PT_BAR_FLAG_MEM
;
385 static inline uint32_t base_address_with_flags(XenHostPCIIORegion
*hr
)
387 if (hr
->type
& XEN_HOST_PCI_REGION_TYPE_IO
) {
388 return hr
->base_addr
| (hr
->bus_flags
& ~PCI_BASE_ADDRESS_IO_MASK
);
390 return hr
->base_addr
| (hr
->bus_flags
& ~PCI_BASE_ADDRESS_MEM_MASK
);
394 static int xen_pt_bar_reg_init(XenPCIPassthroughState
*s
, XenPTRegInfo
*reg
,
395 uint32_t real_offset
, uint32_t *data
)
397 uint32_t reg_field
= 0;
400 index
= xen_pt_bar_offset_to_index(reg
->offset
);
401 if (index
< 0 || index
>= PCI_NUM_REGIONS
) {
402 XEN_PT_ERR(&s
->dev
, "Internal error: Invalid BAR index [%d].\n", index
);
407 s
->bases
[index
].bar_flag
= xen_pt_bar_reg_parse(s
, index
);
408 if (s
->bases
[index
].bar_flag
== XEN_PT_BAR_FLAG_UNUSED
) {
409 reg_field
= XEN_PT_INVALID_REG
;
415 static int xen_pt_bar_reg_read(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
416 uint32_t *value
, uint32_t valid_mask
)
418 XenPTRegInfo
*reg
= cfg_entry
->reg
;
419 uint32_t valid_emu_mask
= 0;
420 uint32_t bar_emu_mask
= 0;
424 index
= xen_pt_bar_offset_to_index(reg
->offset
);
425 if (index
< 0 || index
>= PCI_NUM_REGIONS
- 1) {
426 XEN_PT_ERR(&s
->dev
, "Internal error: Invalid BAR index [%d].\n", index
);
430 /* use fixed-up value from kernel sysfs */
431 *value
= base_address_with_flags(&s
->real_device
.io_regions
[index
]);
433 /* set emulate mask depend on BAR flag */
434 switch (s
->bases
[index
].bar_flag
) {
435 case XEN_PT_BAR_FLAG_MEM
:
436 bar_emu_mask
= XEN_PT_BAR_MEM_EMU_MASK
;
438 case XEN_PT_BAR_FLAG_IO
:
439 bar_emu_mask
= XEN_PT_BAR_IO_EMU_MASK
;
441 case XEN_PT_BAR_FLAG_UPPER
:
442 bar_emu_mask
= XEN_PT_BAR_ALLF
;
449 valid_emu_mask
= bar_emu_mask
& valid_mask
;
450 *value
= XEN_PT_MERGE_VALUE(*value
, cfg_entry
->data
, ~valid_emu_mask
);
454 static int xen_pt_bar_reg_write(XenPCIPassthroughState
*s
, XenPTReg
*cfg_entry
,
455 uint32_t *val
, uint32_t dev_value
,
458 XenPTRegInfo
*reg
= cfg_entry
->reg
;
459 XenPTRegion
*base
= NULL
;
460 PCIDevice
*d
= &s
->dev
;
461 const PCIIORegion
*r
;
462 uint32_t writable_mask
= 0;
463 uint32_t bar_emu_mask
= 0;
464 uint32_t bar_ro_mask
= 0;
468 index
= xen_pt_bar_offset_to_index(reg
->offset
);
469 if (index
< 0 || index
>= PCI_NUM_REGIONS
) {
470 XEN_PT_ERR(d
, "Internal error: Invalid BAR index [%d].\n", index
);
474 r
= &d
->io_regions
[index
];
475 base
= &s
->bases
[index
];
476 r_size
= xen_pt_get_emul_size(base
->bar_flag
, r
->size
);
478 /* set emulate mask and read-only mask values depend on the BAR flag */
479 switch (s
->bases
[index
].bar_flag
) {
480 case XEN_PT_BAR_FLAG_MEM
:
481 bar_emu_mask
= XEN_PT_BAR_MEM_EMU_MASK
;
483 /* low 32 bits mask for 64 bit bars */
484 bar_ro_mask
= XEN_PT_BAR_ALLF
;
486 bar_ro_mask
= XEN_PT_BAR_MEM_RO_MASK
| (r_size
- 1);
489 case XEN_PT_BAR_FLAG_IO
:
490 bar_emu_mask
= XEN_PT_BAR_IO_EMU_MASK
;
491 bar_ro_mask
= XEN_PT_BAR_IO_RO_MASK
| (r_size
- 1);
493 case XEN_PT_BAR_FLAG_UPPER
:
494 bar_emu_mask
= XEN_PT_BAR_ALLF
;
495 bar_ro_mask
= r_size
? r_size
- 1 : 0;
501 /* modify emulate register */
502 writable_mask
= bar_emu_mask
& ~bar_ro_mask
& valid_mask
;
503 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
505 /* check whether we need to update the virtual region address or not */
506 switch (s
->bases
[index
].bar_flag
) {
507 case XEN_PT_BAR_FLAG_UPPER
:
508 case XEN_PT_BAR_FLAG_MEM
:
511 case XEN_PT_BAR_FLAG_IO
:
518 /* create value for writing to I/O device register */
519 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, 0);
524 /* write Exp ROM BAR */
525 static int xen_pt_exp_rom_bar_reg_write(XenPCIPassthroughState
*s
,
526 XenPTReg
*cfg_entry
, uint32_t *val
,
527 uint32_t dev_value
, uint32_t valid_mask
)
529 XenPTRegInfo
*reg
= cfg_entry
->reg
;
530 XenPTRegion
*base
= NULL
;
531 PCIDevice
*d
= (PCIDevice
*)&s
->dev
;
532 uint32_t writable_mask
= 0;
533 uint32_t throughable_mask
= get_throughable_mask(s
, reg
, valid_mask
);
535 uint32_t bar_ro_mask
= 0;
537 r_size
= d
->io_regions
[PCI_ROM_SLOT
].size
;
538 base
= &s
->bases
[PCI_ROM_SLOT
];
539 /* align memory type resource size */
540 r_size
= xen_pt_get_emul_size(base
->bar_flag
, r_size
);
542 /* set emulate mask and read-only mask */
543 bar_ro_mask
= (reg
->ro_mask
| (r_size
- 1)) & ~PCI_ROM_ADDRESS_ENABLE
;
545 /* modify emulate register */
546 writable_mask
= ~bar_ro_mask
& valid_mask
;
547 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
549 /* create value for writing to I/O device register */
550 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
555 static int xen_pt_intel_opregion_read(XenPCIPassthroughState
*s
,
557 uint32_t *value
, uint32_t valid_mask
)
559 *value
= igd_read_opregion(s
);
563 static int xen_pt_intel_opregion_write(XenPCIPassthroughState
*s
,
564 XenPTReg
*cfg_entry
, uint32_t *value
,
565 uint32_t dev_value
, uint32_t valid_mask
)
567 igd_write_opregion(s
, *value
);
571 /* Header Type0 reg static information table */
572 static XenPTRegInfo xen_pt_emu_reg_header0
[] = {
575 .offset
= PCI_VENDOR_ID
,
580 .init
= xen_pt_vendor_reg_init
,
581 .u
.w
.read
= xen_pt_word_reg_read
,
582 .u
.w
.write
= xen_pt_word_reg_write
,
586 .offset
= PCI_DEVICE_ID
,
591 .init
= xen_pt_device_reg_init
,
592 .u
.w
.read
= xen_pt_word_reg_read
,
593 .u
.w
.write
= xen_pt_word_reg_write
,
597 .offset
= PCI_COMMAND
,
602 .init
= xen_pt_common_reg_init
,
603 .u
.w
.read
= xen_pt_word_reg_read
,
604 .u
.w
.write
= xen_pt_cmd_reg_write
,
606 /* Capabilities Pointer reg */
608 .offset
= PCI_CAPABILITY_LIST
,
613 .init
= xen_pt_ptr_reg_init
,
614 .u
.b
.read
= xen_pt_byte_reg_read
,
615 .u
.b
.write
= xen_pt_byte_reg_write
,
618 /* use emulated Cap Ptr value to initialize,
619 * so need to be declared after Cap Ptr reg
622 .offset
= PCI_STATUS
,
628 .init
= xen_pt_status_reg_init
,
629 .u
.w
.read
= xen_pt_word_reg_read
,
630 .u
.w
.write
= xen_pt_word_reg_write
,
632 /* Cache Line Size reg */
634 .offset
= PCI_CACHE_LINE_SIZE
,
639 .init
= xen_pt_common_reg_init
,
640 .u
.b
.read
= xen_pt_byte_reg_read
,
641 .u
.b
.write
= xen_pt_byte_reg_write
,
643 /* Latency Timer reg */
645 .offset
= PCI_LATENCY_TIMER
,
650 .init
= xen_pt_common_reg_init
,
651 .u
.b
.read
= xen_pt_byte_reg_read
,
652 .u
.b
.write
= xen_pt_byte_reg_write
,
654 /* Header Type reg */
656 .offset
= PCI_HEADER_TYPE
,
661 .init
= xen_pt_header_type_reg_init
,
662 .u
.b
.read
= xen_pt_byte_reg_read
,
663 .u
.b
.write
= xen_pt_byte_reg_write
,
665 /* Interrupt Line reg */
667 .offset
= PCI_INTERRUPT_LINE
,
672 .init
= xen_pt_common_reg_init
,
673 .u
.b
.read
= xen_pt_byte_reg_read
,
674 .u
.b
.write
= xen_pt_byte_reg_write
,
676 /* Interrupt Pin reg */
678 .offset
= PCI_INTERRUPT_PIN
,
683 .init
= xen_pt_irqpin_reg_init
,
684 .u
.b
.read
= xen_pt_byte_reg_read
,
685 .u
.b
.write
= xen_pt_byte_reg_write
,
688 /* mask of BAR need to be decided later, depends on IO/MEM type */
690 .offset
= PCI_BASE_ADDRESS_0
,
692 .init_val
= 0x00000000,
693 .init
= xen_pt_bar_reg_init
,
694 .u
.dw
.read
= xen_pt_bar_reg_read
,
695 .u
.dw
.write
= xen_pt_bar_reg_write
,
699 .offset
= PCI_BASE_ADDRESS_1
,
701 .init_val
= 0x00000000,
702 .init
= xen_pt_bar_reg_init
,
703 .u
.dw
.read
= xen_pt_bar_reg_read
,
704 .u
.dw
.write
= xen_pt_bar_reg_write
,
708 .offset
= PCI_BASE_ADDRESS_2
,
710 .init_val
= 0x00000000,
711 .init
= xen_pt_bar_reg_init
,
712 .u
.dw
.read
= xen_pt_bar_reg_read
,
713 .u
.dw
.write
= xen_pt_bar_reg_write
,
717 .offset
= PCI_BASE_ADDRESS_3
,
719 .init_val
= 0x00000000,
720 .init
= xen_pt_bar_reg_init
,
721 .u
.dw
.read
= xen_pt_bar_reg_read
,
722 .u
.dw
.write
= xen_pt_bar_reg_write
,
726 .offset
= PCI_BASE_ADDRESS_4
,
728 .init_val
= 0x00000000,
729 .init
= xen_pt_bar_reg_init
,
730 .u
.dw
.read
= xen_pt_bar_reg_read
,
731 .u
.dw
.write
= xen_pt_bar_reg_write
,
735 .offset
= PCI_BASE_ADDRESS_5
,
737 .init_val
= 0x00000000,
738 .init
= xen_pt_bar_reg_init
,
739 .u
.dw
.read
= xen_pt_bar_reg_read
,
740 .u
.dw
.write
= xen_pt_bar_reg_write
,
742 /* Expansion ROM BAR reg */
744 .offset
= PCI_ROM_ADDRESS
,
746 .init_val
= 0x00000000,
747 .ro_mask
= ~PCI_ROM_ADDRESS_MASK
& ~PCI_ROM_ADDRESS_ENABLE
,
748 .emu_mask
= (uint32_t)PCI_ROM_ADDRESS_MASK
,
749 .init
= xen_pt_bar_reg_init
,
750 .u
.dw
.read
= xen_pt_long_reg_read
,
751 .u
.dw
.write
= xen_pt_exp_rom_bar_reg_write
,
759 /*********************************
760 * Vital Product Data Capability
763 /* Vital Product Data Capability Structure reg static information table */
764 static XenPTRegInfo xen_pt_emu_reg_vpd
[] = {
766 .offset
= PCI_CAP_LIST_NEXT
,
771 .init
= xen_pt_ptr_reg_init
,
772 .u
.b
.read
= xen_pt_byte_reg_read
,
773 .u
.b
.write
= xen_pt_byte_reg_write
,
776 .offset
= PCI_VPD_ADDR
,
780 .init
= xen_pt_common_reg_init
,
781 .u
.w
.read
= xen_pt_word_reg_read
,
782 .u
.w
.write
= xen_pt_word_reg_write
,
790 /**************************************
791 * Vendor Specific Capability
794 /* Vendor Specific Capability Structure reg static information table */
795 static XenPTRegInfo xen_pt_emu_reg_vendor
[] = {
797 .offset
= PCI_CAP_LIST_NEXT
,
802 .init
= xen_pt_ptr_reg_init
,
803 .u
.b
.read
= xen_pt_byte_reg_read
,
804 .u
.b
.write
= xen_pt_byte_reg_write
,
812 /*****************************
813 * PCI Express Capability
816 static inline uint8_t get_capability_version(XenPCIPassthroughState
*s
,
820 if (xen_host_pci_get_byte(&s
->real_device
, offset
+ PCI_EXP_FLAGS
, &flag
)) {
823 return flag
& PCI_EXP_FLAGS_VERS
;
826 static inline uint8_t get_device_type(XenPCIPassthroughState
*s
,
830 if (xen_host_pci_get_byte(&s
->real_device
, offset
+ PCI_EXP_FLAGS
, &flag
)) {
833 return (flag
& PCI_EXP_FLAGS_TYPE
) >> 4;
836 /* initialize Link Control register */
837 static int xen_pt_linkctrl_reg_init(XenPCIPassthroughState
*s
,
838 XenPTRegInfo
*reg
, uint32_t real_offset
,
841 uint8_t cap_ver
= get_capability_version(s
, real_offset
- reg
->offset
);
842 uint8_t dev_type
= get_device_type(s
, real_offset
- reg
->offset
);
844 /* no need to initialize in case of Root Complex Integrated Endpoint
847 if ((dev_type
== PCI_EXP_TYPE_RC_END
) && (cap_ver
== 1)) {
848 *data
= XEN_PT_INVALID_REG
;
851 *data
= reg
->init_val
;
854 /* initialize Device Control 2 register */
855 static int xen_pt_devctrl2_reg_init(XenPCIPassthroughState
*s
,
856 XenPTRegInfo
*reg
, uint32_t real_offset
,
859 uint8_t cap_ver
= get_capability_version(s
, real_offset
- reg
->offset
);
861 /* no need to initialize in case of cap_ver 1.x */
863 *data
= XEN_PT_INVALID_REG
;
866 *data
= reg
->init_val
;
869 /* initialize Link Control 2 register */
870 static int xen_pt_linkctrl2_reg_init(XenPCIPassthroughState
*s
,
871 XenPTRegInfo
*reg
, uint32_t real_offset
,
874 uint8_t cap_ver
= get_capability_version(s
, real_offset
- reg
->offset
);
875 uint32_t reg_field
= 0;
877 /* no need to initialize in case of cap_ver 1.x */
879 reg_field
= XEN_PT_INVALID_REG
;
881 /* set Supported Link Speed */
884 rc
= xen_host_pci_get_byte(&s
->real_device
,
885 real_offset
- reg
->offset
+ PCI_EXP_LNKCAP
,
890 reg_field
|= PCI_EXP_LNKCAP_SLS
& lnkcap
;
897 /* PCI Express Capability Structure reg static information table */
898 static XenPTRegInfo xen_pt_emu_reg_pcie
[] = {
899 /* Next Pointer reg */
901 .offset
= PCI_CAP_LIST_NEXT
,
906 .init
= xen_pt_ptr_reg_init
,
907 .u
.b
.read
= xen_pt_byte_reg_read
,
908 .u
.b
.write
= xen_pt_byte_reg_write
,
910 /* Device Capabilities reg */
912 .offset
= PCI_EXP_DEVCAP
,
914 .init_val
= 0x00000000,
915 .ro_mask
= 0xFFFFFFFF,
916 .emu_mask
= 0x10000000,
917 .init
= xen_pt_common_reg_init
,
918 .u
.dw
.read
= xen_pt_long_reg_read
,
919 .u
.dw
.write
= xen_pt_long_reg_write
,
921 /* Device Control reg */
923 .offset
= PCI_EXP_DEVCTL
,
928 .init
= xen_pt_common_reg_init
,
929 .u
.w
.read
= xen_pt_word_reg_read
,
930 .u
.w
.write
= xen_pt_word_reg_write
,
932 /* Device Status reg */
934 .offset
= PCI_EXP_DEVSTA
,
938 .init
= xen_pt_common_reg_init
,
939 .u
.w
.read
= xen_pt_word_reg_read
,
940 .u
.w
.write
= xen_pt_word_reg_write
,
942 /* Link Control reg */
944 .offset
= PCI_EXP_LNKCTL
,
949 .init
= xen_pt_linkctrl_reg_init
,
950 .u
.w
.read
= xen_pt_word_reg_read
,
951 .u
.w
.write
= xen_pt_word_reg_write
,
953 /* Link Status reg */
955 .offset
= PCI_EXP_LNKSTA
,
958 .init
= xen_pt_common_reg_init
,
959 .u
.w
.read
= xen_pt_word_reg_read
,
960 .u
.w
.write
= xen_pt_word_reg_write
,
962 /* Device Control 2 reg */
969 .init
= xen_pt_devctrl2_reg_init
,
970 .u
.w
.read
= xen_pt_word_reg_read
,
971 .u
.w
.write
= xen_pt_word_reg_write
,
973 /* Link Control 2 reg */
980 .init
= xen_pt_linkctrl2_reg_init
,
981 .u
.w
.read
= xen_pt_word_reg_read
,
982 .u
.w
.write
= xen_pt_word_reg_write
,
990 /*********************************
991 * Power Management Capability
994 /* write Power Management Control/Status register */
995 static int xen_pt_pmcsr_reg_write(XenPCIPassthroughState
*s
,
996 XenPTReg
*cfg_entry
, uint16_t *val
,
997 uint16_t dev_value
, uint16_t valid_mask
)
999 XenPTRegInfo
*reg
= cfg_entry
->reg
;
1000 uint16_t writable_mask
= 0;
1001 uint16_t throughable_mask
= get_throughable_mask(s
, reg
, valid_mask
);
1003 /* modify emulate register */
1004 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
1005 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
1007 /* create value for writing to I/O device register */
1008 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
& ~PCI_PM_CTRL_PME_STATUS
,
1014 /* Power Management Capability reg static information table */
1015 static XenPTRegInfo xen_pt_emu_reg_pm
[] = {
1016 /* Next Pointer reg */
1018 .offset
= PCI_CAP_LIST_NEXT
,
1023 .init
= xen_pt_ptr_reg_init
,
1024 .u
.b
.read
= xen_pt_byte_reg_read
,
1025 .u
.b
.write
= xen_pt_byte_reg_write
,
1027 /* Power Management Capabilities reg */
1029 .offset
= PCI_CAP_FLAGS
,
1034 .init
= xen_pt_common_reg_init
,
1035 .u
.w
.read
= xen_pt_word_reg_read
,
1036 .u
.w
.write
= xen_pt_word_reg_write
,
1038 /* PCI Power Management Control/Status reg */
1040 .offset
= PCI_PM_CTRL
,
1046 .init
= xen_pt_common_reg_init
,
1047 .u
.w
.read
= xen_pt_word_reg_read
,
1048 .u
.w
.write
= xen_pt_pmcsr_reg_write
,
1056 /********************************
1061 #define xen_pt_msi_check_type(offset, flags, what) \
1062 ((offset) == ((flags) & PCI_MSI_FLAGS_64BIT ? \
1063 PCI_MSI_##what##_64 : PCI_MSI_##what##_32))
1065 /* Message Control register */
1066 static int xen_pt_msgctrl_reg_init(XenPCIPassthroughState
*s
,
1067 XenPTRegInfo
*reg
, uint32_t real_offset
,
1070 XenPTMSI
*msi
= s
->msi
;
1074 /* use I/O device register's value as initial value */
1075 rc
= xen_host_pci_get_word(&s
->real_device
, real_offset
, ®_field
);
1079 if (reg_field
& PCI_MSI_FLAGS_ENABLE
) {
1080 XEN_PT_LOG(&s
->dev
, "MSI already enabled, disabling it first\n");
1081 xen_host_pci_set_word(&s
->real_device
, real_offset
,
1082 reg_field
& ~PCI_MSI_FLAGS_ENABLE
);
1084 msi
->flags
|= reg_field
;
1085 msi
->ctrl_offset
= real_offset
;
1086 msi
->initialized
= false;
1087 msi
->mapped
= false;
1089 *data
= reg
->init_val
;
1092 static int xen_pt_msgctrl_reg_write(XenPCIPassthroughState
*s
,
1093 XenPTReg
*cfg_entry
, uint16_t *val
,
1094 uint16_t dev_value
, uint16_t valid_mask
)
1096 XenPTRegInfo
*reg
= cfg_entry
->reg
;
1097 XenPTMSI
*msi
= s
->msi
;
1098 uint16_t writable_mask
= 0;
1099 uint16_t throughable_mask
= get_throughable_mask(s
, reg
, valid_mask
);
1101 /* Currently no support for multi-vector */
1102 if (*val
& PCI_MSI_FLAGS_QSIZE
) {
1103 XEN_PT_WARN(&s
->dev
, "Tries to set more than 1 vector ctrl %x\n", *val
);
1106 /* modify emulate register */
1107 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
1108 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
1109 msi
->flags
|= cfg_entry
->data
& ~PCI_MSI_FLAGS_ENABLE
;
1111 /* create value for writing to I/O device register */
1112 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
1115 if (*val
& PCI_MSI_FLAGS_ENABLE
) {
1116 /* setup MSI pirq for the first time */
1117 if (!msi
->initialized
) {
1118 /* Init physical one */
1119 XEN_PT_LOG(&s
->dev
, "setup MSI (register: %x).\n", *val
);
1120 if (xen_pt_msi_setup(s
)) {
1121 /* We do not broadcast the error to the framework code, so
1122 * that MSI errors are contained in MSI emulation code and
1123 * QEMU can go on running.
1124 * Guest MSI would be actually not working.
1126 *val
&= ~PCI_MSI_FLAGS_ENABLE
;
1127 XEN_PT_WARN(&s
->dev
, "Can not map MSI (register: %x)!\n", *val
);
1130 if (xen_pt_msi_update(s
)) {
1131 *val
&= ~PCI_MSI_FLAGS_ENABLE
;
1132 XEN_PT_WARN(&s
->dev
, "Can not bind MSI (register: %x)!\n", *val
);
1135 msi
->initialized
= true;
1138 msi
->flags
|= PCI_MSI_FLAGS_ENABLE
;
1139 } else if (msi
->mapped
) {
1140 xen_pt_msi_disable(s
);
1146 /* initialize Message Upper Address register */
1147 static int xen_pt_msgaddr64_reg_init(XenPCIPassthroughState
*s
,
1148 XenPTRegInfo
*reg
, uint32_t real_offset
,
1151 /* no need to initialize in case of 32 bit type */
1152 if (!(s
->msi
->flags
& PCI_MSI_FLAGS_64BIT
)) {
1153 *data
= XEN_PT_INVALID_REG
;
1155 *data
= reg
->init_val
;
1160 /* this function will be called twice (for 32 bit and 64 bit type) */
1161 /* initialize Message Data register */
1162 static int xen_pt_msgdata_reg_init(XenPCIPassthroughState
*s
,
1163 XenPTRegInfo
*reg
, uint32_t real_offset
,
1166 uint32_t flags
= s
->msi
->flags
;
1167 uint32_t offset
= reg
->offset
;
1169 /* check the offset whether matches the type or not */
1170 if (xen_pt_msi_check_type(offset
, flags
, DATA
)) {
1171 *data
= reg
->init_val
;
1173 *data
= XEN_PT_INVALID_REG
;
1178 /* this function will be called twice (for 32 bit and 64 bit type) */
1179 /* initialize Mask register */
1180 static int xen_pt_mask_reg_init(XenPCIPassthroughState
*s
,
1181 XenPTRegInfo
*reg
, uint32_t real_offset
,
1184 uint32_t flags
= s
->msi
->flags
;
1186 /* check the offset whether matches the type or not */
1187 if (!(flags
& PCI_MSI_FLAGS_MASKBIT
)) {
1188 *data
= XEN_PT_INVALID_REG
;
1189 } else if (xen_pt_msi_check_type(reg
->offset
, flags
, MASK
)) {
1190 *data
= reg
->init_val
;
1192 *data
= XEN_PT_INVALID_REG
;
1197 /* this function will be called twice (for 32 bit and 64 bit type) */
1198 /* initialize Pending register */
1199 static int xen_pt_pending_reg_init(XenPCIPassthroughState
*s
,
1200 XenPTRegInfo
*reg
, uint32_t real_offset
,
1203 uint32_t flags
= s
->msi
->flags
;
1205 /* check the offset whether matches the type or not */
1206 if (!(flags
& PCI_MSI_FLAGS_MASKBIT
)) {
1207 *data
= XEN_PT_INVALID_REG
;
1208 } else if (xen_pt_msi_check_type(reg
->offset
, flags
, PENDING
)) {
1209 *data
= reg
->init_val
;
1211 *data
= XEN_PT_INVALID_REG
;
1216 /* write Message Address register */
1217 static int xen_pt_msgaddr32_reg_write(XenPCIPassthroughState
*s
,
1218 XenPTReg
*cfg_entry
, uint32_t *val
,
1219 uint32_t dev_value
, uint32_t valid_mask
)
1221 XenPTRegInfo
*reg
= cfg_entry
->reg
;
1222 uint32_t writable_mask
= 0;
1223 uint32_t old_addr
= cfg_entry
->data
;
1225 /* modify emulate register */
1226 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
1227 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
1228 s
->msi
->addr_lo
= cfg_entry
->data
;
1230 /* create value for writing to I/O device register */
1231 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, 0);
1234 if (cfg_entry
->data
!= old_addr
) {
1235 if (s
->msi
->mapped
) {
1236 xen_pt_msi_update(s
);
1242 /* write Message Upper Address register */
1243 static int xen_pt_msgaddr64_reg_write(XenPCIPassthroughState
*s
,
1244 XenPTReg
*cfg_entry
, uint32_t *val
,
1245 uint32_t dev_value
, uint32_t valid_mask
)
1247 XenPTRegInfo
*reg
= cfg_entry
->reg
;
1248 uint32_t writable_mask
= 0;
1249 uint32_t old_addr
= cfg_entry
->data
;
1251 /* check whether the type is 64 bit or not */
1252 if (!(s
->msi
->flags
& PCI_MSI_FLAGS_64BIT
)) {
1254 "Can't write to the upper address without 64 bit support\n");
1258 /* modify emulate register */
1259 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
1260 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
1261 /* update the msi_info too */
1262 s
->msi
->addr_hi
= cfg_entry
->data
;
1264 /* create value for writing to I/O device register */
1265 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, 0);
1268 if (cfg_entry
->data
!= old_addr
) {
1269 if (s
->msi
->mapped
) {
1270 xen_pt_msi_update(s
);
1278 /* this function will be called twice (for 32 bit and 64 bit type) */
1279 /* write Message Data register */
1280 static int xen_pt_msgdata_reg_write(XenPCIPassthroughState
*s
,
1281 XenPTReg
*cfg_entry
, uint16_t *val
,
1282 uint16_t dev_value
, uint16_t valid_mask
)
1284 XenPTRegInfo
*reg
= cfg_entry
->reg
;
1285 XenPTMSI
*msi
= s
->msi
;
1286 uint16_t writable_mask
= 0;
1287 uint16_t old_data
= cfg_entry
->data
;
1288 uint32_t offset
= reg
->offset
;
1290 /* check the offset whether matches the type or not */
1291 if (!xen_pt_msi_check_type(offset
, msi
->flags
, DATA
)) {
1292 /* exit I/O emulator */
1293 XEN_PT_ERR(&s
->dev
, "the offset does not match the 32/64 bit type!\n");
1297 /* modify emulate register */
1298 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
1299 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
1300 /* update the msi_info too */
1301 msi
->data
= cfg_entry
->data
;
1303 /* create value for writing to I/O device register */
1304 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, 0);
1307 if (cfg_entry
->data
!= old_data
) {
1309 xen_pt_msi_update(s
);
1316 /* MSI Capability Structure reg static information table */
1317 static XenPTRegInfo xen_pt_emu_reg_msi
[] = {
1318 /* Next Pointer reg */
1320 .offset
= PCI_CAP_LIST_NEXT
,
1325 .init
= xen_pt_ptr_reg_init
,
1326 .u
.b
.read
= xen_pt_byte_reg_read
,
1327 .u
.b
.write
= xen_pt_byte_reg_write
,
1329 /* Message Control reg */
1331 .offset
= PCI_MSI_FLAGS
,
1337 .init
= xen_pt_msgctrl_reg_init
,
1338 .u
.w
.read
= xen_pt_word_reg_read
,
1339 .u
.w
.write
= xen_pt_msgctrl_reg_write
,
1341 /* Message Address reg */
1343 .offset
= PCI_MSI_ADDRESS_LO
,
1345 .init_val
= 0x00000000,
1346 .ro_mask
= 0x00000003,
1347 .emu_mask
= 0xFFFFFFFF,
1348 .init
= xen_pt_common_reg_init
,
1349 .u
.dw
.read
= xen_pt_long_reg_read
,
1350 .u
.dw
.write
= xen_pt_msgaddr32_reg_write
,
1352 /* Message Upper Address reg (if PCI_MSI_FLAGS_64BIT set) */
1354 .offset
= PCI_MSI_ADDRESS_HI
,
1356 .init_val
= 0x00000000,
1357 .ro_mask
= 0x00000000,
1358 .emu_mask
= 0xFFFFFFFF,
1359 .init
= xen_pt_msgaddr64_reg_init
,
1360 .u
.dw
.read
= xen_pt_long_reg_read
,
1361 .u
.dw
.write
= xen_pt_msgaddr64_reg_write
,
1363 /* Message Data reg (16 bits of data for 32-bit devices) */
1365 .offset
= PCI_MSI_DATA_32
,
1370 .init
= xen_pt_msgdata_reg_init
,
1371 .u
.w
.read
= xen_pt_word_reg_read
,
1372 .u
.w
.write
= xen_pt_msgdata_reg_write
,
1374 /* Message Data reg (16 bits of data for 64-bit devices) */
1376 .offset
= PCI_MSI_DATA_64
,
1381 .init
= xen_pt_msgdata_reg_init
,
1382 .u
.w
.read
= xen_pt_word_reg_read
,
1383 .u
.w
.write
= xen_pt_msgdata_reg_write
,
1385 /* Mask reg (if PCI_MSI_FLAGS_MASKBIT set, for 32-bit devices) */
1387 .offset
= PCI_MSI_MASK_32
,
1389 .init_val
= 0x00000000,
1390 .ro_mask
= 0xFFFFFFFF,
1391 .emu_mask
= 0xFFFFFFFF,
1392 .init
= xen_pt_mask_reg_init
,
1393 .u
.dw
.read
= xen_pt_long_reg_read
,
1394 .u
.dw
.write
= xen_pt_long_reg_write
,
1396 /* Mask reg (if PCI_MSI_FLAGS_MASKBIT set, for 64-bit devices) */
1398 .offset
= PCI_MSI_MASK_64
,
1400 .init_val
= 0x00000000,
1401 .ro_mask
= 0xFFFFFFFF,
1402 .emu_mask
= 0xFFFFFFFF,
1403 .init
= xen_pt_mask_reg_init
,
1404 .u
.dw
.read
= xen_pt_long_reg_read
,
1405 .u
.dw
.write
= xen_pt_long_reg_write
,
1407 /* Pending reg (if PCI_MSI_FLAGS_MASKBIT set, for 32-bit devices) */
1409 .offset
= PCI_MSI_MASK_32
+ 4,
1411 .init_val
= 0x00000000,
1412 .ro_mask
= 0xFFFFFFFF,
1413 .emu_mask
= 0x00000000,
1414 .init
= xen_pt_pending_reg_init
,
1415 .u
.dw
.read
= xen_pt_long_reg_read
,
1416 .u
.dw
.write
= xen_pt_long_reg_write
,
1418 /* Pending reg (if PCI_MSI_FLAGS_MASKBIT set, for 64-bit devices) */
1420 .offset
= PCI_MSI_MASK_64
+ 4,
1422 .init_val
= 0x00000000,
1423 .ro_mask
= 0xFFFFFFFF,
1424 .emu_mask
= 0x00000000,
1425 .init
= xen_pt_pending_reg_init
,
1426 .u
.dw
.read
= xen_pt_long_reg_read
,
1427 .u
.dw
.write
= xen_pt_long_reg_write
,
1435 /**************************************
1439 /* Message Control register for MSI-X */
1440 static int xen_pt_msixctrl_reg_init(XenPCIPassthroughState
*s
,
1441 XenPTRegInfo
*reg
, uint32_t real_offset
,
1447 /* use I/O device register's value as initial value */
1448 rc
= xen_host_pci_get_word(&s
->real_device
, real_offset
, ®_field
);
1452 if (reg_field
& PCI_MSIX_FLAGS_ENABLE
) {
1453 XEN_PT_LOG(&s
->dev
, "MSIX already enabled, disabling it first\n");
1454 xen_host_pci_set_word(&s
->real_device
, real_offset
,
1455 reg_field
& ~PCI_MSIX_FLAGS_ENABLE
);
1458 s
->msix
->ctrl_offset
= real_offset
;
1460 *data
= reg
->init_val
;
1463 static int xen_pt_msixctrl_reg_write(XenPCIPassthroughState
*s
,
1464 XenPTReg
*cfg_entry
, uint16_t *val
,
1465 uint16_t dev_value
, uint16_t valid_mask
)
1467 XenPTRegInfo
*reg
= cfg_entry
->reg
;
1468 uint16_t writable_mask
= 0;
1469 uint16_t throughable_mask
= get_throughable_mask(s
, reg
, valid_mask
);
1470 int debug_msix_enabled_old
;
1472 /* modify emulate register */
1473 writable_mask
= reg
->emu_mask
& ~reg
->ro_mask
& valid_mask
;
1474 cfg_entry
->data
= XEN_PT_MERGE_VALUE(*val
, cfg_entry
->data
, writable_mask
);
1476 /* create value for writing to I/O device register */
1477 *val
= XEN_PT_MERGE_VALUE(*val
, dev_value
, throughable_mask
);
1480 if ((*val
& PCI_MSIX_FLAGS_ENABLE
)
1481 && !(*val
& PCI_MSIX_FLAGS_MASKALL
)) {
1482 xen_pt_msix_update(s
);
1483 } else if (!(*val
& PCI_MSIX_FLAGS_ENABLE
) && s
->msix
->enabled
) {
1484 xen_pt_msix_disable(s
);
1487 debug_msix_enabled_old
= s
->msix
->enabled
;
1488 s
->msix
->enabled
= !!(*val
& PCI_MSIX_FLAGS_ENABLE
);
1489 if (s
->msix
->enabled
!= debug_msix_enabled_old
) {
1490 XEN_PT_LOG(&s
->dev
, "%s MSI-X\n",
1491 s
->msix
->enabled
? "enable" : "disable");
1497 /* MSI-X Capability Structure reg static information table */
1498 static XenPTRegInfo xen_pt_emu_reg_msix
[] = {
1499 /* Next Pointer reg */
1501 .offset
= PCI_CAP_LIST_NEXT
,
1506 .init
= xen_pt_ptr_reg_init
,
1507 .u
.b
.read
= xen_pt_byte_reg_read
,
1508 .u
.b
.write
= xen_pt_byte_reg_write
,
1510 /* Message Control reg */
1512 .offset
= PCI_MSI_FLAGS
,
1518 .init
= xen_pt_msixctrl_reg_init
,
1519 .u
.w
.read
= xen_pt_word_reg_read
,
1520 .u
.w
.write
= xen_pt_msixctrl_reg_write
,
1527 static XenPTRegInfo xen_pt_emu_reg_igd_opregion
[] = {
1528 /* Intel IGFX OpRegion reg */
1533 .u
.dw
.read
= xen_pt_intel_opregion_read
,
1534 .u
.dw
.write
= xen_pt_intel_opregion_write
,
1541 /****************************
1545 /* capability structure register group size functions */
1547 static int xen_pt_reg_grp_size_init(XenPCIPassthroughState
*s
,
1548 const XenPTRegGroupInfo
*grp_reg
,
1549 uint32_t base_offset
, uint8_t *size
)
1551 *size
= grp_reg
->grp_size
;
1554 /* get Vendor Specific Capability Structure register group size */
1555 static int xen_pt_vendor_size_init(XenPCIPassthroughState
*s
,
1556 const XenPTRegGroupInfo
*grp_reg
,
1557 uint32_t base_offset
, uint8_t *size
)
1559 return xen_host_pci_get_byte(&s
->real_device
, base_offset
+ 0x02, size
);
1561 /* get PCI Express Capability Structure register group size */
1562 static int xen_pt_pcie_size_init(XenPCIPassthroughState
*s
,
1563 const XenPTRegGroupInfo
*grp_reg
,
1564 uint32_t base_offset
, uint8_t *size
)
1566 PCIDevice
*d
= &s
->dev
;
1567 uint8_t version
= get_capability_version(s
, base_offset
);
1568 uint8_t type
= get_device_type(s
, base_offset
);
1569 uint8_t pcie_size
= 0;
1572 /* calculate size depend on capability version and device/port type */
1573 /* in case of PCI Express Base Specification Rev 1.x */
1575 /* The PCI Express Capabilities, Device Capabilities, and Device
1576 * Status/Control registers are required for all PCI Express devices.
1577 * The Link Capabilities and Link Status/Control are required for all
1578 * Endpoints that are not Root Complex Integrated Endpoints. Endpoints
1579 * are not required to implement registers other than those listed
1580 * above and terminate the capability structure.
1583 case PCI_EXP_TYPE_ENDPOINT
:
1584 case PCI_EXP_TYPE_LEG_END
:
1587 case PCI_EXP_TYPE_RC_END
:
1591 /* only EndPoint passthrough is supported */
1592 case PCI_EXP_TYPE_ROOT_PORT
:
1593 case PCI_EXP_TYPE_UPSTREAM
:
1594 case PCI_EXP_TYPE_DOWNSTREAM
:
1595 case PCI_EXP_TYPE_PCI_BRIDGE
:
1596 case PCI_EXP_TYPE_PCIE_BRIDGE
:
1597 case PCI_EXP_TYPE_RC_EC
:
1599 XEN_PT_ERR(d
, "Unsupported device/port type %#x.\n", type
);
1603 /* in case of PCI Express Base Specification Rev 2.0 */
1604 else if (version
== 2) {
1606 case PCI_EXP_TYPE_ENDPOINT
:
1607 case PCI_EXP_TYPE_LEG_END
:
1608 case PCI_EXP_TYPE_RC_END
:
1609 /* For Functions that do not implement the registers,
1610 * these spaces must be hardwired to 0b.
1614 /* only EndPoint passthrough is supported */
1615 case PCI_EXP_TYPE_ROOT_PORT
:
1616 case PCI_EXP_TYPE_UPSTREAM
:
1617 case PCI_EXP_TYPE_DOWNSTREAM
:
1618 case PCI_EXP_TYPE_PCI_BRIDGE
:
1619 case PCI_EXP_TYPE_PCIE_BRIDGE
:
1620 case PCI_EXP_TYPE_RC_EC
:
1622 XEN_PT_ERR(d
, "Unsupported device/port type %#x.\n", type
);
1626 XEN_PT_ERR(d
, "Unsupported capability version %#x.\n", version
);
1633 /* get MSI Capability Structure register group size */
1634 static int xen_pt_msi_size_init(XenPCIPassthroughState
*s
,
1635 const XenPTRegGroupInfo
*grp_reg
,
1636 uint32_t base_offset
, uint8_t *size
)
1638 uint16_t msg_ctrl
= 0;
1639 uint8_t msi_size
= 0xa;
1642 rc
= xen_host_pci_get_word(&s
->real_device
, base_offset
+ PCI_MSI_FLAGS
,
1647 /* check if 64-bit address is capable of per-vector masking */
1648 if (msg_ctrl
& PCI_MSI_FLAGS_64BIT
) {
1651 if (msg_ctrl
& PCI_MSI_FLAGS_MASKBIT
) {
1655 s
->msi
= g_new0(XenPTMSI
, 1);
1656 s
->msi
->pirq
= XEN_PT_UNASSIGNED_PIRQ
;
1661 /* get MSI-X Capability Structure register group size */
1662 static int xen_pt_msix_size_init(XenPCIPassthroughState
*s
,
1663 const XenPTRegGroupInfo
*grp_reg
,
1664 uint32_t base_offset
, uint8_t *size
)
1668 rc
= xen_pt_msix_init(s
, base_offset
);
1671 XEN_PT_ERR(&s
->dev
, "Internal error: Invalid xen_pt_msix_init.\n");
1675 *size
= grp_reg
->grp_size
;
1680 static const XenPTRegGroupInfo xen_pt_emu_reg_grps
[] = {
1681 /* Header Type0 reg group */
1684 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1686 .size_init
= xen_pt_reg_grp_size_init
,
1687 .emu_regs
= xen_pt_emu_reg_header0
,
1689 /* PCI PowerManagement Capability reg group */
1691 .grp_id
= PCI_CAP_ID_PM
,
1692 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1693 .grp_size
= PCI_PM_SIZEOF
,
1694 .size_init
= xen_pt_reg_grp_size_init
,
1695 .emu_regs
= xen_pt_emu_reg_pm
,
1697 /* AGP Capability Structure reg group */
1699 .grp_id
= PCI_CAP_ID_AGP
,
1700 .grp_type
= XEN_PT_GRP_TYPE_HARDWIRED
,
1702 .size_init
= xen_pt_reg_grp_size_init
,
1704 /* Vital Product Data Capability Structure reg group */
1706 .grp_id
= PCI_CAP_ID_VPD
,
1707 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1709 .size_init
= xen_pt_reg_grp_size_init
,
1710 .emu_regs
= xen_pt_emu_reg_vpd
,
1712 /* Slot Identification reg group */
1714 .grp_id
= PCI_CAP_ID_SLOTID
,
1715 .grp_type
= XEN_PT_GRP_TYPE_HARDWIRED
,
1717 .size_init
= xen_pt_reg_grp_size_init
,
1719 /* MSI Capability Structure reg group */
1721 .grp_id
= PCI_CAP_ID_MSI
,
1722 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1724 .size_init
= xen_pt_msi_size_init
,
1725 .emu_regs
= xen_pt_emu_reg_msi
,
1727 /* PCI-X Capabilities List Item reg group */
1729 .grp_id
= PCI_CAP_ID_PCIX
,
1730 .grp_type
= XEN_PT_GRP_TYPE_HARDWIRED
,
1732 .size_init
= xen_pt_reg_grp_size_init
,
1734 /* Vendor Specific Capability Structure reg group */
1736 .grp_id
= PCI_CAP_ID_VNDR
,
1737 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1739 .size_init
= xen_pt_vendor_size_init
,
1740 .emu_regs
= xen_pt_emu_reg_vendor
,
1742 /* SHPC Capability List Item reg group */
1744 .grp_id
= PCI_CAP_ID_SHPC
,
1745 .grp_type
= XEN_PT_GRP_TYPE_HARDWIRED
,
1747 .size_init
= xen_pt_reg_grp_size_init
,
1749 /* Subsystem ID and Subsystem Vendor ID Capability List Item reg group */
1751 .grp_id
= PCI_CAP_ID_SSVID
,
1752 .grp_type
= XEN_PT_GRP_TYPE_HARDWIRED
,
1754 .size_init
= xen_pt_reg_grp_size_init
,
1756 /* AGP 8x Capability Structure reg group */
1758 .grp_id
= PCI_CAP_ID_AGP3
,
1759 .grp_type
= XEN_PT_GRP_TYPE_HARDWIRED
,
1761 .size_init
= xen_pt_reg_grp_size_init
,
1763 /* PCI Express Capability Structure reg group */
1765 .grp_id
= PCI_CAP_ID_EXP
,
1766 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1768 .size_init
= xen_pt_pcie_size_init
,
1769 .emu_regs
= xen_pt_emu_reg_pcie
,
1771 /* MSI-X Capability Structure reg group */
1773 .grp_id
= PCI_CAP_ID_MSIX
,
1774 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1776 .size_init
= xen_pt_msix_size_init
,
1777 .emu_regs
= xen_pt_emu_reg_msix
,
1779 /* Intel IGD Opregion group */
1781 .grp_id
= XEN_PCI_INTEL_OPREGION
,
1782 .grp_type
= XEN_PT_GRP_TYPE_EMU
,
1784 .size_init
= xen_pt_reg_grp_size_init
,
1785 .emu_regs
= xen_pt_emu_reg_igd_opregion
,
1792 /* initialize Capabilities Pointer or Next Pointer register */
1793 static int xen_pt_ptr_reg_init(XenPCIPassthroughState
*s
,
1794 XenPTRegInfo
*reg
, uint32_t real_offset
,
1801 rc
= xen_host_pci_get_byte(&s
->real_device
, real_offset
, ®_field
);
1805 /* find capability offset */
1807 for (i
= 0; xen_pt_emu_reg_grps
[i
].grp_size
!= 0; i
++) {
1808 if (xen_pt_hide_dev_cap(&s
->real_device
,
1809 xen_pt_emu_reg_grps
[i
].grp_id
)) {
1813 rc
= xen_host_pci_get_byte(&s
->real_device
,
1814 reg_field
+ PCI_CAP_LIST_ID
, &cap_id
);
1818 if (xen_pt_emu_reg_grps
[i
].grp_id
== cap_id
) {
1819 if (xen_pt_emu_reg_grps
[i
].grp_type
== XEN_PT_GRP_TYPE_EMU
) {
1822 /* ignore the 0 hardwired capability, find next one */
1827 /* next capability */
1828 rc
= xen_host_pci_get_byte(&s
->real_device
,
1829 reg_field
+ PCI_CAP_LIST_NEXT
, ®_field
);
1845 static uint8_t find_cap_offset(XenPCIPassthroughState
*s
, uint8_t cap
)
1848 unsigned max_cap
= XEN_PCI_CAP_MAX
;
1849 uint8_t pos
= PCI_CAPABILITY_LIST
;
1852 if (xen_host_pci_get_byte(&s
->real_device
, PCI_STATUS
, &status
)) {
1855 if ((status
& PCI_STATUS_CAP_LIST
) == 0) {
1860 if (xen_host_pci_get_byte(&s
->real_device
, pos
, &pos
)) {
1863 if (pos
< PCI_CONFIG_HEADER_SIZE
) {
1868 if (xen_host_pci_get_byte(&s
->real_device
,
1869 pos
+ PCI_CAP_LIST_ID
, &id
)) {
1880 pos
+= PCI_CAP_LIST_NEXT
;
1885 static int xen_pt_config_reg_init(XenPCIPassthroughState
*s
,
1886 XenPTRegGroup
*reg_grp
, XenPTRegInfo
*reg
)
1888 XenPTReg
*reg_entry
;
1892 reg_entry
= g_new0(XenPTReg
, 1);
1893 reg_entry
->reg
= reg
;
1896 uint32_t host_mask
, size_mask
;
1897 unsigned int offset
;
1900 /* initialize emulate register */
1901 rc
= reg
->init(s
, reg_entry
->reg
,
1902 reg_grp
->base_offset
+ reg
->offset
, &data
);
1907 if (data
== XEN_PT_INVALID_REG
) {
1908 /* free unused BAR register entry */
1912 /* Sync up the data to dev.config */
1913 offset
= reg_grp
->base_offset
+ reg
->offset
;
1914 size_mask
= 0xFFFFFFFF >> ((4 - reg
->size
) << 3);
1916 switch (reg
->size
) {
1917 case 1: rc
= xen_host_pci_get_byte(&s
->real_device
, offset
, (uint8_t *)&val
);
1919 case 2: rc
= xen_host_pci_get_word(&s
->real_device
, offset
, (uint16_t *)&val
);
1921 case 4: rc
= xen_host_pci_get_long(&s
->real_device
, offset
, &val
);
1926 /* Serious issues when we cannot read the host values! */
1930 /* Set bits in emu_mask are the ones we emulate. The dev.config shall
1931 * contain the emulated view of the guest - therefore we flip the mask
1932 * to mask out the host values (which dev.config initially has) . */
1933 host_mask
= size_mask
& ~reg
->emu_mask
;
1935 if ((data
& host_mask
) != (val
& host_mask
)) {
1938 /* Mask out host (including past size). */
1939 new_val
= val
& host_mask
;
1940 /* Merge emulated ones (excluding the non-emulated ones). */
1941 new_val
|= data
& host_mask
;
1942 /* Leave intact host and emulated values past the size - even though
1943 * we do not care as we write per reg->size granularity, but for the
1944 * logging below lets have the proper value. */
1945 new_val
|= ((val
| data
)) & ~size_mask
;
1946 XEN_PT_LOG(&s
->dev
,"Offset 0x%04x mismatch! Emulated=0x%04x, host=0x%04x, syncing to 0x%04x.\n",
1947 offset
, data
, val
, new_val
);
1952 if (val
& ~size_mask
) {
1953 XEN_PT_ERR(&s
->dev
,"Offset 0x%04x:0x%04x expands past register size(%d)!\n",
1954 offset
, val
, reg
->size
);
1958 /* This could be just pci_set_long as we don't modify the bits
1959 * past reg->size, but in case this routine is run in parallel or the
1960 * init value is larger, we do not want to over-write registers. */
1961 switch (reg
->size
) {
1962 case 1: pci_set_byte(s
->dev
.config
+ offset
, (uint8_t)val
);
1964 case 2: pci_set_word(s
->dev
.config
+ offset
, (uint16_t)val
);
1966 case 4: pci_set_long(s
->dev
.config
+ offset
, val
);
1970 /* set register value */
1971 reg_entry
->data
= val
;
1974 /* list add register entry */
1975 QLIST_INSERT_HEAD(®_grp
->reg_tbl_list
, reg_entry
, entries
);
1980 int xen_pt_config_init(XenPCIPassthroughState
*s
)
1984 QLIST_INIT(&s
->reg_grps
);
1986 for (i
= 0; xen_pt_emu_reg_grps
[i
].grp_size
!= 0; i
++) {
1987 uint32_t reg_grp_offset
= 0;
1988 XenPTRegGroup
*reg_grp_entry
= NULL
;
1990 if (xen_pt_emu_reg_grps
[i
].grp_id
!= 0xFF
1991 && xen_pt_emu_reg_grps
[i
].grp_id
!= XEN_PCI_INTEL_OPREGION
) {
1992 if (xen_pt_hide_dev_cap(&s
->real_device
,
1993 xen_pt_emu_reg_grps
[i
].grp_id
)) {
1997 reg_grp_offset
= find_cap_offset(s
, xen_pt_emu_reg_grps
[i
].grp_id
);
1999 if (!reg_grp_offset
) {
2005 * By default we will trap up to 0x40 in the cfg space.
2006 * If an intel device is pass through we need to trap 0xfc,
2007 * therefore the size should be 0xff.
2009 if (xen_pt_emu_reg_grps
[i
].grp_id
== XEN_PCI_INTEL_OPREGION
) {
2010 reg_grp_offset
= XEN_PCI_INTEL_OPREGION
;
2013 reg_grp_entry
= g_new0(XenPTRegGroup
, 1);
2014 QLIST_INIT(®_grp_entry
->reg_tbl_list
);
2015 QLIST_INSERT_HEAD(&s
->reg_grps
, reg_grp_entry
, entries
);
2017 reg_grp_entry
->base_offset
= reg_grp_offset
;
2018 reg_grp_entry
->reg_grp
= xen_pt_emu_reg_grps
+ i
;
2019 if (xen_pt_emu_reg_grps
[i
].size_init
) {
2020 /* get register group size */
2021 rc
= xen_pt_emu_reg_grps
[i
].size_init(s
, reg_grp_entry
->reg_grp
,
2023 ®_grp_entry
->size
);
2025 xen_pt_config_delete(s
);
2030 if (xen_pt_emu_reg_grps
[i
].grp_type
== XEN_PT_GRP_TYPE_EMU
) {
2031 if (xen_pt_emu_reg_grps
[i
].emu_regs
) {
2033 XenPTRegInfo
*regs
= xen_pt_emu_reg_grps
[i
].emu_regs
;
2034 /* initialize capability register */
2035 for (j
= 0; regs
->size
!= 0; j
++, regs
++) {
2036 /* initialize capability register */
2037 rc
= xen_pt_config_reg_init(s
, reg_grp_entry
, regs
);
2039 xen_pt_config_delete(s
);
2050 /* delete all emulate register */
2051 void xen_pt_config_delete(XenPCIPassthroughState
*s
)
2053 struct XenPTRegGroup
*reg_group
, *next_grp
;
2054 struct XenPTReg
*reg
, *next_reg
;
2056 /* free MSI/MSI-X info table */
2058 xen_pt_msix_delete(s
);
2064 /* free all register group entry */
2065 QLIST_FOREACH_SAFE(reg_group
, &s
->reg_grps
, entries
, next_grp
) {
2066 /* free all register entry */
2067 QLIST_FOREACH_SAFE(reg
, ®_group
->reg_tbl_list
, entries
, next_reg
) {
2068 QLIST_REMOVE(reg
, entries
);
2072 QLIST_REMOVE(reg_group
, entries
);