hw/xilinx_spips.c

   1 /*
   2  * QEMU model of the Xilinx Zynq SPI controller
   3  *
   4  * Copyright (c) 2012 Peter A. G. Crosthwaite
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24
  25 #include "sysbus.h"
  26 #include "sysemu.h"
  27 #include "ptimer.h"
  28 #include "qemu-log.h"
  29 #include "fifo.h"
  30 #include "ssi.h"
  31
  32 #ifdef XILINX_SPIPS_ERR_DEBUG
  33 #define DB_PRINT(...) do { \
  34     fprintf(stderr,  ": %s: ", __func__); \
  35     fprintf(stderr, ## __VA_ARGS__); \
  36     } while (0);
  37 #else
  38     #define DB_PRINT(...)
  39 #endif
  40
  41 /* config register */
  42 #define R_CONFIG            (0x00 / 4)
  43 #define MODEFAIL_GEN_EN     (1 << 17)
  44 #define MAN_START_COM       (1 << 16)
  45 #define MAN_START_EN        (1 << 15)
  46 #define MANUAL_CS           (1 << 14)
  47 #define CS                  (0xF << 10)
  48 #define CS_SHIFT            (10)
  49 #define PERI_SEL            (1 << 9)
  50 #define REF_CLK             (1 << 8)
  51 #define FIFO_WIDTH          (3 << 6)
  52 #define BAUD_RATE_DIV       (7 << 3)
  53 #define CLK_PH              (1 << 2)
  54 #define CLK_POL             (1 << 1)
  55 #define MODE_SEL            (1 << 0)
  56
  57 /* interrupt mechanism */
  58 #define R_INTR_STATUS       (0x04 / 4)
  59 #define R_INTR_EN           (0x08 / 4)
  60 #define R_INTR_DIS          (0x0C / 4)
  61 #define R_INTR_MASK         (0x10 / 4)
  62 #define IXR_TX_FIFO_UNDERFLOW   (1 << 6)
  63 #define IXR_RX_FIFO_FULL        (1 << 5)
  64 #define IXR_RX_FIFO_NOT_EMPTY   (1 << 4)
  65 #define IXR_TX_FIFO_FULL        (1 << 3)
  66 #define IXR_TX_FIFO_NOT_FULL    (1 << 2)
  67 #define IXR_TX_FIFO_MODE_FAIL   (1 << 1)
  68 #define IXR_RX_FIFO_OVERFLOW    (1 << 0)
  69 #define IXR_ALL                 ((IXR_TX_FIFO_UNDERFLOW<<1)-1)
  70
  71 #define R_EN                (0x14 / 4)
  72 #define R_DELAY             (0x18 / 4)
  73 #define R_TX_DATA           (0x1C / 4)
  74 #define R_RX_DATA           (0x20 / 4)
  75 #define R_SLAVE_IDLE_COUNT  (0x24 / 4)
  76 #define R_TX_THRES          (0x28 / 4)
  77 #define R_RX_THRES          (0x2C / 4)
  78 #define R_MOD_ID            (0xFC / 4)
  79
  80 #define R_MAX (R_MOD_ID+1)
  81
  82 /* size of TXRX FIFOs */
  83 #define NUM_CS_LINES    4
  84 #define RXFF_A          32
  85 #define TXFF_A          32
  86
  87 typedef struct {
  88     SysBusDevice busdev;
  89     MemoryRegion iomem;
  90     qemu_irq irq;
  91     int irqline;
  92
  93     qemu_irq cs_lines[NUM_CS_LINES];
  94     SSIBus *spi;
  95
  96     Fifo8 rx_fifo;
  97     Fifo8 tx_fifo;
  98
  99     uint32_t regs[R_MAX];
 100 } XilinxSPIPS;
 101
 102 static void xilinx_spips_update_cs_lines(XilinxSPIPS *s)
 103 {
 104     int i;
 105     bool found = false;
 106     int field = s->regs[R_CONFIG] >> CS_SHIFT;
 107
 108     for (i = 0; i < NUM_CS_LINES; i++) {
 109         if (~field & (1 << i) && !found) {
 110             found = true;
 111             DB_PRINT("selecting slave %d\n", i);
 112             qemu_set_irq(s->cs_lines[i], 0);
 113         } else {
 114             qemu_set_irq(s->cs_lines[i], 1);
 115         }
 116      }
 117 }
 118
 119 static void xilinx_spips_update_ixr(XilinxSPIPS *s)
 120 {
 121     /* These are set/cleared as they occur */
 122     s->regs[R_INTR_STATUS] &= (IXR_TX_FIFO_UNDERFLOW | IXR_RX_FIFO_OVERFLOW |
 123                                 IXR_TX_FIFO_MODE_FAIL);
 124     /* these are pure functions of fifo state, set them here */
 125     s->regs[R_INTR_STATUS] |=
 126         (fifo8_is_full(&s->rx_fifo) ? IXR_RX_FIFO_FULL : 0) |
 127         (s->rx_fifo.num >= s->regs[R_RX_THRES] ? IXR_RX_FIFO_NOT_EMPTY : 0) |
 128         (fifo8_is_full(&s->tx_fifo) ? IXR_TX_FIFO_FULL : 0) |
 129         (s->tx_fifo.num < s->regs[R_TX_THRES] ? IXR_TX_FIFO_NOT_FULL : 0);
 130     /* drive external interrupt pin */
 131     int new_irqline = !!(s->regs[R_INTR_MASK] & s->regs[R_INTR_STATUS] &
 132                                                                 IXR_ALL);
 133     if (new_irqline != s->irqline) {
 134         s->irqline = new_irqline;
 135         qemu_set_irq(s->irq, s->irqline);
 136     }
 137 }
 138
 139 static void xilinx_spips_reset(DeviceState *d)
 140 {
 141     XilinxSPIPS *s = DO_UPCAST(XilinxSPIPS, busdev.qdev, d);
 142
 143     int i;
 144     for (i = 0; i < R_MAX; i++) {
 145         s->regs[i] = 0;
 146     }
 147
 148     fifo8_reset(&s->rx_fifo);
 149     fifo8_reset(&s->rx_fifo);
 150     /* non zero resets */
 151     s->regs[R_CONFIG] |= MODEFAIL_GEN_EN;
 152     s->regs[R_SLAVE_IDLE_COUNT] = 0xFF;
 153     s->regs[R_TX_THRES] = 1;
 154     s->regs[R_RX_THRES] = 1;
 155     /* FIXME: move magic number definition somewhere sensible */
 156     s->regs[R_MOD_ID] = 0x01090106;
 157     xilinx_spips_update_ixr(s);
 158     xilinx_spips_update_cs_lines(s);
 159 }
 160
 161 static void xilinx_spips_flush_txfifo(XilinxSPIPS *s)
 162 {
 163     for (;;) {
 164         uint32_t r;
 165         uint8_t value;
 166
 167         if (fifo8_is_empty(&s->tx_fifo)) {
 168             s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW;
 169             break;
 170         } else {
 171             value = fifo8_pop(&s->tx_fifo);
 172         }
 173
 174         r = ssi_transfer(s->spi, (uint32_t)value);
 175         DB_PRINT("tx = %02x rx = %02x\n", value, r);
 176         if (fifo8_is_full(&s->rx_fifo)) {
 177             s->regs[R_INTR_STATUS] |= IXR_RX_FIFO_OVERFLOW;
 178             DB_PRINT("rx FIFO overflow");
 179         } else {
 180             fifo8_push(&s->rx_fifo, (uint8_t)r);
 181         }
 182     }
 183     xilinx_spips_update_ixr(s);
 184 }
 185
 186 static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
 187                                                         unsigned size)
 188 {
 189     XilinxSPIPS *s = opaque;
 190     uint32_t mask = ~0;
 191     uint32_t ret;
 192
 193     addr >>= 2;
 194     switch (addr) {
 195     case R_CONFIG:
 196         mask = 0x0002FFFF;
 197         break;
 198     case R_INTR_STATUS:
 199     case R_INTR_MASK:
 200         mask = IXR_ALL;
 201         break;
 202     case  R_EN:
 203         mask = 0x1;
 204         break;
 205     case R_SLAVE_IDLE_COUNT:
 206         mask = 0xFF;
 207         break;
 208     case R_MOD_ID:
 209         mask = 0x01FFFFFF;
 210         break;
 211     case R_INTR_EN:
 212     case R_INTR_DIS:
 213     case R_TX_DATA:
 214         mask = 0;
 215         break;
 216     case R_RX_DATA:
 217         ret = (uint32_t)fifo8_pop(&s->rx_fifo);
 218         DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
 219         xilinx_spips_update_ixr(s);
 220         return ret;
 221     }
 222     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, s->regs[addr] & mask);
 223     return s->regs[addr] & mask;
 224
 225 }
 226
 227 static void xilinx_spips_write(void *opaque, hwaddr addr,
 228                                         uint64_t value, unsigned size)
 229 {
 230     int mask = ~0;
 231     int man_start_com = 0;
 232     XilinxSPIPS *s = opaque;
 233
 234     DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, (unsigned)value);
 235     addr >>= 2;
 236     switch (addr) {
 237     case R_CONFIG:
 238         mask = 0x0002FFFF;
 239         if (value & MAN_START_COM) {
 240             man_start_com = 1;
 241         }
 242         break;
 243     case R_INTR_STATUS:
 244         mask = IXR_ALL;
 245         s->regs[R_INTR_STATUS] &= ~(mask & value);
 246         goto no_reg_update;
 247     case R_INTR_DIS:
 248         mask = IXR_ALL;
 249         s->regs[R_INTR_MASK] &= ~(mask & value);
 250         goto no_reg_update;
 251     case R_INTR_EN:
 252         mask = IXR_ALL;
 253         s->regs[R_INTR_MASK] |= mask & value;
 254         goto no_reg_update;
 255     case R_EN:
 256         mask = 0x1;
 257         break;
 258     case R_SLAVE_IDLE_COUNT:
 259         mask = 0xFF;
 260         break;
 261     case R_RX_DATA:
 262     case R_INTR_MASK:
 263     case R_MOD_ID:
 264         mask = 0;
 265         break;
 266     case R_TX_DATA:
 267         fifo8_push(&s->tx_fifo, (uint8_t)value);
 268         goto no_reg_update;
 269     }
 270     s->regs[addr] = (s->regs[addr] & ~mask) | (value & mask);
 271 no_reg_update:
 272     if (man_start_com) {
 273         xilinx_spips_flush_txfifo(s);
 274     }
 275     xilinx_spips_update_ixr(s);
 276     xilinx_spips_update_cs_lines(s);
 277 }
 278
 279 static const MemoryRegionOps spips_ops = {
 280     .read = xilinx_spips_read,
 281     .write = xilinx_spips_write,
 282     .endianness = DEVICE_LITTLE_ENDIAN,
 283 };
 284
 285 static int xilinx_spips_init(SysBusDevice *dev)
 286 {
 287     XilinxSPIPS *s = FROM_SYSBUS(typeof(*s), dev);
 288     int i;
 289
 290     DB_PRINT("inited device model\n");
 291
 292     s->spi = ssi_create_bus(&dev->qdev, "spi");
 293
 294     ssi_auto_connect_slaves(DEVICE(s), s->cs_lines, s->spi);
 295     sysbus_init_irq(dev, &s->irq);
 296     for (i = 0; i < NUM_CS_LINES; ++i) {
 297         sysbus_init_irq(dev, &s->cs_lines[i]);
 298     }
 299
 300     memory_region_init_io(&s->iomem, &spips_ops, s, "spi", R_MAX*4);
 301     sysbus_init_mmio(dev, &s->iomem);
 302
 303     s->irqline = -1;
 304
 305     fifo8_create(&s->rx_fifo, RXFF_A);
 306     fifo8_create(&s->tx_fifo, TXFF_A);
 307
 308     return 0;
 309 }
 310
 311 static int xilinx_spips_post_load(void *opaque, int version_id)
 312 {
 313     xilinx_spips_update_ixr((XilinxSPIPS *)opaque);
 314     xilinx_spips_update_cs_lines((XilinxSPIPS *)opaque);
 315     return 0;
 316 }
 317
 318 static const VMStateDescription vmstate_xilinx_spips = {
 319     .name = "xilinx_spips",
 320     .version_id = 1,
 321     .minimum_version_id = 1,
 322     .minimum_version_id_old = 1,
 323     .post_load = xilinx_spips_post_load,
 324     .fields = (VMStateField[]) {
 325         VMSTATE_FIFO8(tx_fifo, XilinxSPIPS),
 326         VMSTATE_FIFO8(rx_fifo, XilinxSPIPS),
 327         VMSTATE_UINT32_ARRAY(regs, XilinxSPIPS, R_MAX),
 328         VMSTATE_END_OF_LIST()
 329     }
 330 };
 331
 332 static void xilinx_spips_class_init(ObjectClass *klass, void *data)
 333 {
 334     DeviceClass *dc = DEVICE_CLASS(klass);
 335     SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
 336
 337     sdc->init = xilinx_spips_init;
 338     dc->reset = xilinx_spips_reset;
 339     dc->vmsd = &vmstate_xilinx_spips;
 340 }
 341
 342 static const TypeInfo xilinx_spips_info = {
 343     .name  = "xilinx,spips",
 344     .parent = TYPE_SYS_BUS_DEVICE,
 345     .instance_size  = sizeof(XilinxSPIPS),
 346     .class_init = xilinx_spips_class_init,
 347 };
 348
 349 static void xilinx_spips_register_types(void)
 350 {
 351     type_register_static(&xilinx_spips_info);
 352 }
 353
 354 type_init(xilinx_spips_register_types)