hw/xio3130_upstream.c

   1 /*
   2  * xio3130_upstream.c
   3  * TI X3130 pci express upstream port switch
   4  *
   5  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
   6  *                    VA Linux Systems Japan K.K.
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License along
  19  * with this program; if not, see <http://www.gnu.org/licenses/>.
  20  */
  21
  22 #include "pci_ids.h"
  23 #include "msi.h"
  24 #include "pcie.h"
  25 #include "xio3130_upstream.h"
  26
  27 #define PCI_DEVICE_ID_TI_XIO3130U       0x8232  /* upstream port */
  28 #define XIO3130_REVISION                0x2
  29 #define XIO3130_MSI_OFFSET              0x70
  30 #define XIO3130_MSI_SUPPORTED_FLAGS     PCI_MSI_FLAGS_64BIT
  31 #define XIO3130_MSI_NR_VECTOR           1
  32 #define XIO3130_SSVID_OFFSET            0x80
  33 #define XIO3130_SSVID_SVID              0
  34 #define XIO3130_SSVID_SSID              0
  35 #define XIO3130_EXP_OFFSET              0x90
  36 #define XIO3130_AER_OFFSET              0x100
  37
  38 static void xio3130_upstream_write_config(PCIDevice *d, uint32_t address,
  39                                           uint32_t val, int len)
  40 {
  41     pci_bridge_write_config(d, address, val, len);
  42     pcie_cap_flr_write_config(d, address, val, len);
  43     pcie_aer_write_config(d, address, val, len);
  44 }
  45
  46 static void xio3130_upstream_reset(DeviceState *qdev)
  47 {
  48     PCIDevice *d = PCI_DEVICE(qdev);
  49
  50     pci_bridge_reset(qdev);
  51     pcie_cap_deverr_reset(d);
  52 }
  53
  54 static int xio3130_upstream_initfn(PCIDevice *d)
  55 {
  56     PCIBridge* br = DO_UPCAST(PCIBridge, dev, d);
  57     PCIEPort *p = DO_UPCAST(PCIEPort, br, br);
  58     int rc;
  59     int tmp;
  60
  61     rc = pci_bridge_initfn(d);
  62     if (rc < 0) {
  63         return rc;
  64     }
  65
  66     pcie_port_init_reg(d);
  67
  68     rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
  69                   XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
  70                   XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT);
  71     if (rc < 0) {
  72         goto err_bridge;
  73     }
  74     rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
  75                                XIO3130_SSVID_SVID, XIO3130_SSVID_SSID);
  76     if (rc < 0) {
  77         goto err_bridge;
  78     }
  79     rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM,
  80                        p->port);
  81     if (rc < 0) {
  82         goto err_msi;
  83     }
  84     pcie_cap_flr_init(d);
  85     pcie_cap_deverr_init(d);
  86     rc = pcie_aer_init(d, XIO3130_AER_OFFSET);
  87     if (rc < 0) {
  88         goto err;
  89     }
  90
  91     return 0;
  92
  93 err:
  94     pcie_cap_exit(d);
  95 err_msi:
  96     msi_uninit(d);
  97 err_bridge:
  98     tmp =  pci_bridge_exitfn(d);
  99     assert(!tmp);
 100     return rc;
 101 }
 102
 103 static int xio3130_upstream_exitfn(PCIDevice *d)
 104 {
 105     pcie_aer_exit(d);
 106     pcie_cap_exit(d);
 107     msi_uninit(d);
 108     return pci_bridge_exitfn(d);
 109 }
 110
 111 PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction,
 112                              const char *bus_name, pci_map_irq_fn map_irq,
 113                              uint8_t port)
 114 {
 115     PCIDevice *d;
 116     PCIBridge *br;
 117     DeviceState *qdev;
 118
 119     d = pci_create_multifunction(bus, devfn, multifunction, "x3130-upstream");
 120     if (!d) {
 121         return NULL;
 122     }
 123     br = DO_UPCAST(PCIBridge, dev, d);
 124
 125     qdev = &br->dev.qdev;
 126     pci_bridge_map_irq(br, bus_name, map_irq);
 127     qdev_prop_set_uint8(qdev, "port", port);
 128     qdev_init_nofail(qdev);
 129
 130     return DO_UPCAST(PCIEPort, br, br);
 131 }
 132
 133 static const VMStateDescription vmstate_xio3130_upstream = {
 134     .name = "xio3130-express-upstream-port",
 135     .version_id = 1,
 136     .minimum_version_id = 1,
 137     .minimum_version_id_old = 1,
 138     .fields = (VMStateField[]) {
 139         VMSTATE_PCIE_DEVICE(br.dev, PCIEPort),
 140         VMSTATE_STRUCT(br.dev.exp.aer_log, PCIEPort, 0, vmstate_pcie_aer_log,
 141                        PCIEAERLog),
 142         VMSTATE_END_OF_LIST()
 143     }
 144 };
 145
 146 static Property xio3130_upstream_properties[] = {
 147     DEFINE_PROP_UINT8("port", PCIEPort, port, 0),
 148     DEFINE_PROP_UINT16("aer_log_max", PCIEPort, br.dev.exp.aer_log.log_max,
 149     PCIE_AER_LOG_MAX_DEFAULT),
 150     DEFINE_PROP_END_OF_LIST(),
 151 };
 152
 153 static void xio3130_upstream_class_init(ObjectClass *klass, void *data)
 154 {
 155     DeviceClass *dc = DEVICE_CLASS(klass);
 156     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
 157
 158     k->is_express = 1;
 159     k->is_bridge = 1;
 160     k->config_write = xio3130_upstream_write_config;
 161     k->init = xio3130_upstream_initfn;
 162     k->exit = xio3130_upstream_exitfn;
 163     k->vendor_id = PCI_VENDOR_ID_TI;
 164     k->device_id = PCI_DEVICE_ID_TI_XIO3130U;
 165     k->revision = XIO3130_REVISION;
 166     dc->desc = "TI X3130 Upstream Port of PCI Express Switch";
 167     dc->reset = xio3130_upstream_reset;
 168     dc->vmsd = &vmstate_xio3130_upstream;
 169     dc->props = xio3130_upstream_properties;
 170 }
 171
 172 static TypeInfo xio3130_upstream_info = {
 173     .name          = "x3130-upstream",
 174     .parent        = TYPE_PCI_DEVICE,
 175     .instance_size = sizeof(PCIEPort),
 176     .class_init    = xio3130_upstream_class_init,
 177 };
 178
 179 static void xio3130_upstream_register_types(void)
 180 {
 181     type_register_static(&xio3130_upstream_info);
 182 }
 183
 184 type_init(xio3130_upstream_register_types)
 185
 186
 187 /*
 188  * Local variables:
 189  *  c-indent-level: 4
 190  *  c-basic-offset: 4
 191  *  tab-width: 8
 192  *  indent-tab-mode: nil
 193  * End:
 194  */