2 * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 * * Redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer.
9 * * Redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution.
12 * * Neither the name of the Open Source and Linux Lab nor the
13 * names of its contributors may be used to endorse or promote products
14 * derived from this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
20 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
22 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
23 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
25 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 #include "qemu/osdep.h"
29 #include "qapi/error.h"
30 #include "qemu-common.h"
32 #include "sysemu/sysemu.h"
33 #include "hw/boards.h"
34 #include "hw/loader.h"
36 #include "exec/memory.h"
37 #include "exec/address-spaces.h"
38 #include "hw/char/serial.h"
40 #include "hw/sysbus.h"
41 #include "hw/block/flash.h"
42 #include "sysemu/block-backend.h"
43 #include "chardev/char.h"
44 #include "sysemu/device_tree.h"
45 #include "qemu/error-report.h"
46 #include "bootparam.h"
47 #include "xtensa_memory.h"
49 typedef struct XtfpgaFlashDesc
{
56 typedef struct XtfpgaBoardDesc
{
57 const XtfpgaFlashDesc
*flash
;
61 typedef struct XtfpgaFpgaState
{
67 static void xtfpga_fpga_reset(void *opaque
)
69 XtfpgaFpgaState
*s
= opaque
;
75 static uint64_t xtfpga_fpga_read(void *opaque
, hwaddr addr
,
78 XtfpgaFpgaState
*s
= opaque
;
81 case 0x0: /*build date code*/
84 case 0x4: /*processor clock frequency, Hz*/
87 case 0x8: /*LEDs (off = 0, on = 1)*/
90 case 0xc: /*DIP switches (off = 0, on = 1)*/
96 static void xtfpga_fpga_write(void *opaque
, hwaddr addr
,
97 uint64_t val
, unsigned size
)
99 XtfpgaFpgaState
*s
= opaque
;
102 case 0x8: /*LEDs (off = 0, on = 1)*/
106 case 0x10: /*board reset*/
108 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET
);
114 static const MemoryRegionOps xtfpga_fpga_ops
= {
115 .read
= xtfpga_fpga_read
,
116 .write
= xtfpga_fpga_write
,
117 .endianness
= DEVICE_NATIVE_ENDIAN
,
120 static XtfpgaFpgaState
*xtfpga_fpga_init(MemoryRegion
*address_space
,
123 XtfpgaFpgaState
*s
= g_malloc(sizeof(XtfpgaFpgaState
));
125 memory_region_init_io(&s
->iomem
, NULL
, &xtfpga_fpga_ops
, s
,
126 "xtfpga.fpga", 0x10000);
127 memory_region_add_subregion(address_space
, base
, &s
->iomem
);
128 xtfpga_fpga_reset(s
);
129 qemu_register_reset(xtfpga_fpga_reset
, s
);
133 static void xtfpga_net_init(MemoryRegion
*address_space
,
137 qemu_irq irq
, NICInfo
*nd
)
143 dev
= qdev_create(NULL
, "open_eth");
144 qdev_set_nic_properties(dev
, nd
);
145 qdev_init_nofail(dev
);
147 s
= SYS_BUS_DEVICE(dev
);
148 sysbus_connect_irq(s
, 0, irq
);
149 memory_region_add_subregion(address_space
, base
,
150 sysbus_mmio_get_region(s
, 0));
151 memory_region_add_subregion(address_space
, descriptors
,
152 sysbus_mmio_get_region(s
, 1));
154 ram
= g_malloc(sizeof(*ram
));
155 memory_region_init_ram_nomigrate(ram
, OBJECT(s
), "open_eth.ram", 16384,
157 vmstate_register_ram_global(ram
);
158 memory_region_add_subregion(address_space
, buffers
, ram
);
161 static pflash_t
*xtfpga_flash_init(MemoryRegion
*address_space
,
162 const XtfpgaBoardDesc
*board
,
163 DriveInfo
*dinfo
, int be
)
166 DeviceState
*dev
= qdev_create(NULL
, "cfi.pflash01");
168 qdev_prop_set_drive(dev
, "drive", blk_by_legacy_dinfo(dinfo
),
170 qdev_prop_set_uint32(dev
, "num-blocks",
171 board
->flash
->size
/ board
->flash
->sector_size
);
172 qdev_prop_set_uint64(dev
, "sector-length", board
->flash
->sector_size
);
173 qdev_prop_set_uint8(dev
, "width", 2);
174 qdev_prop_set_bit(dev
, "big-endian", be
);
175 qdev_prop_set_string(dev
, "name", "xtfpga.io.flash");
176 qdev_init_nofail(dev
);
177 s
= SYS_BUS_DEVICE(dev
);
178 memory_region_add_subregion(address_space
, board
->flash
->base
,
179 sysbus_mmio_get_region(s
, 0));
180 return OBJECT_CHECK(pflash_t
, (dev
), "cfi.pflash01");
183 static uint64_t translate_phys_addr(void *opaque
, uint64_t addr
)
185 XtensaCPU
*cpu
= opaque
;
187 return cpu_get_phys_page_debug(CPU(cpu
), addr
);
190 static void xtfpga_reset(void *opaque
)
192 XtensaCPU
*cpu
= opaque
;
197 static uint64_t xtfpga_io_read(void *opaque
, hwaddr addr
,
203 static void xtfpga_io_write(void *opaque
, hwaddr addr
,
204 uint64_t val
, unsigned size
)
208 static const MemoryRegionOps xtfpga_io_ops
= {
209 .read
= xtfpga_io_read
,
210 .write
= xtfpga_io_write
,
211 .endianness
= DEVICE_NATIVE_ENDIAN
,
214 static void xtfpga_init(const XtfpgaBoardDesc
*board
, MachineState
*machine
)
216 #ifdef TARGET_WORDS_BIGENDIAN
221 MemoryRegion
*system_memory
= get_system_memory();
222 XtensaCPU
*cpu
= NULL
;
223 CPUXtensaState
*env
= NULL
;
224 MemoryRegion
*system_io
;
226 pflash_t
*flash
= NULL
;
227 QemuOpts
*machine_opts
= qemu_get_machine_opts();
228 const char *kernel_filename
= qemu_opt_get(machine_opts
, "kernel");
229 const char *kernel_cmdline
= qemu_opt_get(machine_opts
, "append");
230 const char *dtb_filename
= qemu_opt_get(machine_opts
, "dtb");
231 const char *initrd_filename
= qemu_opt_get(machine_opts
, "initrd");
234 for (n
= 0; n
< smp_cpus
; n
++) {
235 cpu
= XTENSA_CPU(cpu_create(machine
->cpu_type
));
238 env
->sregs
[PRID
] = n
;
239 qemu_register_reset(xtfpga_reset
, cpu
);
240 /* Need MMU initialized prior to ELF loading,
241 * so that ELF gets loaded into virtual addresses
247 XtensaMemory sysram
= env
->config
->sysram
;
249 sysram
.location
[0].size
= machine
->ram_size
;
250 xtensa_create_memory_regions(&env
->config
->instrom
, "xtensa.instrom",
252 xtensa_create_memory_regions(&env
->config
->instram
, "xtensa.instram",
254 xtensa_create_memory_regions(&env
->config
->datarom
, "xtensa.datarom",
256 xtensa_create_memory_regions(&env
->config
->dataram
, "xtensa.dataram",
258 xtensa_create_memory_regions(&sysram
, "xtensa.sysram",
262 system_io
= g_malloc(sizeof(*system_io
));
263 memory_region_init_io(system_io
, NULL
, &xtfpga_io_ops
, NULL
, "xtfpga.io",
265 memory_region_add_subregion(system_memory
, 0xf0000000, system_io
);
266 xtfpga_fpga_init(system_io
, 0x0d020000);
267 if (nd_table
[0].used
) {
268 xtfpga_net_init(system_io
, 0x0d030000, 0x0d030400, 0x0d800000,
269 xtensa_get_extint(env
, 1), nd_table
);
272 if (!serial_hds
[0]) {
273 serial_hds
[0] = qemu_chr_new("serial0", "null");
276 serial_mm_init(system_io
, 0x0d050020, 2, xtensa_get_extint(env
, 0),
277 115200, serial_hds
[0], DEVICE_NATIVE_ENDIAN
);
279 dinfo
= drive_get(IF_PFLASH
, 0, 0);
281 flash
= xtfpga_flash_init(system_io
, board
, dinfo
, be
);
284 /* Use presence of kernel file name as 'boot from SRAM' switch. */
285 if (kernel_filename
) {
286 uint32_t entry_point
= env
->pc
;
287 size_t bp_size
= 3 * get_tag_size(0); /* first/last and memory tags */
288 uint32_t tagptr
= env
->config
->sysrom
.location
[0].addr
+
291 BpMemInfo memory_location
= {
292 .type
= tswap32(MEMORY_TYPE_CONVENTIONAL
),
293 .start
= tswap32(env
->config
->sysram
.location
[0].addr
),
294 .end
= tswap32(env
->config
->sysram
.location
[0].addr
+
297 uint32_t lowmem_end
= machine
->ram_size
< 0x08000000 ?
298 machine
->ram_size
: 0x08000000;
299 uint32_t cur_lowmem
= QEMU_ALIGN_UP(lowmem_end
/ 2, 4096);
301 lowmem_end
+= env
->config
->sysram
.location
[0].addr
;
302 cur_lowmem
+= env
->config
->sysram
.location
[0].addr
;
304 xtensa_create_memory_regions(&env
->config
->sysrom
, "xtensa.sysrom",
307 if (kernel_cmdline
) {
308 bp_size
+= get_tag_size(strlen(kernel_cmdline
) + 1);
311 bp_size
+= get_tag_size(sizeof(uint32_t));
313 if (initrd_filename
) {
314 bp_size
+= get_tag_size(sizeof(BpMemInfo
));
317 /* Put kernel bootparameters to the end of that SRAM */
318 tagptr
= (tagptr
- bp_size
) & ~0xff;
319 cur_tagptr
= put_tag(tagptr
, BP_TAG_FIRST
, 0, NULL
);
320 cur_tagptr
= put_tag(cur_tagptr
, BP_TAG_MEMORY
,
321 sizeof(memory_location
), &memory_location
);
323 if (kernel_cmdline
) {
324 cur_tagptr
= put_tag(cur_tagptr
, BP_TAG_COMMAND_LINE
,
325 strlen(kernel_cmdline
) + 1, kernel_cmdline
);
330 void *fdt
= load_device_tree(dtb_filename
, &fdt_size
);
331 uint32_t dtb_addr
= tswap32(cur_lowmem
);
334 error_report("could not load DTB '%s'", dtb_filename
);
338 cpu_physical_memory_write(cur_lowmem
, fdt
, fdt_size
);
339 cur_tagptr
= put_tag(cur_tagptr
, BP_TAG_FDT
,
340 sizeof(dtb_addr
), &dtb_addr
);
341 cur_lowmem
= QEMU_ALIGN_UP(cur_lowmem
+ fdt_size
, 4096);
345 error_report("could not load DTB '%s': "
346 "FDT support is not configured in QEMU",
351 if (initrd_filename
) {
352 BpMemInfo initrd_location
= { 0 };
353 int initrd_size
= load_ramdisk(initrd_filename
, cur_lowmem
,
354 lowmem_end
- cur_lowmem
);
356 if (initrd_size
< 0) {
357 initrd_size
= load_image_targphys(initrd_filename
,
359 lowmem_end
- cur_lowmem
);
361 if (initrd_size
< 0) {
362 error_report("could not load initrd '%s'", initrd_filename
);
365 initrd_location
.start
= tswap32(cur_lowmem
);
366 initrd_location
.end
= tswap32(cur_lowmem
+ initrd_size
);
367 cur_tagptr
= put_tag(cur_tagptr
, BP_TAG_INITRD
,
368 sizeof(initrd_location
), &initrd_location
);
369 cur_lowmem
= QEMU_ALIGN_UP(cur_lowmem
+ initrd_size
, 4096);
371 cur_tagptr
= put_tag(cur_tagptr
, BP_TAG_LAST
, 0, NULL
);
372 env
->regs
[2] = tagptr
;
375 uint64_t elf_lowaddr
;
376 int success
= load_elf(kernel_filename
, translate_phys_addr
, cpu
,
377 &elf_entry
, &elf_lowaddr
, NULL
, be
, EM_XTENSA
, 0, 0);
379 entry_point
= elf_entry
;
383 success
= load_uimage(kernel_filename
, &ep
, NULL
, &is_linux
,
384 translate_phys_addr
, cpu
);
385 if (success
> 0 && is_linux
) {
388 error_report("could not load kernel '%s'",
393 if (entry_point
!= env
->pc
) {
395 #ifdef TARGET_WORDS_BIGENDIAN
396 0x60, 0x00, 0x08, /* j 1f */
397 0x00, /* .literal_position */
398 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
399 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
401 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */
402 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */
403 0x0a, 0x00, 0x00, /* jx a0 */
405 0x06, 0x02, 0x00, /* j 1f */
406 0x00, /* .literal_position */
407 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */
408 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */
410 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */
411 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */
412 0xa0, 0x00, 0x00, /* jx a0 */
415 uint32_t entry_pc
= tswap32(entry_point
);
416 uint32_t entry_a2
= tswap32(tagptr
);
418 memcpy(boot
+ 4, &entry_pc
, sizeof(entry_pc
));
419 memcpy(boot
+ 8, &entry_a2
, sizeof(entry_a2
));
420 cpu_physical_memory_write(env
->pc
, boot
, sizeof(boot
));
424 MemoryRegion
*flash_mr
= pflash_cfi01_get_memory(flash
);
425 MemoryRegion
*flash_io
= g_malloc(sizeof(*flash_io
));
426 uint32_t size
= env
->config
->sysrom
.location
[0].size
;
428 if (board
->flash
->size
- board
->flash
->boot_base
< size
) {
429 size
= board
->flash
->size
- board
->flash
->boot_base
;
432 memory_region_init_alias(flash_io
, NULL
, "xtfpga.flash",
433 flash_mr
, board
->flash
->boot_base
, size
);
434 memory_region_add_subregion(system_memory
,
435 env
->config
->sysrom
.location
[0].addr
,
438 xtensa_create_memory_regions(&env
->config
->sysrom
, "xtensa.sysrom",
444 static const XtfpgaFlashDesc lx60_flash
= {
447 .sector_size
= 0x10000,
450 static void xtfpga_lx60_init(MachineState
*machine
)
452 static const XtfpgaBoardDesc lx60_board
= {
453 .flash
= &lx60_flash
,
454 .sram_size
= 0x20000,
456 xtfpga_init(&lx60_board
, machine
);
459 static const XtfpgaFlashDesc lx200_flash
= {
462 .sector_size
= 0x20000,
465 static void xtfpga_lx200_init(MachineState
*machine
)
467 static const XtfpgaBoardDesc lx200_board
= {
468 .flash
= &lx200_flash
,
469 .sram_size
= 0x2000000,
471 xtfpga_init(&lx200_board
, machine
);
474 static const XtfpgaFlashDesc ml605_flash
= {
477 .sector_size
= 0x20000,
480 static void xtfpga_ml605_init(MachineState
*machine
)
482 static const XtfpgaBoardDesc ml605_board
= {
483 .flash
= &ml605_flash
,
484 .sram_size
= 0x2000000,
486 xtfpga_init(&ml605_board
, machine
);
489 static const XtfpgaFlashDesc kc705_flash
= {
492 .boot_base
= 0x06000000,
493 .sector_size
= 0x20000,
496 static void xtfpga_kc705_init(MachineState
*machine
)
498 static const XtfpgaBoardDesc kc705_board
= {
499 .flash
= &kc705_flash
,
500 .sram_size
= 0x2000000,
502 xtfpga_init(&kc705_board
, machine
);
505 static void xtfpga_lx60_class_init(ObjectClass
*oc
, void *data
)
507 MachineClass
*mc
= MACHINE_CLASS(oc
);
509 mc
->desc
= "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL
")";
510 mc
->init
= xtfpga_lx60_init
;
512 mc
->default_cpu_type
= XTENSA_DEFAULT_CPU_TYPE
;
515 static const TypeInfo xtfpga_lx60_type
= {
516 .name
= MACHINE_TYPE_NAME("lx60"),
517 .parent
= TYPE_MACHINE
,
518 .class_init
= xtfpga_lx60_class_init
,
521 static void xtfpga_lx200_class_init(ObjectClass
*oc
, void *data
)
523 MachineClass
*mc
= MACHINE_CLASS(oc
);
525 mc
->desc
= "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL
")";
526 mc
->init
= xtfpga_lx200_init
;
528 mc
->default_cpu_type
= XTENSA_DEFAULT_CPU_TYPE
;
531 static const TypeInfo xtfpga_lx200_type
= {
532 .name
= MACHINE_TYPE_NAME("lx200"),
533 .parent
= TYPE_MACHINE
,
534 .class_init
= xtfpga_lx200_class_init
,
537 static void xtfpga_ml605_class_init(ObjectClass
*oc
, void *data
)
539 MachineClass
*mc
= MACHINE_CLASS(oc
);
541 mc
->desc
= "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL
")";
542 mc
->init
= xtfpga_ml605_init
;
544 mc
->default_cpu_type
= XTENSA_DEFAULT_CPU_TYPE
;
547 static const TypeInfo xtfpga_ml605_type
= {
548 .name
= MACHINE_TYPE_NAME("ml605"),
549 .parent
= TYPE_MACHINE
,
550 .class_init
= xtfpga_ml605_class_init
,
553 static void xtfpga_kc705_class_init(ObjectClass
*oc
, void *data
)
555 MachineClass
*mc
= MACHINE_CLASS(oc
);
557 mc
->desc
= "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL
")";
558 mc
->init
= xtfpga_kc705_init
;
560 mc
->default_cpu_type
= XTENSA_DEFAULT_CPU_TYPE
;
563 static const TypeInfo xtfpga_kc705_type
= {
564 .name
= MACHINE_TYPE_NAME("kc705"),
565 .parent
= TYPE_MACHINE
,
566 .class_init
= xtfpga_kc705_class_init
,
569 static void xtfpga_machines_init(void)
571 type_register_static(&xtfpga_lx60_type
);
572 type_register_static(&xtfpga_lx200_type
);
573 type_register_static(&xtfpga_ml605_type
);
574 type_register_static(&xtfpga_kc705_type
);
577 type_init(xtfpga_machines_init
)