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2 * linux/include/asm-arm/arch-clps711x/hardware.h
4 * This file contains the hardware definitions of the Prospector P720T.
6 * Copyright (C) 2000 Deep Blue Solutions Ltd.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 #ifndef __ASM_ARCH_HARDWARE_H
23 #define __ASM_ARCH_HARDWARE_H
25 #include <linux/config.h>
27 #define CLPS7111_VIRT_BASE 0xff000000
28 #define CLPS7111_BASE CLPS7111_VIRT_BASE
31 * The physical addresses that the external chip select signals map to is
32 * dependent on the setting of the nMEDCHG signal on EP7211 and EP7212
33 * processors. CONFIG_EP72XX_BOOT_ROM is only available if these
34 * processors are in use.
36 #ifndef CONFIG_EP72XX_ROM_BOOT
37 #define CS0_PHYS_BASE (0x00000000)
38 #define CS1_PHYS_BASE (0x10000000)
39 #define CS2_PHYS_BASE (0x20000000)
40 #define CS3_PHYS_BASE (0x30000000)
41 #define CS4_PHYS_BASE (0x40000000)
42 #define CS5_PHYS_BASE (0x50000000)
43 #define CS6_PHYS_BASE (0x60000000)
44 #define CS7_PHYS_BASE (0x70000000)
46 #define CS0_PHYS_BASE (0x70000000)
47 #define CS1_PHYS_BASE (0x60000000)
48 #define CS2_PHYS_BASE (0x50000000)
49 #define CS3_PHYS_BASE (0x40000000)
50 #define CS4_PHYS_BASE (0x30000000)
51 #define CS5_PHYS_BASE (0x20000000)
52 #define CS6_PHYS_BASE (0x10000000)
53 #define CS7_PHYS_BASE (0x00000000)
56 #if defined (CONFIG_ARCH_EP7211)
58 #define EP7211_VIRT_BASE CLPS7111_VIRT_BASE
59 #define EP7211_BASE CLPS7111_VIRT_BASE
60 #include <asm/hardware/ep7211.h>
62 #elif defined (CONFIG_ARCH_EP7212)
64 #define EP7212_VIRT_BASE CLPS7111_VIRT_BASE
65 #define EP7212_BASE CLPS7111_VIRT_BASE
66 #include <asm/hardware/ep7212.h>
70 #define SYSPLD_VIRT_BASE 0xfe000000
71 #define SYSPLD_BASE SYSPLD_VIRT_BASE
75 #define PCIO_BASE IO_BASE
80 #if defined (CONFIG_ARCH_AUTCPU12)
82 #define CS89712_VIRT_BASE CLPS7111_VIRT_BASE
83 #define CS89712_BASE CLPS7111_VIRT_BASE
85 #include <asm/hardware/clps7111.h>
86 #include <asm/hardware/ep7212.h>
87 #include <asm/hardware/cs89712.h>
92 #if defined (CONFIG_ARCH_CDB89712)
94 #include <asm/hardware/clps7111.h>
95 #include <asm/hardware/ep7212.h>
96 #include <asm/hardware/cs89712.h>
98 /* dynamic ioremap() areas */
99 #define FLASH_START 0x00000000
100 #define FLASH_SIZE 0x800000
101 #define FLASH_WIDTH 4
103 #define SRAM_START 0x60000000
104 #define SRAM_SIZE 0xc000
107 #define BOOTROM_START 0x70000000
108 #define BOOTROM_SIZE 0x80
109 #define BOOTROM_WIDTH 4
112 /* static cdb89712_map_io() areas */
113 #define REGISTER_START 0x80000000
114 #define REGISTER_SIZE 0x4000
115 #define REGISTER_BASE 0xff000000
117 #define ETHER_START 0x20000000
118 #define ETHER_SIZE 0x1000
119 #define ETHER_BASE 0xfe000000
124 #if defined (CONFIG_ARCH_EDB7211)
127 * The extra 8 lines of the keyboard matrix are wired to chip select 3 (nCS3)
128 * and repeat across it. This is the mapping for it.
130 * In jumpered boot mode, nCS3 is mapped to 0x4000000, not 0x3000000. This
131 * was cause for much consternation and headscratching. This should probably
132 * be made a compile/run time kernel option.
134 #define EP7211_PHYS_EXTKBD CS3_PHYS_BASE /* physical */
136 #define EP7211_VIRT_EXTKBD (0xfd000000) /* virtual */
140 * The CS8900A ethernet chip has its I/O registers wired to chip select 2
141 * (nCS2). This is the mapping for it.
143 * In jumpered boot mode, nCS2 is mapped to 0x5000000, not 0x2000000. This
144 * was cause for much consternation and headscratching. This should probably
145 * be made a compile/run time kernel option.
147 #define EP7211_PHYS_CS8900A CS2_PHYS_BASE /* physical */
149 #define EP7211_VIRT_CS8900A (0xfc000000) /* virtual */
153 * The two flash banks are wired to chip selects 0 and 1. This is the mapping
156 * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
157 * in jumpered boot mode.
159 #define EP7211_PHYS_FLASH1 CS0_PHYS_BASE /* physical */
160 #define EP7211_PHYS_FLASH2 CS1_PHYS_BASE /* physical */
162 #define EP7211_VIRT_FLASH1 (0xfa000000) /* virtual */
163 #define EP7211_VIRT_FLASH2 (0xfb000000) /* virtual */
165 #endif /* CONFIG_ARCH_EDB7211 */
169 * Relevant bits in port D, which controls power to the various parts of
170 * the LCD on the EDB7211.
172 #define EDB_PD1_LCD_DC_DC_EN (1<<1)
173 #define EDB_PD2_LCDEN (1<<2)
174 #define EDB_PD3_LCDBL (1<<3)
177 #if defined (CONFIG_ARCH_CEIVA)
179 #define CEIVA_VIRT_BASE CLPS7111_VIRT_BASE
180 #define CEIVA_BASE CLPS7111_VIRT_BASE
182 #include <asm/hardware/clps7111.h>
183 #include <asm/hardware/ep7212.h>
187 * The two flash banks are wired to chip selects 0 and 1. This is the mapping
190 * nCS0 and nCS1 are at 0x70000000 and 0x60000000, respectively, when running
191 * in jumpered boot mode.
193 #define CEIVA_PHYS_FLASH1 CS0_PHYS_BASE /* physical */
194 #define CEIVA_PHYS_FLASH2 CS1_PHYS_BASE /* physical */
196 #define CEIVA_VIRT_FLASH1 (0xfa000000) /* virtual */
197 #define CEIVA_VIRT_FLASH2 (0xfb000000) /* virtual */
199 #define CEIVA_FLASH_SIZE 0x100000
200 #define CEIVA_FLASH_WIDTH 2
202 #define SRAM_START 0x60000000
203 #define SRAM_SIZE 0xc000
206 #define BOOTROM_START 0x70000000
207 #define BOOTROM_SIZE 0x80
208 #define BOOTROM_WIDTH 4
211 * SED1355 LCD controller
213 #define CEIVA_PHYS_SED1355 CS2_PHYS_BASE
214 #define CEIVA_VIRT_SED1355 (0xfc000000)
217 * Relevant bits in port D, which controls power to the various parts of
218 * the LCD on the Ceiva Photo Max, and reset to the LCD controller.
221 // Reset line to SED1355 (must be high to operate)
222 #define CEIVA_PD1_LCDRST (1<<1)
223 // LCD panel enable (set to one, to enable LCD)
224 #define CEIVA_PD4_LCDEN (1<<4)
225 // Backlight (set to one, to turn on backlight
226 #define CEIVA_PD5_LCDBL (1<<5)
229 * Relevant bits in port B, which report the status of the buttons.
233 #define CEIVA_PB4_WHT_BTN (1<<4)
235 #define CEIVA_PB0_BLK_BTN (1<<0)
236 #endif // #if defined (CONFIG_ARCH_CEIVA)
238 #if defined (CONFIG_MACH_MP1000)
240 #define MP1000_NIO_BASE 0xf9000000 /* virtual */
241 #define MP1000_NIO_START CS0_PHYS_BASE /* physical */
242 #define MP1000_NIO_SIZE 0x00400000
245 #define MP1000_DSP_BASE 0xfa000000 /* virtual */
246 #define MP1000_DSP_START CS1_PHYS_BASE /* physical */
247 #define MP1000_DSP_SIZE 0x00100000
249 /* LCD, DAA/DSP, RTC, DAA RW Reg all in CS2 */
250 #define MP1000_LIO_BASE 0xfb000000 /* virtual */
251 #define MP1000_LIO_START CS2_PHYS_BASE /* physical */
252 #define MP1000_LIO_SIZE 0x00100000
255 #define MP1000_FIO_BASE 0xfc000000 /* virtual */
256 #define MP1000_FIO_START CS3_PHYS_BASE /* physical */
257 #define MP1000_FIO_SIZE 0x00800000
260 #define MP1000_EIO_BASE 0xfd000000 /* virtual */
261 #define MP1000_EIO_START CS4_PHYS_BASE /* physical */
262 #define MP1000_EIO_SIZE 0x00100000
264 #define MP1000_LCD_OFFSET 0x00000000 /* LCD offset in CS2 */
265 #define MP1000_DDD_OFFSET 0x00001000 /* DAA/DAI/DSP sft reset offst*/
266 #define MP1000_RTC_OFFSET 0x00002000 /* RTC offset in CS2 */
267 #define MP1000_DAA_OFFSET 0x00003000 /* DAA RW reg offset in CS2 */
270 #define MP1000_IDE_BASE 0xfe000000 /* virtual */
271 #define MP1000_IDE_START CS5_PHYS_BASE /* physical */
272 #define MP1000_IDE_SIZE 0x00100000 /* actually it's only 0x1000 */
274 #define IRQ_HARDDISK IRQ_EINT2
277 * IDE registers definition
280 #define IDE_CONTROL_BASE (MP1000_IDE_BASE + 0x1000)
281 #define IDE_BASE_OFF (MP1000_IDE_BASE)
283 #define IDE_WRITE_DEVICE_DATA (IDE_BASE_OFF + 0x0)
284 #define IDE_FEATURES_REGISTER (IDE_BASE_OFF + 0x2)
285 #define IDE_SECTOR_COUNT_REGISTER (IDE_BASE_OFF + 0x4)
286 #define IDE_SECTOR_NUMBER_REGISTER (IDE_BASE_OFF + 0x6)
287 #define IDE_CYLINDER_LOW_REGISTER (IDE_BASE_OFF + 0x8)
288 #define IDE_CYLINDER_HIGH_REGISTER (IDE_BASE_OFF + 0xa)
289 #define IDE_DEVICE_HEAD_REGISTER (IDE_BASE_OFF + 0xc)
290 #define IDE_COMMAND_DATA_REGISTER (IDE_BASE_OFF + 0xe)
291 #define IDE_DEVICE_CONTROL_REGISTER (IDE_CONTROL_BASE + 0xc)
293 #define IDE_IRQ IRQ_EINT2
296 #define RTC_PORT(x) (MP1000_LIO_BASE+0x2000 + (x*2))
297 #define RTC_ALWAYS_BCD 0
300 // Definitions of the bit fields in the HwPortA register for the
303 #define HwPortAKeyboardRow1 0x00000001
304 #define HwPortAKeyboardRow2 0x00000002
305 #define HwPortAKeyboardRow3 0x00000004
306 #define HwPortAKeyboardRow4 0x00000008
307 #define HwPortAKeyboardRow5 0x00000010
308 #define HwPortAKeyboardRow6 0x00000020
309 #define HwPortALCDEnable 0x00000040
310 #define HwPortAOffhook 0x00000080
313 // Definitions of the bit fields in the HwPortB register for the
316 #define HwPortBL3Mode 0x00000001
317 #define HwPortBL3Clk 0x00000002
318 #define HwPortBSClk 0x00000001
319 #define HwPortBSData 0x00000002
320 #define HwPortBL3Data 0x00000004
321 #define HwPortBMute 0x00000008
322 #define HwPortBQD0 0x00000010
323 #define HwPortBQD1 0x00000020
324 #define HwPortBQD2 0x00000040
325 #define HwPortBQD3 0x00000080
328 // Definitions of the bit fields in the HwPortD register for the
331 #define HwPortDLED1 0x00000001
332 #define HwPortDLED2 0x00000002
333 #define HwPortDLED3 0x00000004
334 #define HwPortDLED4 0x00000008
335 #define HwPortDLED5 0x00000010
336 #define HwPortDEECS 0x00000020
337 #define HwPortBRTS 0x00000040
338 #define HwPortBRI 0x00000080
342 // Definitions of the bit fields in the HwPortE register for the
346 #define HwPortECLE 0x00000001
347 #define HwPortESepromDOut 0x00000001
348 #define HwPortEALE 0x00000002
349 #define HwPortESepromDIn 0x00000002
350 #define HwPortENANDCS 0x00000004
351 #define HwPortESepromCLK 0x00000004
353 #endif // #if defined (CONFIG_MACH_MP1000)