include/asm-arm/arch-h720x/entry-macro.S

   1 /*
   2  * include/asm-arm/arch-h720x/entry-macro.S
   3  *
   4  * Low-level IRQ helper macros for Hynix HMS720x based platforms
   5  *
   6  * This file is licensed under  the terms of the GNU General Public
   7  * License version 2. This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10
  11                 .macro  disable_fiq
  12                 .endm
  13
  14                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
  15 #if defined (CONFIG_CPU_H7201) || defined (CONFIG_CPU_H7202)
  16                 @ we could use the id register on H7202, but this is not
  17                 @ properly updated when we come back from asm_do_irq
  18                 @ without a previous return from interrupt
  19                 @ (see loops below in irq_svc, irq_usr)
  20                 @ We see unmasked pending ints only, as the masked pending ints
  21                 @ are not visible here
  22
  23                 mov     \base, #0xf0000000             @ base register
  24                 orr     \base, \base, #0x24000         @ irqbase
  25                 ldr     \irqstat, [\base, #0x04]        @ get interrupt status
  26 #if defined (CONFIG_CPU_H7201)
  27                 ldr     \tmp, =0x001fffff
  28 #else
  29                 mvn     \tmp, #0xc0000000
  30 #endif
  31                 and     \irqstat, \irqstat, \tmp        @ mask out unused ints
  32                 mov     \irqnr, #0
  33
  34                 mov     \tmp, #0xff00
  35                 orr     \tmp, \tmp, #0xff
  36                 tst     \irqstat, \tmp
  37                 addeq   \irqnr, \irqnr, #16
  38                 moveq   \irqstat, \irqstat, lsr #16
  39                 tst     \irqstat, #255
  40                 addeq   \irqnr, \irqnr, #8
  41                 moveq   \irqstat, \irqstat, lsr #8
  42                 tst     \irqstat, #15
  43                 addeq   \irqnr, \irqnr, #4
  44                 moveq   \irqstat, \irqstat, lsr #4
  45                 tst     \irqstat, #3
  46                 addeq   \irqnr, \irqnr, #2
  47                 moveq   \irqstat, \irqstat, lsr #2
  48                 tst     \irqstat, #1
  49                 addeq   \irqnr, \irqnr, #1
  50                 moveq   \irqstat, \irqstat, lsr #1
  51                 tst     \irqstat, #1                   @ bit 0 should be set
  52                 .endm
  53
  54                 .macro  irq_prio_table
  55                 .endm
  56
  57 #else
  58 #error hynix processor selection missmatch
  59 #endif
  60