include/asm-arm/arch-omap/hardware.h

   1 /*
   2  * linux/include/asm-arm/arch-omap/hardware.h
   3  *
   4  * Hardware definitions for TI OMAP processors and boards
   5  *
   6  * NOTE: Please put device driver specific defines into a separate header
   7  *       file for each driver.
   8  *
   9  * Copyright (C) 2001 RidgeRun, Inc.
  10  * Author: RidgeRun, Inc. Greg Lonnon <glonnon@ridgerun.com>
  11  *
  12  * Reorganized for Linux-2.6 by Tony Lindgren <tony@atomide.com>
  13  *                          and Dirk Behme <dirk.behme@de.bosch.com>
  14  *
  15  * This program is free software; you can redistribute it and/or modify it
  16  * under the terms of the GNU General Public License as published by the
  17  * Free Software Foundation; either version 2 of the License, or (at your
  18  * option) any later version.
  19  *
  20  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  21  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  22  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  23  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  24  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  25  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  26  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  27  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  29  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30  *
  31  * You should have received a copy of the GNU General Public License along
  32  * with this program; if not, write to the Free Software Foundation, Inc.,
  33  * 675 Mass Ave, Cambridge, MA 02139, USA.
  34  */
  35
  36 #ifndef __ASM_ARCH_OMAP_HARDWARE_H
  37 #define __ASM_ARCH_OMAP_HARDWARE_H
  38
  39 #include <asm/sizes.h>
  40 #ifndef __ASSEMBLER__
  41 #include <asm/types.h>
  42 #include <asm/arch/cpu.h>
  43 #endif
  44 #include <asm/arch/io.h>
  45 #include <asm/arch/serial.h>
  46
  47 /*
  48  * ---------------------------------------------------------------------------
  49  * Common definitions for all OMAP processors
  50  * NOTE: Put all processor or board specific parts to the special header
  51  *       files.
  52  * ---------------------------------------------------------------------------
  53  */
  54
  55 /*
  56  * ----------------------------------------------------------------------------
  57  * Timers
  58  * ----------------------------------------------------------------------------
  59  */
  60 #define OMAP_MPU_TIMER1_BASE    (0xfffec500)
  61 #define OMAP_MPU_TIMER2_BASE    (0xfffec600)
  62 #define OMAP_MPU_TIMER3_BASE    (0xfffec700)
  63 #define MPU_TIMER_FREE          (1 << 6)
  64 #define MPU_TIMER_CLOCK_ENABLE  (1 << 5)
  65 #define MPU_TIMER_AR            (1 << 1)
  66 #define MPU_TIMER_ST            (1 << 0)
  67
  68 /*
  69  * ----------------------------------------------------------------------------
  70  * Clocks
  71  * ----------------------------------------------------------------------------
  72  */
  73 #define CLKGEN_REG_BASE         (0xfffece00)
  74 #define ARM_CKCTL               (CLKGEN_REG_BASE + 0x0)
  75 #define ARM_IDLECT1             (CLKGEN_REG_BASE + 0x4)
  76 #define ARM_IDLECT2             (CLKGEN_REG_BASE + 0x8)
  77 #define ARM_EWUPCT              (CLKGEN_REG_BASE + 0xC)
  78 #define ARM_RSTCT1              (CLKGEN_REG_BASE + 0x10)
  79 #define ARM_RSTCT2              (CLKGEN_REG_BASE + 0x14)
  80 #define ARM_SYSST               (CLKGEN_REG_BASE + 0x18)
  81 #define ARM_IDLECT3             (CLKGEN_REG_BASE + 0x24)
  82
  83 #define CK_RATEF                1
  84 #define CK_IDLEF                2
  85 #define CK_ENABLEF              4
  86 #define CK_SELECTF              8
  87 #define SETARM_IDLE_SHIFT
  88
  89 /* DPLL control registers */
  90 #define DPLL_CTL                (0xfffecf00)
  91
  92 /* DSP clock control. Must use __raw_readw() and __raw_writew() with these */
  93 #define DSP_CONFIG_REG_BASE     (0xe1008000)
  94 #define DSP_CKCTL               (DSP_CONFIG_REG_BASE + 0x0)
  95 #define DSP_IDLECT1             (DSP_CONFIG_REG_BASE + 0x4)
  96 #define DSP_IDLECT2             (DSP_CONFIG_REG_BASE + 0x8)
  97 #define DSP_RSTCT2              (DSP_CONFIG_REG_BASE + 0x14)
  98
  99 /*
 100  * ---------------------------------------------------------------------------
 101  * UPLD
 102  * ---------------------------------------------------------------------------
 103  */
 104 #define ULPD_REG_BASE           (0xfffe0800)
 105 #define ULPD_IT_STATUS          (ULPD_REG_BASE + 0x14)
 106 #define ULPD_SETUP_ANALOG_CELL_3        (ULPD_REG_BASE + 0x24)
 107 #define ULPD_CLOCK_CTRL         (ULPD_REG_BASE + 0x30)
 108 #       define DIS_USB_PVCI_CLK         (1 << 5)        /* no USB/FAC synch */
 109 #       define USB_MCLK_EN              (1 << 4)        /* enable W4_USB_CLKO */
 110 #define ULPD_SOFT_REQ           (ULPD_REG_BASE + 0x34)
 111 #       define SOFT_UDC_REQ             (1 << 4)
 112 #       define SOFT_USB_CLK_REQ         (1 << 3)
 113 #       define SOFT_DPLL_REQ            (1 << 0)
 114 #define ULPD_DPLL_CTRL          (ULPD_REG_BASE + 0x3c)
 115 #define ULPD_STATUS_REQ         (ULPD_REG_BASE + 0x40)
 116 #define ULPD_APLL_CTRL          (ULPD_REG_BASE + 0x4c)
 117 #define ULPD_POWER_CTRL         (ULPD_REG_BASE + 0x50)
 118 #define ULPD_SOFT_DISABLE_REQ_REG       (ULPD_REG_BASE + 0x68)
 119 #       define DIS_MMC2_DPLL_REQ        (1 << 11)
 120 #       define DIS_MMC1_DPLL_REQ        (1 << 10)
 121 #       define DIS_UART3_DPLL_REQ       (1 << 9)
 122 #       define DIS_UART2_DPLL_REQ       (1 << 8)
 123 #       define DIS_UART1_DPLL_REQ       (1 << 7)
 124 #       define DIS_USB_HOST_DPLL_REQ    (1 << 6)
 125 #define ULPD_SDW_CLK_DIV_CTRL_SEL       (ULPD_REG_BASE + 0x74)
 126 #define ULPD_CAM_CLK_CTRL       (ULPD_REG_BASE + 0x7c)
 127
 128 /*
 129  * ---------------------------------------------------------------------------
 130  * Watchdog timer
 131  * ---------------------------------------------------------------------------
 132  */
 133
 134 /* Watchdog timer within the OMAP3.2 gigacell */
 135 #define OMAP_MPU_WATCHDOG_BASE  (0xfffec800)
 136 #define OMAP_WDT_TIMER          (OMAP_MPU_WATCHDOG_BASE + 0x0)
 137 #define OMAP_WDT_LOAD_TIM       (OMAP_MPU_WATCHDOG_BASE + 0x4)
 138 #define OMAP_WDT_READ_TIM       (OMAP_MPU_WATCHDOG_BASE + 0x4)
 139 #define OMAP_WDT_TIMER_MODE     (OMAP_MPU_WATCHDOG_BASE + 0x8)
 140
 141 /*
 142  * ---------------------------------------------------------------------------
 143  * Interrupts
 144  * ---------------------------------------------------------------------------
 145  */
 146 #ifdef CONFIG_ARCH_OMAP1
 147
 148 /*
 149  * XXX: These probably want to be moved to arch/arm/mach-omap/omap1/irq.c
 150  * or something similar.. -- PFM.
 151  */
 152
 153 #define OMAP_IH1_BASE           0xfffecb00
 154 #define OMAP_IH2_BASE           0xfffe0000
 155
 156 #define OMAP_IH1_ITR            (OMAP_IH1_BASE + 0x00)
 157 #define OMAP_IH1_MIR            (OMAP_IH1_BASE + 0x04)
 158 #define OMAP_IH1_SIR_IRQ        (OMAP_IH1_BASE + 0x10)
 159 #define OMAP_IH1_SIR_FIQ        (OMAP_IH1_BASE + 0x14)
 160 #define OMAP_IH1_CONTROL        (OMAP_IH1_BASE + 0x18)
 161 #define OMAP_IH1_ILR0           (OMAP_IH1_BASE + 0x1c)
 162 #define OMAP_IH1_ISR            (OMAP_IH1_BASE + 0x9c)
 163
 164 #define OMAP_IH2_ITR            (OMAP_IH2_BASE + 0x00)
 165 #define OMAP_IH2_MIR            (OMAP_IH2_BASE + 0x04)
 166 #define OMAP_IH2_SIR_IRQ        (OMAP_IH2_BASE + 0x10)
 167 #define OMAP_IH2_SIR_FIQ        (OMAP_IH2_BASE + 0x14)
 168 #define OMAP_IH2_CONTROL        (OMAP_IH2_BASE + 0x18)
 169 #define OMAP_IH2_ILR0           (OMAP_IH2_BASE + 0x1c)
 170 #define OMAP_IH2_ISR            (OMAP_IH2_BASE + 0x9c)
 171
 172 #define IRQ_ITR_REG_OFFSET      0x00
 173 #define IRQ_MIR_REG_OFFSET      0x04
 174 #define IRQ_SIR_IRQ_REG_OFFSET  0x10
 175 #define IRQ_SIR_FIQ_REG_OFFSET  0x14
 176 #define IRQ_CONTROL_REG_OFFSET  0x18
 177 #define IRQ_ISR_REG_OFFSET      0x9c
 178 #define IRQ_ILR0_REG_OFFSET     0x1c
 179 #define IRQ_GMR_REG_OFFSET      0xa0
 180
 181 #endif
 182
 183 /*
 184  * ----------------------------------------------------------------------------
 185  * System control registers
 186  * ----------------------------------------------------------------------------
 187  */
 188 #define MOD_CONF_CTRL_0         0xfffe1080
 189 #define MOD_CONF_CTRL_1         0xfffe1110
 190
 191 /*
 192  * ----------------------------------------------------------------------------
 193  * Pin multiplexing registers
 194  * ----------------------------------------------------------------------------
 195  */
 196 #define FUNC_MUX_CTRL_0         0xfffe1000
 197 #define FUNC_MUX_CTRL_1         0xfffe1004
 198 #define FUNC_MUX_CTRL_2         0xfffe1008
 199 #define COMP_MODE_CTRL_0        0xfffe100c
 200 #define FUNC_MUX_CTRL_3         0xfffe1010
 201 #define FUNC_MUX_CTRL_4         0xfffe1014
 202 #define FUNC_MUX_CTRL_5         0xfffe1018
 203 #define FUNC_MUX_CTRL_6         0xfffe101C
 204 #define FUNC_MUX_CTRL_7         0xfffe1020
 205 #define FUNC_MUX_CTRL_8         0xfffe1024
 206 #define FUNC_MUX_CTRL_9         0xfffe1028
 207 #define FUNC_MUX_CTRL_A         0xfffe102C
 208 #define FUNC_MUX_CTRL_B         0xfffe1030
 209 #define FUNC_MUX_CTRL_C         0xfffe1034
 210 #define FUNC_MUX_CTRL_D         0xfffe1038
 211 #define PULL_DWN_CTRL_0         0xfffe1040
 212 #define PULL_DWN_CTRL_1         0xfffe1044
 213 #define PULL_DWN_CTRL_2         0xfffe1048
 214 #define PULL_DWN_CTRL_3         0xfffe104c
 215 #define PULL_DWN_CTRL_4         0xfffe10ac
 216
 217 /* OMAP-1610 specific multiplexing registers */
 218 #define FUNC_MUX_CTRL_E         0xfffe1090
 219 #define FUNC_MUX_CTRL_F         0xfffe1094
 220 #define FUNC_MUX_CTRL_10        0xfffe1098
 221 #define FUNC_MUX_CTRL_11        0xfffe109c
 222 #define FUNC_MUX_CTRL_12        0xfffe10a0
 223 #define PU_PD_SEL_0             0xfffe10b4
 224 #define PU_PD_SEL_1             0xfffe10b8
 225 #define PU_PD_SEL_2             0xfffe10bc
 226 #define PU_PD_SEL_3             0xfffe10c0
 227 #define PU_PD_SEL_4             0xfffe10c4
 228
 229 /* Timer32K for 1610 and 1710*/
 230 #define OMAP_TIMER32K_BASE      0xFFFBC400
 231
 232 /*
 233  * ---------------------------------------------------------------------------
 234  * TIPB bus interface
 235  * ---------------------------------------------------------------------------
 236  */
 237 #define TIPB_PUBLIC_CNTL_BASE           0xfffed300
 238 #define MPU_PUBLIC_TIPB_CNTL            (TIPB_PUBLIC_CNTL_BASE + 0x8)
 239 #define TIPB_PRIVATE_CNTL_BASE          0xfffeca00
 240 #define MPU_PRIVATE_TIPB_CNTL           (TIPB_PRIVATE_CNTL_BASE + 0x8)
 241
 242 /*
 243  * ----------------------------------------------------------------------------
 244  * MPUI interface
 245  * ----------------------------------------------------------------------------
 246  */
 247 #define MPUI_BASE                       (0xfffec900)
 248 #define MPUI_CTRL                       (MPUI_BASE + 0x0)
 249 #define MPUI_DEBUG_ADDR                 (MPUI_BASE + 0x4)
 250 #define MPUI_DEBUG_DATA                 (MPUI_BASE + 0x8)
 251 #define MPUI_DEBUG_FLAG                 (MPUI_BASE + 0xc)
 252 #define MPUI_STATUS_REG                 (MPUI_BASE + 0x10)
 253 #define MPUI_DSP_STATUS                 (MPUI_BASE + 0x14)
 254 #define MPUI_DSP_BOOT_CONFIG            (MPUI_BASE + 0x18)
 255 #define MPUI_DSP_API_CONFIG             (MPUI_BASE + 0x1c)
 256
 257 /*
 258  * ----------------------------------------------------------------------------
 259  * LED Pulse Generator
 260  * ----------------------------------------------------------------------------
 261  */
 262 #define OMAP_LPG1_BASE                  0xfffbd000
 263 #define OMAP_LPG2_BASE                  0xfffbd800
 264 #define OMAP_LPG1_LCR                   (OMAP_LPG1_BASE + 0x00)
 265 #define OMAP_LPG1_PMR                   (OMAP_LPG1_BASE + 0x04)
 266 #define OMAP_LPG2_LCR                   (OMAP_LPG2_BASE + 0x00)
 267 #define OMAP_LPG2_PMR                   (OMAP_LPG2_BASE + 0x04)
 268
 269 /*
 270  * ---------------------------------------------------------------------------
 271  * Processor specific defines
 272  * ---------------------------------------------------------------------------
 273  */
 274
 275 #include "omap730.h"
 276 #include "omap1510.h"
 277 #include "omap24xx.h"
 278 #include "omap16xx.h"
 279
 280 #ifndef __ASSEMBLER__
 281
 282 /*
 283  * ---------------------------------------------------------------------------
 284  * Board specific defines
 285  * ---------------------------------------------------------------------------
 286  */
 287
 288 #ifdef CONFIG_MACH_OMAP_INNOVATOR
 289 #include "board-innovator.h"
 290 #endif
 291
 292 #ifdef CONFIG_MACH_OMAP_H2
 293 #include "board-h2.h"
 294 #endif
 295
 296 #ifdef CONFIG_MACH_OMAP_PERSEUS2
 297 #include "board-perseus2.h"
 298 #endif
 299
 300 #ifdef CONFIG_MACH_OMAP_FSAMPLE
 301 #include "board-fsample.h"
 302 #endif
 303
 304 #ifdef CONFIG_MACH_OMAP_H3
 305 #include "board-h3.h"
 306 #endif
 307
 308 #ifdef CONFIG_MACH_OMAP_H4
 309 #include "board-h4.h"
 310 #endif
 311
 312 #ifdef CONFIG_MACH_OMAP_APOLLON
 313 #include "board-apollon.h"
 314 #endif
 315
 316 #ifdef CONFIG_MACH_OMAP_OSK
 317 #include "board-osk.h"
 318 #endif
 319
 320 #ifdef CONFIG_MACH_VOICEBLUE
 321 #include "board-voiceblue.h"
 322 #endif
 323
 324 #endif /* !__ASSEMBLER__ */
 325
 326 #endif  /* __ASM_ARCH_OMAP_HARDWARE_H */