include/asm-arm/arch-omap/io.h

   1 /*
   2  * linux/include/asm-arm/arch-omap/io.h
   3  *
   4  * IO definitions for TI OMAP processors and boards
   5  *
   6  * Copied from linux/include/asm-arm/arch-sa1100/io.h
   7  * Copyright (C) 1997-1999 Russell King
   8  *
   9  * This program is free software; you can redistribute it and/or modify it
  10  * under the terms of the GNU General Public License as published by the
  11  * Free Software Foundation; either version 2 of the License, or (at your
  12  * option) any later version.
  13  *
  14  * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
  15  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
  16  * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
  17  * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
  18  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  19  * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
  20  * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
  21  * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  22  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  23  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  24  *
  25  * You should have received a copy of the GNU General Public License along
  26  * with this program; if not, write to the Free Software Foundation, Inc.,
  27  * 675 Mass Ave, Cambridge, MA 02139, USA.
  28  *
  29  * Modifications:
  30  *  06-12-1997  RMK     Created.
  31  *  07-04-1999  RMK     Major cleanup
  32  */
  33
  34 #ifndef __ASM_ARM_ARCH_IO_H
  35 #define __ASM_ARM_ARCH_IO_H
  36
  37 #include <asm/hardware.h>
  38
  39 #define IO_SPACE_LIMIT 0xffffffff
  40
  41 /*
  42  * We don't actually have real ISA nor PCI buses, but there is so many
  43  * drivers out there that might just work if we fake them...
  44  */
  45 #define __io(a)                 ((void __iomem *)(PCIO_BASE + (a)))
  46 #define __mem_pci(a)            (a)
  47
  48 /*
  49  * ----------------------------------------------------------------------------
  50  * I/O mapping
  51  * ----------------------------------------------------------------------------
  52  */
  53
  54 #define PCIO_BASE       0
  55
  56 #if defined(CONFIG_ARCH_OMAP1)
  57
  58 #define IO_PHYS         0xFFFB0000
  59 #define IO_OFFSET       0x01000000      /* Virtual IO = 0xfefb0000 */
  60 #define IO_SIZE         0x40000
  61 #define IO_VIRT         (IO_PHYS - IO_OFFSET)
  62 #define IO_ADDRESS(pa)  ((pa) - IO_OFFSET)
  63 #define io_p2v(pa)      ((pa) - IO_OFFSET)
  64 #define io_v2p(va)      ((va) + IO_OFFSET)
  65
  66 #elif defined(CONFIG_ARCH_OMAP2)
  67
  68 /* We map both L3 and L4 on OMAP2 */
  69 #define L3_24XX_PHYS    L3_24XX_BASE    /* 0x68000000 */
  70 #define L3_24XX_VIRT    0xf8000000
  71 #define L3_24XX_SIZE    SZ_1M           /* 44kB of 128MB used, want 1MB sect */
  72 #define L4_24XX_PHYS    L4_24XX_BASE    /* 0x48000000 */
  73 #define L4_24XX_VIRT    0xd8000000
  74 #define L4_24XX_SIZE    SZ_1M           /* 1MB of 128MB used, want 1MB sect */
  75
  76 #ifdef CONFIG_ARCH_OMAP2430
  77 #define L4_WK_243X_PHYS         L4_WK_243X_BASE         /* 0x49000000 */
  78 #define L4_WK_243X_VIRT         0xd9000000
  79 #define L4_WK_243X_SIZE         SZ_1M
  80 #define OMAP243X_GPMC_PHYS      OMAP243X_GPMC_BASE      /* 0x49000000 */
  81 #define OMAP243X_GPMC_VIRT      0xFE000000
  82 #define OMAP243X_GPMC_SIZE      SZ_1M
  83 #define OMAP243X_SDRC_PHYS      OMAP243X_SDRC_BASE
  84 #define OMAP243X_SDRC_VIRT      0xFD000000
  85 #define OMAP243X_SDRC_SIZE      SZ_1M
  86 #define OMAP243X_SMS_PHYS       OMAP243X_SMS_BASE
  87 #define OMAP243X_SMS_VIRT       0xFC000000
  88 #define OMAP243X_SMS_SIZE       SZ_1M
  89
  90 #endif
  91
  92 #define IO_OFFSET       0x90000000
  93 #define IO_ADDRESS(pa)  ((pa) + IO_OFFSET)      /* Works for L3 and L4 */
  94 #define io_p2v(pa)      ((pa) + IO_OFFSET)      /* Works for L3 and L4 */
  95 #define io_v2p(va)      ((va) - IO_OFFSET)      /* Works for L3 and L4 */
  96
  97 /* DSP */
  98 #define DSP_MEM_24XX_PHYS       OMAP2420_DSP_MEM_BASE   /* 0x58000000 */
  99 #define DSP_MEM_24XX_VIRT       0xe0000000
 100 #define DSP_MEM_24XX_SIZE       0x28000
 101 #define DSP_IPI_24XX_PHYS       OMAP2420_DSP_IPI_BASE   /* 0x59000000 */
 102 #define DSP_IPI_24XX_VIRT       0xe1000000
 103 #define DSP_IPI_24XX_SIZE       SZ_4K
 104 #define DSP_MMU_24XX_PHYS       OMAP2420_DSP_MMU_BASE   /* 0x5a000000 */
 105 #define DSP_MMU_24XX_VIRT       0xe2000000
 106 #define DSP_MMU_24XX_SIZE       SZ_4K
 107
 108 #elif defined(CONFIG_ARCH_OMAP3)
 109
 110 /* We map both L3 and L4 on OMAP3 */
 111 #define L3_34XX_PHYS            L3_34XX_BASE    /* 0x68000000 */
 112 #define L3_34XX_VIRT            0xf8000000
 113 #define L3_34XX_SIZE            SZ_1M   /* 44kB of 128MB used, want 1MB sect */
 114
 115 #define L4_34XX_PHYS            L4_34XX_BASE    /* 0x48000000 */
 116 #define L4_34XX_VIRT            0xd8000000
 117 #define L4_34XX_SIZE            SZ_4M   /* 1MB of 128MB used, want 1MB sect */
 118
 119 /*
 120  * Need to look at the Size 4M for L4.
 121  * VPOM3430 was not working for Int controller
 122  */
 123
 124 #define L4_WK_34XX_PHYS         L4_WK_34XX_BASE /* 0x48300000 */
 125 #define L4_WK_34XX_VIRT         0xd8300000
 126 #define L4_WK_34XX_SIZE         SZ_1M
 127
 128 #define L4_PER_34XX_PHYS        L4_PER_34XX_BASE /* 0x49000000 */
 129 #define L4_PER_34XX_VIRT        0xd9000000
 130 #define L4_PER_34XX_SIZE        SZ_1M
 131
 132 #define L4_EMU_34XX_PHYS        L4_EMU_34XX_BASE /* 0x54000000 */
 133 #define L4_EMU_34XX_VIRT        0xe4000000
 134 #define L4_EMU_34XX_SIZE        SZ_64M
 135
 136 #define OMAP34XX_GPMC_PHYS      OMAP34XX_GPMC_BASE /* 0x6E000000 */
 137 #define OMAP34XX_GPMC_VIRT      0xFE000000
 138 #define OMAP34XX_GPMC_SIZE      SZ_1M
 139
 140 #define OMAP343X_SMS_PHYS       OMAP343X_SMS_BASE /* 0x6C000000 */
 141 #define OMAP343X_SMS_VIRT       0xFC000000
 142 #define OMAP343X_SMS_SIZE       SZ_1M
 143
 144 #define OMAP343X_SDRC_PHYS      OMAP343X_SDRC_BASE /* 0x6D000000 */
 145 #define OMAP343X_SDRC_VIRT      0xFD000000
 146 #define OMAP343X_SDRC_SIZE      SZ_1M
 147
 148
 149 #define IO_OFFSET               0x90000000
 150 #define IO_ADDRESS(pa)          ((pa) + IO_OFFSET)/* Works for L3 and L4 */
 151 #define io_p2v(pa)              ((pa) + IO_OFFSET)/* Works for L3 and L4 */
 152 #define io_v2p(va)              ((va) - IO_OFFSET)/* Works for L3 and L4 */
 153
 154 /* DSP */
 155 #define DSP_MEM_34XX_PHYS       OMAP34XX_DSP_MEM_BASE   /* 0x58000000 */
 156 #define DSP_MEM_34XX_VIRT       0xe0000000
 157 #define DSP_MEM_34XX_SIZE       0x28000
 158 #define DSP_IPI_34XX_PHYS       OMAP34XX_DSP_IPI_BASE   /* 0x59000000 */
 159 #define DSP_IPI_34XX_VIRT       0xe1000000
 160 #define DSP_IPI_34XX_SIZE       SZ_4K
 161 #define DSP_MMU_34XX_PHYS       OMAP34XX_DSP_MMU_BASE   /* 0x5a000000 */
 162 #define DSP_MMU_34XX_VIRT       0xe2000000
 163 #define DSP_MMU_34XX_SIZE       SZ_4K
 164
 165 #endif
 166
 167 #ifndef __ASSEMBLER__
 168
 169 /*
 170  * Functions to access the OMAP IO region
 171  *
 172  * NOTE: - Use omap_read/write[bwl] for physical register addresses
 173  *       - Use __raw_read/write[bwl]() for virtual register addresses
 174  *       - Use IO_ADDRESS(phys_addr) to convert registers to virtual addresses
 175  *       - DO NOT use hardcoded virtual addresses to allow changing the
 176  *         IO address space again if needed
 177  */
 178 #define omap_readb(a)           (*(volatile unsigned char  *)IO_ADDRESS(a))
 179 #define omap_readw(a)           (*(volatile unsigned short *)IO_ADDRESS(a))
 180 #define omap_readl(a)           (*(volatile unsigned int   *)IO_ADDRESS(a))
 181
 182 #define omap_writeb(v,a)        (*(volatile unsigned char  *)IO_ADDRESS(a) = (v))
 183 #define omap_writew(v,a)        (*(volatile unsigned short *)IO_ADDRESS(a) = (v))
 184 #define omap_writel(v,a)        (*(volatile unsigned int   *)IO_ADDRESS(a) = (v))
 185
 186 /* 16 bit uses LDRH/STRH, base +/- offset_8 */
 187 typedef struct { volatile u16 offset[256]; } __regbase16;
 188 #define __REGV16(vaddr)         ((__regbase16 *)((vaddr)&~0xff)) \
 189                                         ->offset[((vaddr)&0xff)>>1]
 190 #define __REG16(paddr)          __REGV16(io_p2v(paddr))
 191
 192 /* 8/32 bit uses LDR/STR, base +/- offset_12 */
 193 typedef struct { volatile u8 offset[4096]; } __regbase8;
 194 #define __REGV8(vaddr)          ((__regbase8  *)((vaddr)&~4095)) \
 195                                         ->offset[((vaddr)&4095)>>0]
 196 #define __REG8(paddr)           __REGV8(io_p2v(paddr))
 197
 198 typedef struct { volatile u32 offset[4096]; } __regbase32;
 199 #define __REGV32(vaddr)         ((__regbase32 *)((vaddr)&~4095)) \
 200                                         ->offset[((vaddr)&4095)>>2]
 201 #define __REG32(paddr)          __REGV32(io_p2v(paddr))
 202
 203 extern void omap1_map_common_io(void);
 204 extern void omap1_init_common_hw(void);
 205
 206 extern void omap2_map_common_io(void);
 207 extern void omap2_init_common_hw(void);
 208
 209 #else
 210
 211 #define __REG8(paddr)           io_p2v(paddr)
 212 #define __REG16(paddr)          io_p2v(paddr)
 213 #define __REG32(paddr)          io_p2v(paddr)
 214
 215 #endif
 216
 217 #endif