include/asm-arm/arch-realview/entry-macro.S

   1 /*
   2  * include/asm-arm/arch-realview/entry-macro.S
   3  *
   4  * Low-level IRQ helper macros for RealView platforms
   5  *
   6  * This file is licensed under  the terms of the GNU General Public
   7  * License version 2. This program is licensed "as is" without any
   8  * warranty of any kind, whether express or implied.
   9  */
  10 #include <asm/hardware.h>
  11 #include <asm/hardware/gic.h>
  12
  13                 .macro  disable_fiq
  14                 .endm
  15
  16                 /*
  17                  * The interrupt numbering scheme is defined in the
  18                  * interrupt controller spec.  To wit:
  19                  *
  20                  * Interrupts 0-15 are IPI
  21                  * 16-28 are reserved
  22                  * 29-31 are local.  We allow 30 to be used for the watchdog.
  23                  * 32-1020 are global
  24                  * 1021-1022 are reserved
  25                  * 1023 is "spurious" (no interrupt)
  26                  *
  27                  * For now, we ignore all local interrupts so only return an interrupt if it's
  28                  * between 30 and 1020.  The test_for_ipi routine below will pick up on IPIs.
  29                  *
  30                  * A simple read from the controller will tell us the number of the highest
  31                  * priority enabled interrupt.  We then just need to check whether it is in the
  32                  * valid range for an IRQ (30-1020 inclusive).
  33                  */
  34
  35                 .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
  36
  37                 ldr     \base, =IO_ADDRESS(REALVIEW_GIC_CPU_BASE)
  38                 ldr     \irqstat, [\base, #GIC_CPU_INTACK] /* bits 12-10 = src CPU, 9-0 = int # */
  39
  40                 ldr     \tmp, =1021
  41
  42                 bic     \irqnr, \irqstat, #0x1c00
  43
  44                 cmp     \irqnr, #29
  45                 cmpcc   \irqnr, \irqnr
  46                 cmpne   \irqnr, \tmp
  47                 cmpcs   \irqnr, \irqnr
  48
  49                 .endm
  50
  51                 /* We assume that irqstat (the raw value of the IRQ acknowledge
  52                  * register) is preserved from the macro above.
  53                  * If there is an IPI, we immediately signal end of interrupt on the
  54                  * controller, since this requires the original irqstat value which
  55                  * we won't easily be able to recreate later.
  56                  */
  57
  58                 .macro test_for_ipi, irqnr, irqstat, base, tmp
  59                 bic     \irqnr, \irqstat, #0x1c00
  60                 cmp     \irqnr, #16
  61                 strcc   \irqstat, [\base, #GIC_CPU_EOI]
  62                 cmpcs   \irqnr, \irqnr
  63                 .endm
  64
  65                 /* As above, this assumes that irqstat and base are preserved.. */
  66
  67                 .macro test_for_ltirq, irqnr, irqstat, base, tmp
  68                 bic     \irqnr, \irqstat, #0x1c00
  69                 mov     \tmp, #0
  70                 cmp     \irqnr, #29
  71                 moveq   \tmp, #1
  72                 streq   \irqstat, [\base, #GIC_CPU_EOI]
  73                 cmp     \tmp, #0
  74                 .endm