include/asm-arm/tlbflush.h

   1 /*
   2  *  linux/include/asm-arm/tlbflush.h
   3  *
   4  *  Copyright (C) 1999-2003 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  */
  10 #ifndef _ASMARM_TLBFLUSH_H
  11 #define _ASMARM_TLBFLUSH_H
  12
  13
  14 #ifndef CONFIG_MMU
  15
  16 #define tlb_flush(tlb)  ((void) tlb)
  17
  18 #else /* CONFIG_MMU */
  19
  20 #include <asm/glue.h>
  21
  22 #define TLB_V3_PAGE     (1 << 0)
  23 #define TLB_V4_U_PAGE   (1 << 1)
  24 #define TLB_V4_D_PAGE   (1 << 2)
  25 #define TLB_V4_I_PAGE   (1 << 3)
  26 #define TLB_V6_U_PAGE   (1 << 4)
  27 #define TLB_V6_D_PAGE   (1 << 5)
  28 #define TLB_V6_I_PAGE   (1 << 6)
  29
  30 #define TLB_V3_FULL     (1 << 8)
  31 #define TLB_V4_U_FULL   (1 << 9)
  32 #define TLB_V4_D_FULL   (1 << 10)
  33 #define TLB_V4_I_FULL   (1 << 11)
  34 #define TLB_V6_U_FULL   (1 << 12)
  35 #define TLB_V6_D_FULL   (1 << 13)
  36 #define TLB_V6_I_FULL   (1 << 14)
  37
  38 #define TLB_V6_U_ASID   (1 << 16)
  39 #define TLB_V6_D_ASID   (1 << 17)
  40 #define TLB_V6_I_ASID   (1 << 18)
  41
  42 #define TLB_DCLEAN      (1 << 30)
  43 #define TLB_WB          (1 << 31)
  44
  45 /*
  46  *      MMU TLB Model
  47  *      =============
  48  *
  49  *      We have the following to choose from:
  50  *        v3    - ARMv3
  51  *        v4    - ARMv4 without write buffer
  52  *        v4wb  - ARMv4 with write buffer without I TLB flush entry instruction
  53  *        v4wbi - ARMv4 with write buffer with I TLB flush entry instruction
  54  *        v6wbi - ARMv6 with write buffer with I TLB flush entry instruction
  55  */
  56 #undef _TLB
  57 #undef MULTI_TLB
  58
  59 #define v3_tlb_flags    (TLB_V3_FULL | TLB_V3_PAGE)
  60
  61 #ifdef CONFIG_CPU_TLB_V3
  62 # define v3_possible_flags      v3_tlb_flags
  63 # define v3_always_flags        v3_tlb_flags
  64 # ifdef _TLB
  65 #  define MULTI_TLB 1
  66 # else
  67 #  define _TLB v3
  68 # endif
  69 #else
  70 # define v3_possible_flags      0
  71 # define v3_always_flags        (-1UL)
  72 #endif
  73
  74 #define v4_tlb_flags    (TLB_V4_U_FULL | TLB_V4_U_PAGE)
  75
  76 #ifdef CONFIG_CPU_TLB_V4WT
  77 # define v4_possible_flags      v4_tlb_flags
  78 # define v4_always_flags        v4_tlb_flags
  79 # ifdef _TLB
  80 #  define MULTI_TLB 1
  81 # else
  82 #  define _TLB v4
  83 # endif
  84 #else
  85 # define v4_possible_flags      0
  86 # define v4_always_flags        (-1UL)
  87 #endif
  88
  89 #define v4wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \
  90                          TLB_V4_I_FULL | TLB_V4_D_FULL | \
  91                          TLB_V4_I_PAGE | TLB_V4_D_PAGE)
  92
  93 #ifdef CONFIG_CPU_TLB_V4WBI
  94 # define v4wbi_possible_flags   v4wbi_tlb_flags
  95 # define v4wbi_always_flags     v4wbi_tlb_flags
  96 # ifdef _TLB
  97 #  define MULTI_TLB 1
  98 # else
  99 #  define _TLB v4wbi
 100 # endif
 101 #else
 102 # define v4wbi_possible_flags   0
 103 # define v4wbi_always_flags     (-1UL)
 104 #endif
 105
 106 #define v4wb_tlb_flags  (TLB_WB | TLB_DCLEAN | \
 107                          TLB_V4_I_FULL | TLB_V4_D_FULL | \
 108                          TLB_V4_D_PAGE)
 109
 110 #ifdef CONFIG_CPU_TLB_V4WB
 111 # define v4wb_possible_flags    v4wb_tlb_flags
 112 # define v4wb_always_flags      v4wb_tlb_flags
 113 # ifdef _TLB
 114 #  define MULTI_TLB 1
 115 # else
 116 #  define _TLB v4wb
 117 # endif
 118 #else
 119 # define v4wb_possible_flags    0
 120 # define v4wb_always_flags      (-1UL)
 121 #endif
 122
 123 #define v6wbi_tlb_flags (TLB_WB | TLB_DCLEAN | \
 124                          TLB_V6_I_FULL | TLB_V6_D_FULL | \
 125                          TLB_V6_I_PAGE | TLB_V6_D_PAGE | \
 126                          TLB_V6_I_ASID | TLB_V6_D_ASID)
 127
 128 #ifdef CONFIG_CPU_TLB_V6
 129 # define v6wbi_possible_flags   v6wbi_tlb_flags
 130 # define v6wbi_always_flags     v6wbi_tlb_flags
 131 # ifdef _TLB
 132 #  define MULTI_TLB 1
 133 # else
 134 #  define _TLB v6wbi
 135 # endif
 136 #else
 137 # define v6wbi_possible_flags   0
 138 # define v6wbi_always_flags     (-1UL)
 139 #endif
 140
 141 #ifndef _TLB
 142 #error Unknown TLB model
 143 #endif
 144
 145 #ifndef __ASSEMBLY__
 146
 147 #include <linux/sched.h>
 148
 149 struct cpu_tlb_fns {
 150         void (*flush_user_range)(unsigned long, unsigned long, struct vm_area_struct *);
 151         void (*flush_kern_range)(unsigned long, unsigned long);
 152         unsigned long tlb_flags;
 153 };
 154
 155 /*
 156  * Select the calling method
 157  */
 158 #ifdef MULTI_TLB
 159
 160 #define __cpu_flush_user_tlb_range      cpu_tlb.flush_user_range
 161 #define __cpu_flush_kern_tlb_range      cpu_tlb.flush_kern_range
 162
 163 #else
 164
 165 #define __cpu_flush_user_tlb_range      __glue(_TLB,_flush_user_tlb_range)
 166 #define __cpu_flush_kern_tlb_range      __glue(_TLB,_flush_kern_tlb_range)
 167
 168 extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
 169 extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);
 170
 171 #endif
 172
 173 extern struct cpu_tlb_fns cpu_tlb;
 174
 175 #define __cpu_tlb_flags                 cpu_tlb.tlb_flags
 176
 177 /*
 178  *      TLB Management
 179  *      ==============
 180  *
 181  *      The arch/arm/mm/tlb-*.S files implement these methods.
 182  *
 183  *      The TLB specific code is expected to perform whatever tests it
 184  *      needs to determine if it should invalidate the TLB for each
 185  *      call.  Start addresses are inclusive and end addresses are
 186  *      exclusive; it is safe to round these addresses down.
 187  *
 188  *      flush_tlb_all()
 189  *
 190  *              Invalidate the entire TLB.
 191  *
 192  *      flush_tlb_mm(mm)
 193  *
 194  *              Invalidate all TLB entries in a particular address
 195  *              space.
 196  *              - mm    - mm_struct describing address space
 197  *
 198  *      flush_tlb_range(mm,start,end)
 199  *
 200  *              Invalidate a range of TLB entries in the specified
 201  *              address space.
 202  *              - mm    - mm_struct describing address space
 203  *              - start - start address (may not be aligned)
 204  *              - end   - end address (exclusive, may not be aligned)
 205  *
 206  *      flush_tlb_page(vaddr,vma)
 207  *
 208  *              Invalidate the specified page in the specified address range.
 209  *              - vaddr - virtual address (may not be aligned)
 210  *              - vma   - vma_struct describing address range
 211  *
 212  *      flush_kern_tlb_page(kaddr)
 213  *
 214  *              Invalidate the TLB entry for the specified page.  The address
 215  *              will be in the kernels virtual memory space.  Current uses
 216  *              only require the D-TLB to be invalidated.
 217  *              - kaddr - Kernel virtual memory address
 218  */
 219
 220 /*
 221  * We optimise the code below by:
 222  *  - building a set of TLB flags that might be set in __cpu_tlb_flags
 223  *  - building a set of TLB flags that will always be set in __cpu_tlb_flags
 224  *  - if we're going to need __cpu_tlb_flags, access it once and only once
 225  *
 226  * This allows us to build optimal assembly for the single-CPU type case,
 227  * and as close to optimal given the compiler constrants for multi-CPU
 228  * case.  We could do better for the multi-CPU case if the compiler
 229  * implemented the "%?" method, but this has been discontinued due to too
 230  * many people getting it wrong.
 231  */
 232 #define possible_tlb_flags      (v3_possible_flags | \
 233                                  v4_possible_flags | \
 234                                  v4wbi_possible_flags | \
 235                                  v4wb_possible_flags | \
 236                                  v6wbi_possible_flags)
 237
 238 #define always_tlb_flags        (v3_always_flags & \
 239                                  v4_always_flags & \
 240                                  v4wbi_always_flags & \
 241                                  v4wb_always_flags & \
 242                                  v6wbi_always_flags)
 243
 244 #define tlb_flag(f)     ((always_tlb_flags & (f)) || (__tlb_flag & possible_tlb_flags & (f)))
 245
 246 static inline void local_flush_tlb_all(void)
 247 {
 248         const int zero = 0;
 249         const unsigned int __tlb_flag = __cpu_tlb_flags;
 250
 251         if (tlb_flag(TLB_WB))
 252                 dsb();
 253
 254         if (tlb_flag(TLB_V3_FULL))
 255                 asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
 256         if (tlb_flag(TLB_V4_U_FULL | TLB_V6_U_FULL))
 257                 asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
 258         if (tlb_flag(TLB_V4_D_FULL | TLB_V6_D_FULL))
 259                 asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
 260         if (tlb_flag(TLB_V4_I_FULL | TLB_V6_I_FULL))
 261                 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
 262
 263         if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
 264                      TLB_V6_I_PAGE | TLB_V6_D_PAGE |
 265                      TLB_V6_I_ASID | TLB_V6_D_ASID)) {
 266                 /* flush the branch target cache */
 267                 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
 268                 dsb();
 269                 isb();
 270         }
 271 }
 272
 273 static inline void local_flush_tlb_mm(struct mm_struct *mm)
 274 {
 275         const int zero = 0;
 276         const int asid = ASID(mm);
 277         const unsigned int __tlb_flag = __cpu_tlb_flags;
 278
 279         if (tlb_flag(TLB_WB))
 280                 dsb();
 281
 282         if (cpu_isset(smp_processor_id(), mm->cpu_vm_mask)) {
 283                 if (tlb_flag(TLB_V3_FULL))
 284                         asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (zero) : "cc");
 285                 if (tlb_flag(TLB_V4_U_FULL))
 286                         asm("mcr p15, 0, %0, c8, c7, 0" : : "r" (zero) : "cc");
 287                 if (tlb_flag(TLB_V4_D_FULL))
 288                         asm("mcr p15, 0, %0, c8, c6, 0" : : "r" (zero) : "cc");
 289                 if (tlb_flag(TLB_V4_I_FULL))
 290                         asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
 291         }
 292
 293         if (tlb_flag(TLB_V6_U_ASID))
 294                 asm("mcr p15, 0, %0, c8, c7, 2" : : "r" (asid) : "cc");
 295         if (tlb_flag(TLB_V6_D_ASID))
 296                 asm("mcr p15, 0, %0, c8, c6, 2" : : "r" (asid) : "cc");
 297         if (tlb_flag(TLB_V6_I_ASID))
 298                 asm("mcr p15, 0, %0, c8, c5, 2" : : "r" (asid) : "cc");
 299
 300         if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
 301                      TLB_V6_I_PAGE | TLB_V6_D_PAGE |
 302                      TLB_V6_I_ASID | TLB_V6_D_ASID)) {
 303                 /* flush the branch target cache */
 304                 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
 305                 dsb();
 306         }
 307 }
 308
 309 static inline void
 310 local_flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr)
 311 {
 312         const int zero = 0;
 313         const unsigned int __tlb_flag = __cpu_tlb_flags;
 314
 315         uaddr = (uaddr & PAGE_MASK) | ASID(vma->vm_mm);
 316
 317         if (tlb_flag(TLB_WB))
 318                 dsb();
 319
 320         if (cpu_isset(smp_processor_id(), vma->vm_mm->cpu_vm_mask)) {
 321                 if (tlb_flag(TLB_V3_PAGE))
 322                         asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (uaddr) : "cc");
 323                 if (tlb_flag(TLB_V4_U_PAGE))
 324                         asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
 325                 if (tlb_flag(TLB_V4_D_PAGE))
 326                         asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
 327                 if (tlb_flag(TLB_V4_I_PAGE))
 328                         asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
 329                 if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
 330                         asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
 331         }
 332
 333         if (tlb_flag(TLB_V6_U_PAGE))
 334                 asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (uaddr) : "cc");
 335         if (tlb_flag(TLB_V6_D_PAGE))
 336                 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (uaddr) : "cc");
 337         if (tlb_flag(TLB_V6_I_PAGE))
 338                 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (uaddr) : "cc");
 339
 340         if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
 341                      TLB_V6_I_PAGE | TLB_V6_D_PAGE |
 342                      TLB_V6_I_ASID | TLB_V6_D_ASID)) {
 343                 /* flush the branch target cache */
 344                 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
 345                 dsb();
 346         }
 347 }
 348
 349 static inline void local_flush_tlb_kernel_page(unsigned long kaddr)
 350 {
 351         const int zero = 0;
 352         const unsigned int __tlb_flag = __cpu_tlb_flags;
 353
 354         kaddr &= PAGE_MASK;
 355
 356         if (tlb_flag(TLB_WB))
 357                 dsb();
 358
 359         if (tlb_flag(TLB_V3_PAGE))
 360                 asm("mcr p15, 0, %0, c6, c0, 0" : : "r" (kaddr) : "cc");
 361         if (tlb_flag(TLB_V4_U_PAGE))
 362                 asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
 363         if (tlb_flag(TLB_V4_D_PAGE))
 364                 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
 365         if (tlb_flag(TLB_V4_I_PAGE))
 366                 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
 367         if (!tlb_flag(TLB_V4_I_PAGE) && tlb_flag(TLB_V4_I_FULL))
 368                 asm("mcr p15, 0, %0, c8, c5, 0" : : "r" (zero) : "cc");
 369
 370         if (tlb_flag(TLB_V6_U_PAGE))
 371                 asm("mcr p15, 0, %0, c8, c7, 1" : : "r" (kaddr) : "cc");
 372         if (tlb_flag(TLB_V6_D_PAGE))
 373                 asm("mcr p15, 0, %0, c8, c6, 1" : : "r" (kaddr) : "cc");
 374         if (tlb_flag(TLB_V6_I_PAGE))
 375                 asm("mcr p15, 0, %0, c8, c5, 1" : : "r" (kaddr) : "cc");
 376
 377         if (tlb_flag(TLB_V6_I_FULL | TLB_V6_D_FULL |
 378                      TLB_V6_I_PAGE | TLB_V6_D_PAGE |
 379                      TLB_V6_I_ASID | TLB_V6_D_ASID)) {
 380                 /* flush the branch target cache */
 381                 asm("mcr p15, 0, %0, c7, c5, 6" : : "r" (zero) : "cc");
 382                 dsb();
 383                 isb();
 384         }
 385 }
 386
 387 /*
 388  *      flush_pmd_entry
 389  *
 390  *      Flush a PMD entry (word aligned, or double-word aligned) to
 391  *      RAM if the TLB for the CPU we are running on requires this.
 392  *      This is typically used when we are creating PMD entries.
 393  *
 394  *      clean_pmd_entry
 395  *
 396  *      Clean (but don't drain the write buffer) if the CPU requires
 397  *      these operations.  This is typically used when we are removing
 398  *      PMD entries.
 399  */
 400 static inline void flush_pmd_entry(pmd_t *pmd)
 401 {
 402         const unsigned int __tlb_flag = __cpu_tlb_flags;
 403
 404         if (tlb_flag(TLB_DCLEAN))
 405                 asm("mcr        p15, 0, %0, c7, c10, 1  @ flush_pmd"
 406                         : : "r" (pmd) : "cc");
 407         if (tlb_flag(TLB_WB))
 408                 dsb();
 409 }
 410
 411 static inline void clean_pmd_entry(pmd_t *pmd)
 412 {
 413         const unsigned int __tlb_flag = __cpu_tlb_flags;
 414
 415         if (tlb_flag(TLB_DCLEAN))
 416                 asm("mcr        p15, 0, %0, c7, c10, 1  @ flush_pmd"
 417                         : : "r" (pmd) : "cc");
 418 }
 419
 420 #undef tlb_flag
 421 #undef always_tlb_flags
 422 #undef possible_tlb_flags
 423
 424 /*
 425  * Convert calls to our calling convention.
 426  */
 427 #define local_flush_tlb_range(vma,start,end)    __cpu_flush_user_tlb_range(start,end,vma)
 428 #define local_flush_tlb_kernel_range(s,e)       __cpu_flush_kern_tlb_range(s,e)
 429
 430 #ifndef CONFIG_SMP
 431 #define flush_tlb_all           local_flush_tlb_all
 432 #define flush_tlb_mm            local_flush_tlb_mm
 433 #define flush_tlb_page          local_flush_tlb_page
 434 #define flush_tlb_kernel_page   local_flush_tlb_kernel_page
 435 #define flush_tlb_range         local_flush_tlb_range
 436 #define flush_tlb_kernel_range  local_flush_tlb_kernel_range
 437 #else
 438 extern void flush_tlb_all(void);
 439 extern void flush_tlb_mm(struct mm_struct *mm);
 440 extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long uaddr);
 441 extern void flush_tlb_kernel_page(unsigned long kaddr);
 442 extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end);
 443 extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
 444 #endif
 445
 446 /*
 447  * if PG_dcache_dirty is set for the page, we need to ensure that any
 448  * cache entries for the kernels virtual memory range are written
 449  * back to the page.
 450  */
 451 extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte_t pte);
 452
 453 /*
 454  * ARM processors do not cache TLB tables in RAM.
 455  */
 456 #define flush_tlb_pgtables(mm,start,end)        do { } while (0)
 457
 458 #endif
 459
 460 #endif /* CONFIG_MMU */
 461
 462 #endif