include/asm-blackfin/bfin5xx_spi.h

   1 /************************************************************
   2 *
   3 * Copyright (C) 2004, Analog Devices. All Rights Reserved
   4 *
   5 * FILE bfin5xx_spi.h
   6 * PROGRAMMER(S): Luke Yang (Analog Devices Inc.)
   7 *
   8 *
   9 * DATE OF CREATION: March. 10th 2006
  10 *
  11 * SYNOPSIS:
  12 *
  13 * DESCRIPTION: header file for SPI controller driver for Blackfin5xx.
  14 **************************************************************
  15
  16 * MODIFICATION HISTORY:
  17 * March 10, 2006  bfin5xx_spi.h Created. (Luke Yang)
  18
  19 ************************************************************/
  20
  21 #ifndef _SPI_CHANNEL_H_
  22 #define _SPI_CHANNEL_H_
  23
  24 #define SPI0_REGBASE       0xffc00500
  25
  26 #define SPI_READ              0
  27 #define SPI_WRITE             1
  28
  29 #define SPI_CTRL_OFF            0x0
  30 #define SPI_FLAG_OFF            0x4
  31 #define SPI_STAT_OFF            0x8
  32 #define SPI_TXBUFF_OFF          0xc
  33 #define SPI_RXBUFF_OFF          0x10
  34 #define SPI_BAUD_OFF            0x14
  35 #define SPI_SHAW_OFF            0x18
  36
  37 #define CMD_SPI_OUT_ENABLE    1
  38 #define CMD_SPI_SET_BAUDRATE  2
  39 #define CMD_SPI_SET_POLAR     3
  40 #define CMD_SPI_SET_PHASE     4
  41 #define CMD_SPI_SET_MASTER    5
  42 #define CMD_SPI_SET_SENDOPT   6
  43 #define CMD_SPI_SET_RECVOPT   7
  44 #define CMD_SPI_SET_ORDER     8
  45 #define CMD_SPI_SET_LENGTH16  9
  46 #define CMD_SPI_GET_STAT      11
  47 #define CMD_SPI_GET_CFG       12
  48 #define CMD_SPI_SET_CSAVAIL   13
  49 #define CMD_SPI_SET_CSHIGH    14        /* CS unavail */
  50 #define CMD_SPI_SET_CSLOW     15        /* CS avail */
  51 #define CMD_SPI_MISO_ENABLE   16
  52 #define CMD_SPI_SET_CSENABLE  17
  53 #define CMD_SPI_SET_CSDISABLE 18
  54
  55 #define CMD_SPI_SET_TRIGGER_MODE  19
  56 #define CMD_SPI_SET_TRIGGER_SENSE 20
  57 #define CMD_SPI_SET_TRIGGER_EDGE  21
  58 #define CMD_SPI_SET_TRIGGER_LEVEL 22
  59
  60 #define CMD_SPI_SET_TIME_SPS      23
  61 #define CMD_SPI_SET_TIME_SAMPLES  24
  62 #define CMD_SPI_GET_SYSTEMCLOCK   25
  63
  64 #define CMD_SPI_SET_WRITECONTINUOUS     26
  65 #define CMD_SPI_SET_SKFS                27
  66
  67 #define CMD_SPI_GET_ALLCONFIG 32        /* For debug */
  68
  69 #define SPI_DEFAULT_BARD    0x0100
  70
  71 #define SPI0_IRQ_NUM        IRQ_SPI
  72 #define SPI_ERR_TRIG       -1
  73
  74 #define BIT_CTL_ENABLE      0x4000
  75 #define BIT_CTL_OPENDRAIN   0x2000
  76 #define BIT_CTL_MASTER      0x1000
  77 #define BIT_CTL_POLAR       0x0800
  78 #define BIT_CTL_PHASE       0x0400
  79 #define BIT_CTL_BITORDER    0x0200
  80 #define BIT_CTL_WORDSIZE    0x0100
  81 #define BIT_CTL_MISOENABLE  0x0020
  82 #define BIT_CTL_RXMOD       0x0000
  83 #define BIT_CTL_TXMOD       0x0001
  84 #define BIT_CTL_TIMOD_DMA_TX 0x0003
  85 #define BIT_CTL_TIMOD_DMA_RX 0x0002
  86 #define BIT_CTL_SENDOPT     0x0004
  87 #define BIT_CTL_TIMOD       0x0003
  88
  89 #define BIT_STAT_SPIF       0x0001
  90 #define BIT_STAT_MODF       0x0002
  91 #define BIT_STAT_TXE        0x0004
  92 #define BIT_STAT_TXS        0x0008
  93 #define BIT_STAT_RBSY       0x0010
  94 #define BIT_STAT_RXS        0x0020
  95 #define BIT_STAT_TXCOL      0x0040
  96 #define BIT_STAT_CLR        0xFFFF
  97
  98 #define BIT_STU_SENDOVER    0x0001
  99 #define BIT_STU_RECVFULL    0x0020
 100
 101 #define CFG_SPI_ENABLE      1
 102 #define CFG_SPI_DISABLE     0
 103
 104 #define CFG_SPI_OUTENABLE   1
 105 #define CFG_SPI_OUTDISABLE  0
 106
 107 #define CFG_SPI_ACTLOW      1
 108 #define CFG_SPI_ACTHIGH     0
 109
 110 #define CFG_SPI_PHASESTART  1
 111 #define CFG_SPI_PHASEMID    0
 112
 113 #define CFG_SPI_MASTER      1
 114 #define CFG_SPI_SLAVE       0
 115
 116 #define CFG_SPI_SENELAST    0
 117 #define CFG_SPI_SENDZERO    1
 118
 119 #define CFG_SPI_RCVFLUSH    1
 120 #define CFG_SPI_RCVDISCARD  0
 121
 122 #define CFG_SPI_LSBFIRST    1
 123 #define CFG_SPI_MSBFIRST    0
 124
 125 #define CFG_SPI_WORDSIZE16  1
 126 #define CFG_SPI_WORDSIZE8   0
 127
 128 #define CFG_SPI_MISOENABLE   1
 129 #define CFG_SPI_MISODISABLE  0
 130
 131 #define CFG_SPI_READ      0x00
 132 #define CFG_SPI_WRITE     0x01
 133 #define CFG_SPI_DMAREAD   0x02
 134 #define CFG_SPI_DMAWRITE  0x03
 135
 136 #define CFG_SPI_CSCLEARALL  0
 137 #define CFG_SPI_CHIPSEL1    1
 138 #define CFG_SPI_CHIPSEL2    2
 139 #define CFG_SPI_CHIPSEL3    3
 140 #define CFG_SPI_CHIPSEL4    4
 141 #define CFG_SPI_CHIPSEL5    5
 142 #define CFG_SPI_CHIPSEL6    6
 143 #define CFG_SPI_CHIPSEL7    7
 144
 145 #define CFG_SPI_CS1VALUE    1
 146 #define CFG_SPI_CS2VALUE    2
 147 #define CFG_SPI_CS3VALUE    3
 148 #define CFG_SPI_CS4VALUE    4
 149 #define CFG_SPI_CS5VALUE    5
 150 #define CFG_SPI_CS6VALUE    6
 151 #define CFG_SPI_CS7VALUE    7
 152
 153 /* device.platform_data for SSP controller devices */
 154 struct bfin5xx_spi_master {
 155         u16 num_chipselect;
 156         u8 enable_dma;
 157 };
 158
 159 /* spi_board_info.controller_data for SPI slave devices,
 160  * copied to spi_device.platform_data ... mostly for dma tuning
 161  */
 162 struct bfin5xx_spi_chip {
 163         u16 ctl_reg;
 164         u8 enable_dma;
 165         u8 bits_per_word;
 166         u8 cs_change_per_word;
 167         u8 cs_chg_udelay;
 168 };
 169
 170 #endif /* _SPI_CHANNEL_H_ */