include/asm-blackfin/bfin5xx_spi.h

   1 /************************************************************
   2 *
   3 * Copyright (C) 2004, Analog Devices. All Rights Reserved
   4 *
   5 * FILE bfin5xx_spi.h
   6 * PROGRAMMER(S): Luke Yang (Analog Devices Inc.)
   7 *
   8 *
   9 * DATE OF CREATION: March. 10th 2006
  10 *
  11 * SYNOPSIS:
  12 *
  13 * DESCRIPTION: header file for SPI controller driver for Blackfin5xx.
  14 **************************************************************
  15
  16 * MODIFICATION HISTORY:
  17 * March 10, 2006  bfin5xx_spi.h Created. (Luke Yang)
  18
  19 ************************************************************/
  20
  21 #ifndef _SPI_CHANNEL_H_
  22 #define _SPI_CHANNEL_H_
  23
  24 #define SPI_READ              0
  25 #define SPI_WRITE             1
  26
  27 #define SPI_CTRL_OFF            0x0
  28 #define SPI_FLAG_OFF            0x4
  29 #define SPI_STAT_OFF            0x8
  30 #define SPI_TXBUFF_OFF          0xc
  31 #define SPI_RXBUFF_OFF          0x10
  32 #define SPI_BAUD_OFF            0x14
  33 #define SPI_SHAW_OFF            0x18
  34
  35 #define CMD_SPI_OUT_ENABLE    1
  36 #define CMD_SPI_SET_BAUDRATE  2
  37 #define CMD_SPI_SET_POLAR     3
  38 #define CMD_SPI_SET_PHASE     4
  39 #define CMD_SPI_SET_MASTER    5
  40 #define CMD_SPI_SET_SENDOPT   6
  41 #define CMD_SPI_SET_RECVOPT   7
  42 #define CMD_SPI_SET_ORDER     8
  43 #define CMD_SPI_SET_LENGTH16  9
  44 #define CMD_SPI_GET_STAT      11
  45 #define CMD_SPI_GET_CFG       12
  46 #define CMD_SPI_SET_CSAVAIL   13
  47 #define CMD_SPI_SET_CSHIGH    14        /* CS unavail */
  48 #define CMD_SPI_SET_CSLOW     15        /* CS avail */
  49 #define CMD_SPI_MISO_ENABLE   16
  50 #define CMD_SPI_SET_CSENABLE  17
  51 #define CMD_SPI_SET_CSDISABLE 18
  52
  53 #define CMD_SPI_SET_TRIGGER_MODE  19
  54 #define CMD_SPI_SET_TRIGGER_SENSE 20
  55 #define CMD_SPI_SET_TRIGGER_EDGE  21
  56 #define CMD_SPI_SET_TRIGGER_LEVEL 22
  57
  58 #define CMD_SPI_SET_TIME_SPS      23
  59 #define CMD_SPI_SET_TIME_SAMPLES  24
  60 #define CMD_SPI_GET_SYSTEMCLOCK   25
  61
  62 #define CMD_SPI_SET_WRITECONTINUOUS     26
  63 #define CMD_SPI_SET_SKFS                27
  64
  65 #define CMD_SPI_GET_ALLCONFIG 32        /* For debug */
  66
  67 #define SPI_DEFAULT_BARD    0x0100
  68
  69 #define SPI0_IRQ_NUM        IRQ_SPI
  70 #define SPI_ERR_TRIG       -1
  71
  72 #define BIT_CTL_ENABLE      0x4000
  73 #define BIT_CTL_OPENDRAIN   0x2000
  74 #define BIT_CTL_MASTER      0x1000
  75 #define BIT_CTL_POLAR       0x0800
  76 #define BIT_CTL_PHASE       0x0400
  77 #define BIT_CTL_BITORDER    0x0200
  78 #define BIT_CTL_WORDSIZE    0x0100
  79 #define BIT_CTL_MISOENABLE  0x0020
  80 #define BIT_CTL_RXMOD       0x0000
  81 #define BIT_CTL_TXMOD       0x0001
  82 #define BIT_CTL_TIMOD_DMA_TX 0x0003
  83 #define BIT_CTL_TIMOD_DMA_RX 0x0002
  84 #define BIT_CTL_SENDOPT     0x0004
  85 #define BIT_CTL_TIMOD       0x0003
  86
  87 #define BIT_STAT_SPIF       0x0001
  88 #define BIT_STAT_MODF       0x0002
  89 #define BIT_STAT_TXE        0x0004
  90 #define BIT_STAT_TXS        0x0008
  91 #define BIT_STAT_RBSY       0x0010
  92 #define BIT_STAT_RXS        0x0020
  93 #define BIT_STAT_TXCOL      0x0040
  94 #define BIT_STAT_CLR        0xFFFF
  95
  96 #define BIT_STU_SENDOVER    0x0001
  97 #define BIT_STU_RECVFULL    0x0020
  98
  99 #define CFG_SPI_ENABLE      1
 100 #define CFG_SPI_DISABLE     0
 101
 102 #define CFG_SPI_OUTENABLE   1
 103 #define CFG_SPI_OUTDISABLE  0
 104
 105 #define CFG_SPI_ACTLOW      1
 106 #define CFG_SPI_ACTHIGH     0
 107
 108 #define CFG_SPI_PHASESTART  1
 109 #define CFG_SPI_PHASEMID    0
 110
 111 #define CFG_SPI_MASTER      1
 112 #define CFG_SPI_SLAVE       0
 113
 114 #define CFG_SPI_SENELAST    0
 115 #define CFG_SPI_SENDZERO    1
 116
 117 #define CFG_SPI_RCVFLUSH    1
 118 #define CFG_SPI_RCVDISCARD  0
 119
 120 #define CFG_SPI_LSBFIRST    1
 121 #define CFG_SPI_MSBFIRST    0
 122
 123 #define CFG_SPI_WORDSIZE16  1
 124 #define CFG_SPI_WORDSIZE8   0
 125
 126 #define CFG_SPI_MISOENABLE   1
 127 #define CFG_SPI_MISODISABLE  0
 128
 129 #define CFG_SPI_READ      0x00
 130 #define CFG_SPI_WRITE     0x01
 131 #define CFG_SPI_DMAREAD   0x02
 132 #define CFG_SPI_DMAWRITE  0x03
 133
 134 #define CFG_SPI_CSCLEARALL  0
 135 #define CFG_SPI_CHIPSEL1    1
 136 #define CFG_SPI_CHIPSEL2    2
 137 #define CFG_SPI_CHIPSEL3    3
 138 #define CFG_SPI_CHIPSEL4    4
 139 #define CFG_SPI_CHIPSEL5    5
 140 #define CFG_SPI_CHIPSEL6    6
 141 #define CFG_SPI_CHIPSEL7    7
 142
 143 #define CFG_SPI_CS1VALUE    1
 144 #define CFG_SPI_CS2VALUE    2
 145 #define CFG_SPI_CS3VALUE    3
 146 #define CFG_SPI_CS4VALUE    4
 147 #define CFG_SPI_CS5VALUE    5
 148 #define CFG_SPI_CS6VALUE    6
 149 #define CFG_SPI_CS7VALUE    7
 150
 151 /* device.platform_data for SSP controller devices */
 152 struct bfin5xx_spi_master {
 153         u16 num_chipselect;
 154         u8 enable_dma;
 155 };
 156
 157 /* spi_board_info.controller_data for SPI slave devices,
 158  * copied to spi_device.platform_data ... mostly for dma tuning
 159  */
 160 struct bfin5xx_spi_chip {
 161         u16 ctl_reg;
 162         u8 enable_dma;
 163         u8 bits_per_word;
 164         u8 cs_change_per_word;
 165         u8 cs_chg_udelay;
 166 };
 167
 168 #endif /* _SPI_CHANNEL_H_ */