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git.proxmox.com Git - mirror_ubuntu-zesty-kernel.git/blob - include/asm-frv/atomic.h
1 /* atomic.h: atomic operation emulation for FR-V
3 * For an explanation of how atomic ops work in this arch, see:
4 * Documentation/fujitsu/frv/atomic-ops.txt
6 * Copyright (C) 2004 Red Hat, Inc. All Rights Reserved.
7 * Written by David Howells (dhowells@redhat.com)
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License
11 * as published by the Free Software Foundation; either version
12 * 2 of the License, or (at your option) any later version.
17 #include <linux/types.h>
18 #include <asm/spr-regs.h>
25 * Atomic operations that C can't guarantee us. Useful for
26 * resource counting etc..
28 * We do not have SMP systems, so we don't have to deal with that.
31 /* Atomic operations are already serializing */
32 #define smp_mb__before_atomic_dec() barrier()
33 #define smp_mb__after_atomic_dec() barrier()
34 #define smp_mb__before_atomic_inc() barrier()
35 #define smp_mb__after_atomic_inc() barrier()
41 #define ATOMIC_INIT(i) { (i) }
42 #define atomic_read(v) ((v)->counter)
43 #define atomic_set(v, i) (((v)->counter) = (i))
45 #ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
46 static inline int atomic_add_return(int i
, atomic_t
*v
)
51 " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
53 " ld.p %M0,%1 \n" /* LD.P/ORCR must be atomic */
54 " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
56 " cst.p %1,%M0 ,cc3,#1 \n"
57 " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* clear ICC3.Z if store happens */
59 : "+U"(v
->counter
), "=&r"(val
)
61 : "memory", "cc7", "cc3", "icc3"
67 static inline int atomic_sub_return(int i
, atomic_t
*v
)
72 " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
74 " ld.p %M0,%1 \n" /* LD.P/ORCR must be atomic */
75 " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
77 " cst.p %1,%M0 ,cc3,#1 \n"
78 " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* clear ICC3.Z if store happens */
80 : "+U"(v
->counter
), "=&r"(val
)
82 : "memory", "cc7", "cc3", "icc3"
90 extern int atomic_add_return(int i
, atomic_t
*v
);
91 extern int atomic_sub_return(int i
, atomic_t
*v
);
95 static inline int atomic_add_negative(int i
, atomic_t
*v
)
97 return atomic_add_return(i
, v
) < 0;
100 static inline void atomic_add(int i
, atomic_t
*v
)
102 atomic_add_return(i
, v
);
105 static inline void atomic_sub(int i
, atomic_t
*v
)
107 atomic_sub_return(i
, v
);
110 static inline void atomic_inc(atomic_t
*v
)
112 atomic_add_return(1, v
);
115 static inline void atomic_dec(atomic_t
*v
)
117 atomic_sub_return(1, v
);
120 #define atomic_dec_return(v) atomic_sub_return(1, (v))
121 #define atomic_inc_return(v) atomic_add_return(1, (v))
123 #define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
124 #define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
125 #define atomic_inc_and_test(v) (atomic_add_return(1, (v)) == 0)
127 #ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
129 unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask
, volatile unsigned long *v
)
131 unsigned long old
, tmp
;
135 " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
137 " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */
138 " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
139 " and%I3 %1,%3,%2 \n"
140 " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */
141 " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */
143 : "+U"(*v
), "=&r"(old
), "=r"(tmp
)
145 : "memory", "cc7", "cc3", "icc3"
152 unsigned long atomic_test_and_OR_mask(unsigned long mask
, volatile unsigned long *v
)
154 unsigned long old
, tmp
;
158 " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
160 " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */
161 " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
163 " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */
164 " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */
166 : "+U"(*v
), "=&r"(old
), "=r"(tmp
)
168 : "memory", "cc7", "cc3", "icc3"
175 unsigned long atomic_test_and_XOR_mask(unsigned long mask
, volatile unsigned long *v
)
177 unsigned long old
, tmp
;
181 " orcc gr0,gr0,gr0,icc3 \n" /* set ICC3.Z */
183 " ld.p %M0,%1 \n" /* LD.P/ORCR are atomic */
184 " orcr cc7,cc7,cc3 \n" /* set CC3 to true */
185 " xor%I3 %1,%3,%2 \n"
186 " cst.p %2,%M0 ,cc3,#1 \n" /* if store happens... */
187 " corcc gr29,gr29,gr0 ,cc3,#1 \n" /* ... clear ICC3.Z */
189 : "+U"(*v
), "=&r"(old
), "=r"(tmp
)
191 : "memory", "cc7", "cc3", "icc3"
199 extern unsigned long atomic_test_and_ANDNOT_mask(unsigned long mask
, volatile unsigned long *v
);
200 extern unsigned long atomic_test_and_OR_mask(unsigned long mask
, volatile unsigned long *v
);
201 extern unsigned long atomic_test_and_XOR_mask(unsigned long mask
, volatile unsigned long *v
);
205 #define atomic_clear_mask(mask, v) atomic_test_and_ANDNOT_mask((mask), (v))
206 #define atomic_set_mask(mask, v) atomic_test_and_OR_mask((mask), (v))
208 /*****************************************************************************/
210 * exchange value with memory
212 #ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
214 #define xchg(ptr, x) \
216 __typeof__(ptr) __xg_ptr = (ptr); \
217 __typeof__(*(ptr)) __xg_orig; \
219 switch (sizeof(__xg_orig)) { \
223 : "+m"(*__xg_ptr), "=r"(__xg_orig) \
231 asm volatile("break"); \
240 extern uint32_t __xchg_32(uint32_t i
, volatile void *v
);
242 #define xchg(ptr, x) \
244 __typeof__(ptr) __xg_ptr = (ptr); \
245 __typeof__(*(ptr)) __xg_orig; \
247 switch (sizeof(__xg_orig)) { \
248 case 4: __xg_orig = (__typeof__(*(ptr))) __xchg_32((uint32_t) x, __xg_ptr); break; \
251 asm volatile("break"); \
259 #define tas(ptr) (xchg((ptr), 1))
261 /*****************************************************************************/
263 * compare and conditionally exchange value with memory
264 * - if (*ptr == test) then orig = *ptr; *ptr = test;
265 * - if (*ptr != test) then orig = *ptr;
267 #ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
269 #define cmpxchg(ptr, test, new) \
271 __typeof__(ptr) __xg_ptr = (ptr); \
272 __typeof__(*(ptr)) __xg_orig, __xg_tmp; \
273 __typeof__(*(ptr)) __xg_test = (test); \
274 __typeof__(*(ptr)) __xg_new = (new); \
276 switch (sizeof(__xg_orig)) { \
280 " orcc gr0,gr0,gr0,icc3 \n" \
281 " ckeq icc3,cc7 \n" \
283 " orcr cc7,cc7,cc3 \n" \
284 " sub%I4cc %1,%4,%2,icc0 \n" \
285 " bne icc0,#0,1f \n" \
286 " cst.p %3,%M0 ,cc3,#1 \n" \
287 " corcc gr29,gr29,gr0 ,cc3,#1 \n" \
288 " beq icc3,#0,0b \n" \
290 : "+U"(*__xg_ptr), "=&r"(__xg_orig), "=&r"(__xg_tmp) \
291 : "r"(__xg_new), "NPr"(__xg_test) \
292 : "memory", "cc7", "cc3", "icc3", "icc0" \
298 asm volatile("break"); \
307 extern uint32_t __cmpxchg_32(uint32_t *v
, uint32_t test
, uint32_t new);
309 #define cmpxchg(ptr, test, new) \
311 __typeof__(ptr) __xg_ptr = (ptr); \
312 __typeof__(*(ptr)) __xg_orig; \
313 __typeof__(*(ptr)) __xg_test = (test); \
314 __typeof__(*(ptr)) __xg_new = (new); \
316 switch (sizeof(__xg_orig)) { \
317 case 4: __xg_orig = __cmpxchg_32(__xg_ptr, __xg_test, __xg_new); break; \
320 asm volatile("break"); \
329 #define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
330 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
332 #define atomic_add_unless(v, a, u) \
335 c = atomic_read(v); \
336 while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
341 #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
343 #include <asm-generic/atomic.h>
344 #endif /* _ASM_ATOMIC_H */